Search results for "CHDL"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Sungho Kang, Stephen A. Szygenda	Automatic VHDL Model Generation System.	CHDL	1993	DBLP BibTeX RDF
1	Walling R. Cyre	Textual/Graphical Design Concept-Level Synthesis.	CHDL	1993	DBLP BibTeX RDF
1	Bran Selic	An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems.	CHDL	1993	DBLP BibTeX RDF
1	Klaus Schneider 0001, Ramayya Kumar, Thomas Kropf	Hardware-Verification using First Order BDDs.	CHDL	1993	DBLP BibTeX RDF
1	Bhaskar Bose, Steven D. Johnson, Shyamsundar Pullela	Integrating Boolean Verification with Formal Derivation.	CHDL	1993	DBLP BibTeX RDF
1	Wolfgang Glunz, Torsten Rössel	Checking DFT Rules with a VHDL Simulator.	CHDL	1993	DBLP BibTeX RDF
1	Ram Mandayam, Ranga Vemuri	Performance Specification and Measurement.	CHDL	1993	DBLP BibTeX RDF
1	Edmund M. Clarke	Automatic Verification of Sequential Circuit Designs.	CHDL	1993	DBLP BibTeX RDF
1	Roger P. Ang, Nikil D. Dutt	A Representation for the Binding of RT-Component Functionality to HDL Behavior.	CHDL	1993	DBLP BibTeX RDF
1	Edmund M. Clarke, Orna Grumberg, Hiromi Hiraishi, Somesh Jha, David E. Long, Kenneth L. McMillan, Linda A. Ness	Verification of the Futurebus+ Cache Coherence Protocol.	CHDL	1993	DBLP BibTeX RDF
1	Tamio Hoshino	UDL/I version Two: A New Horizon of HDL Standards.	CHDL	1993	DBLP BibTeX RDF
1	Wolfgang Glunz, Thomas Kruse, Torsten Rössel, Dieter Monjau	Integrating SDL and VHDL for System-Level Hardware Design.	CHDL	1993	DBLP BibTeX RDF
1	Zheng Zhu, Steven D. Johnson	Automatic Synthesis of Sequential Synchronizations.	CHDL	1993	DBLP BibTeX RDF
1	Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen	Parameterized VHDL Entities for the Simulation of Hybrid Circuits.	CHDL	1993	DBLP BibTeX RDF
1	David Agnew, Luc J. M. Claesen, Raul Camposano (eds.)	Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993	CHDL	1993	DBLP BibTeX RDF
1	J. W. Gambles, Phillip J. Windley	Reasoning about the VHDL Standard Logic Package Signal Data Type.	CHDL	1993	DBLP BibTeX RDF
1	Wolfgang Ecker, Sabine März	System-Level Specification and Design Using VHDL: A Case Study.	CHDL	1993	DBLP BibTeX RDF
1	Francisco Corella	Automated High-level Verification Against Clocked Algorithmic Specifications.	CHDL	1993	DBLP BibTeX RDF
1	Paolo Camurati, Fulvio Corno, Paolo Prinetto	Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation.	CHDL	1993	DBLP BibTeX RDF
1	Felice Balarin, Gary York	Verilog HDL Modeling Styles for Formal Verification.	CHDL	1993	DBLP BibTeX RDF
1	Ahmed Amine Jerraya, Kevin O'Brien, Tarek Ben Ismail	Linking System Design Tools and Hardware Design Tools.	CHDL	1993	DBLP BibTeX RDF
1	John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark D. Aagaard	HML: A Hardware Description Language Based on Standard ML.	CHDL	1993	DBLP BibTeX RDF
1	Robin Sharp, Ole Rasmussen	Transformational Rewriting with Ruby.	CHDL	1993	DBLP BibTeX RDF
1	Karen C. Davis	A Denotational Definition of the VHDL Simulation Kernel.	CHDL	1993	DBLP BibTeX RDF
1	Laurence Pierre	VHDL Description and Formal Verification of Systolic Multipliers.	CHDL	1993	DBLP BibTeX RDF
1	Balraj Singh, John R. Wicks, Philip Wright, James R. Armstrong	The Modeler's Assistant: A CAD Tool for Behavioral Model Development.	CHDL	1993	DBLP BibTeX RDF
1	C. Norris Ip, David L. Dill	Better Verification Through Symmetry.	CHDL	1993	DBLP BibTeX RDF
1	Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar	Insulin: An Instruction Set Simulation Environment.	CHDL	1993	DBLP BibTeX RDF
1	Mario Barbacci	Real Time Distributed Systems.	CHDL	1993	DBLP BibTeX RDF
1	Klaus Buchenrieder, Alexander Sedlmeier, Christian Veith	HW/SW Co-Design with PRAMs Using CoDES.	CHDL	1993	DBLP BibTeX RDF
1	Eric J. Golin, Annette C. Feng	A Visual Hardware Description Language.	CHDL	1993	DBLP BibTeX RDF
1	Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt	Integrating Behavior and Timing in Executable Specifications.	CHDL	1993	DBLP BibTeX RDF
1	Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai	Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models.	CHDL	1993	DBLP BibTeX RDF
1	Dominique Rodriguez	Analog-VHDL: As an Application, a Real Example.	CHDL	1993	DBLP BibTeX RDF
1	Michel Allemand	A Rewriting Based Method for the Formal Verification of Microprocessors.	CHDL	1993	DBLP BibTeX RDF
1	Xing-Jian Xu, Mitsuru Ishizuka	An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area.	CHDL	1993	DBLP BibTeX RDF
1	Flávio Rech Wagner	Prevail-DM: A Framework-Based Environment for Formal Hardware Verification.	CHDL	1993	DBLP BibTeX RDF
1	Mohammed Faci, Luigi Logrippo	Specifying Hardware Systems in LOTOS.	CHDL	1993	DBLP BibTeX RDF
1	Alan Dent, Keith Hanna	Reasoning about Array Structure Using a Dependently Typed Logic.	CHDL	1993	DBLP BibTeX RDF
1	Stefan Krischer	The Backward Walk Approach in FSM Verification.	CHDL	1993	DBLP BibTeX RDF
1	Tam Anh Chu, Huy T. Cao, Clement K. C. Leung	ESP: An Executable Specification Language for Mixed Timing Control Circuits.	CHDL	1993	DBLP BibTeX RDF
1	Gregor von Bochmann	Specification Languages for Communication Protocols.	CHDL	1993	DBLP BibTeX RDF
1	Kamlesh Rath, Steven D. Johnson	Toward a Basis for Protocol Specification and Process Decomposition.	CHDL	1993	DBLP BibTeX RDF

Publications at "CHDL"( http://dblp.L3S.de/Venues/CHDL )