Search results for "IFMT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ahmed El-Mahdy 0002, Hisham El-Shishiny	Efficient parallel selective separable-kernel convolution on heterogeneous processors.	IFMT	2010	DBLP DOI BibTeX RDF
1	Augusto Vega, Alejandro Rico, Felipe Cabarcas, Alex Ramírez, Mateo Valero	Comparing last-level cache designs for CMP architectures.	IFMT	2010	DBLP DOI BibTeX RDF
1	Junli Gu, Rakesh Kumar 0002, Steven S. Lumetta, Yihe Sun	Accelerating data movement on future chip multi-processors.	IFMT	2010	DBLP DOI BibTeX RDF
1	Nicolas Ventroux, Raphaël David	SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications.	IFMT	2010	DBLP DOI BibTeX RDF
1	Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero	Power and performance aware reconfigurable cache for CMPs.	IFMT	2010	DBLP DOI BibTeX RDF
1	Abdullah Kayi, Tarek A. El-Ghazawi	An adaptive cache coherence protocol for chip multiprocessors.	IFMT	2010	DBLP DOI BibTeX RDF
1	Anurag Negi, M. M. Waliullah, Per Stenström	LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems.	IFMT	2010	DBLP DOI BibTeX RDF
1	István Lorentz, Mihaela Malita, Razvan Andonie	Fitting FFT onto an energy efficient massively parallel architecture.	IFMT	2010	DBLP DOI BibTeX RDF
1	Hisham El-Shishiny, Erven Rohou (eds.)	Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, IFMT '10, Saint-Malo, France, June 19, 2010	IFMT	2010	DBLP DOI BibTeX RDF
1	Tianzhou Chen, Jiangwei Huang, Lingxiang Xiang, Qingsong Shi	Dynamic power management framework for multi-core portable embedded system.	IFMT	2008	DBLP DOI BibTeX RDF	embedded system, power management, DVS, multi-core
1	Hai Jin 0001, Wenzhi Cao, Pingpeng Yuan, Xia Xie	VSCBenchmark: benchmark for dynamic server performance of virtualization technology.	IFMT	2008	DBLP DOI BibTeX RDF	dynamic performance, benchmark, virtual machines, server consolidation
1	Rosilde Corvino, Stéphane Mancini, Roberto Guizzetti	Automatic generation of a parallel tile processing unit for algorithms with non-affine array references.	IFMT	2008	DBLP DOI BibTeX RDF	computations scheduling, design space exploration (DSE), non-affine array references, super-tiling, mapping, high-level synthesis (HLS), tiling
1	Ahmed El-Mahdy 0002, Hisham El-Shishiny	An efficient load-balancing algorithm for image processing applications on multicore processors.	IFMT	2008	DBLP DOI BibTeX RDF	load balancing, parallel computing, fractals, curve fitting, statistical sampling, cell BE
1	Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh	On the potential of latency tolerant execution in speculative multithreading.	IFMT	2008	DBLP DOI BibTeX RDF	latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors
1	Duc Vianney, Gadi Haber, Andre Heilper, Marcel Zalmanovici	Performance analysis and visualization tools for cell/B.E. multicore environment.	IFMT	2008	DBLP DOI BibTeX RDF	Euler based particle simulation, code analyzer, control flow analyzer, counter analyzer, pipeline analyzer, profile analyzer, trace analyzer, virtual performance analyzer, cell broadband engine
1	Peter Bertels, Wim Heirman, Dirk Stroobandt	Efficient measurement of data flow enabling communication-aware parallelisation.	IFMT	2008	DBLP DOI BibTeX RDF	profiling, data-flow
1	Mohamed F. Ahmed, Reda A. Ammar, Sanguthevar Rajasekaran	SPENK: adding another level of parallelism on the cell broadband engine.	IFMT	2008	DBLP DOI BibTeX RDF	embedded parallelism, micro-threads, cell broadband engine
1	Murthy Durbhakula	Sharing-aware OS scheduling algorithms for multi-socket multi-core servers.	IFMT	2008	DBLP DOI BibTeX RDF	cache-to-cache transfers, scheduling algorithms
1	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
1	Amr M. Bayoumi, Yasser Y. Hanafy	Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures.	IFMT	2008	DBLP DOI BibTeX RDF	BSIM, parallel computing, graphics processing units, GPGPU, SIMD, SPICE, manycore
1	Ali El-Moursy, Ahmed El-Mahdy 0002, Hisham El-Shishiny	An efficient in-place 3D transpose for multicore processors with software managed memory hierarchy.	IFMT	2008	DBLP DOI BibTeX RDF	3D transpose, vector programming, parallel programming, SIMD, multi-core systems
1	Ahmed A. Morgan, Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali	Application-specific networks-on-chip topology customization using network partitioning.	IFMT	2008	DBLP DOI BibTeX RDF	application-specific networks-on-chip (ASNoC), core graph, optimization, analysis, topology, network partitioning
1	John E. Savage, Mohammad Zubair	A unified model for multicore architectures.	IFMT	2008	DBLP DOI BibTeX RDF	multicore, memory hierarchy

Publications at "IFMT"( http://dblp.L3S.de/Venues/IFMT )