Search results for "IOLTW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Daniele Rossi 0001, Cecilia Metra, Bruno Riccò	Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto	Automated Synthesis of SEU Tolerant Architectures from OO Descriptions.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Bartomeu Alorda, André Ivanov, Jaume Segura 0001	An Off-Chip Sensor Circuit for On-Line Transient Current Testing.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley	A High Speed Encoder for Recursive Systematic Convolutive Codes.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra	Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Huy Nguyen 0001, Abhijit Chatterjee	Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Luca Schiano, Cecilia Metra, Diego Marino	Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Ari Virtanen	Radiation Effects Facility RADEF.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Naotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui	Learning-Based On-Line Testing in Feedforward Neural Networks.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Petros Oikonomakos, Mark Zwolinski	Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Parag K. Lala, B. Kiran Kumar	An Architecture for Self-Healing Digital Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Aleksandra Rankov, Gaynor E. Taylor, John Webster	Robust Data Compression for Analogue Test Outputs.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka	Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Anzhela Yu. Matrosova, Valentina Andreeva, Yu. Sedov	Survivable Discrete Circuits Design.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis	Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda	A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.	IOLTW	2002	DBLP DOI BibTeX RDF
1	D. Bied-Charreton, D. Guillon, B. Jacques	The YATE Fail-Safe Interface: The User's Point of View.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Carlo Dallavalle	Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus	On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Mohammad A. Naal, M. Rakotoar, Emmanuel Simeu, Chouki Aktouf	Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Adam Kristof	On-Line Detection of Short Circuits in Digital Devices and Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	Analysis of the Equivalences and Dominances of Transient Faults at the RT Level.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Bernard Coloma, Patrick Delaunay, Olivier Husson	High Speed 15 ns 4 Mbits SRAM for Space Application.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker 0001	Sequential n -Detection Criteria: Keep It Simple.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin	Sequential Circuits Applicable for Detecting Different Types of Faults.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Code-Disjoint Carry-Skip Adder.	IOLTW	2002	DBLP DOI BibTeX RDF
1	N. Axelos, J. Watson, D. Taylor, A. Platts	Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response Testing.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Gian Carlo Cardarilli, F. Kaddour, A. Leandri, Marco Ottavi, Salvatore Pontarelli, Raoul Velazco	Bit Flip Injection in Processor-Based Architectures: A Case Study.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Feng Gao 0017, John P. Hayes	On-Line Monitor Design of Finite-State Machines.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Giuseppe Di Gregorio, Maria Grazia La Rosa, Biagio Russo	Checkers for RF Matching Networks on an Automatic Test Board.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto	A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis	Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Joan Font, J. Ginard, Eugeni Isern 0001, Miquel Roca 0001, Jaume Segura 0001, Eugenio García	A BICS for CMOS Opamps by Monitoring the Supply Current Peak.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Valery A. Vardanian, Yervant Zorian	A March-Based Fault Location Algorithm for Static Random Access Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Analysis of SEU Effects in a Pipelined Processor.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus	On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Alvin Jee	Defect-Oriented Analysis of Memory BIST Tests.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Emmanuel Rondey, Yann Tellier, Simone Borri	A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Chouki Aktouf, Benoît Pannetier, Pierre Lemaître-Auger, Smail Tedjini	On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology.	IOLTW	2002	DBLP DOI BibTeX RDF
1		8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France	IOLTW	2002	DBLP BibTeX RDF
1	Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira 0001	Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing.	IOLTW	2002	DBLP DOI BibTeX RDF
1	F. Kaddour, Sana Rezgui, Raoul Velazco, S. Rodriguez, J. R. De Mingo	Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker 0001	Stop & Go BIST.	IOLTW	2002	DBLP DOI BibTeX RDF	Thermal constraints, BIST, Delay testing, IP cores
1	Jose Miguel Vieira dos Santos	Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells.	IOLTW	2002	DBLP DOI BibTeX RDF	Sequential logic, Dependability, DFT, BST
1	Alberto Manzone, Diego De Costantini	Fault Tolerant Insertion and Verification: A Case Study.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Dimitri Kagaris	Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF	simulation, memory testing, embedded memory, redundancy analysis, memory repair
1	Régis Leveugle, K. Hadjiat	Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study.	IOLTW	2002	DBLP DOI BibTeX RDF	VHDL, fault injection, VLSI design, dependability analysis
1	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	A Statistical Sampler for a New On-line Analog Test Method.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis	A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Chouki Aktouf	On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance Evaluation.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil	A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Emmanuel Simeu, Ahmad Abdelhay	A Robust Fault Detection Scheme for Concurrent Testing of Linear Digital Systems.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Zan Yang, Gwan Choi	An On-Line Testing Approach Using Code-Perturbation.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Isabel González, Luis Berrojo	Supporting Fault Tolerance in an Industrial Environment: The AMATISTA Approach.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui, Kazuharu Yamato	On-Line Multiple-Fault-Detection of Fuzzy Controllers.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Richard P. Kleihorst, Nico F. Benschop	Fault Tolerant ICs by Area-Optimized Error Correcting Codes.	IOLTW	2001	DBLP DOI BibTeX RDF
1	José Luis Merino, Sebastià A. Bota, A. Herms, Josep Samitier, Enric Cabruja, Xavier Jordà, Miquel Vellvehí, J. Bausells, A. Ferré, J. Bigorra	Smart Temperature Sensor for On-Line Monitoring in Automotive Applications.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo	Logic Optimization of Unidirectional Circuits with Structural Methods.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Jose Miguel Vieira dos Santos	TRACS-TRansient Activity Checking with Scan Cells.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir	Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Anzhela Yu. Matrosova, K. Nikitin, Olga Goloubeva	Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation.	IOLTW	2001	DBLP DOI BibTeX RDF
1		7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy	IOLTW	2001	DBLP BibTeX RDF
1	Michael Böhnel, Reinhold Weiss	Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Dhiraj K. Pradhan	Logic Insertion to Speed-Up Logic Verification: A Recent Development.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos	On the Design of Self-Testing Checkers for Modified Berger Codes.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Dimitri Kagaris, Spyros Tragoudas	Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Piotr Gawkowski, Janusz Sosnowski	Analyzing Fault Effects in Fault Insertion Experiments.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Andrzej Krasniewski	Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra	Novel Fault-Tolerant Adder Design for FPGA-Based Systems.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert	On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Parag K. Lala, Mark G. Karpovsky	An Approach for Designing On-Line Testable State Machines.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Bogdan Nicolescu, Raoul Velazco, Matteo Sonza Reorda	Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Luis Entrena, Celia López, Emilio Olías	Automatic Insertion of Fault-Tolerant Structures at the RT Level.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton	Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New Approach to Design Reliable Real-Time Speech Recognition Systems.	IOLTW	2001	DBLP DOI BibTeX RDF	HW-SW Codesign, Digital Signal Processing - DSP, Speech-Recognition Systems, Fault-Tolerance Techniques, Transparent BIST, Performance Degradation, Area overhead
1	Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto	Reliability Properties Assessment at System Level: A Co-design Framework.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Michele Favalli, Cecilia Metra	Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Octavian Petre, Hans G. Kerkhoff	Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Alberto Manzone, Alessandro Pincetti, Diego De Costantini	Fault Tolerant Automotive Systems: An Overview.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Matthias Pflanz, Karsten Walther, Heinrich Theodor Vierhaus	On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Fabio Salice, Donatella Sciuto	Designing Reliable Embedded Systems Based on 32 Bit Microprocessors.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	A New Reseeding Technique for LFSR-Based Test Pattern Generation.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Dean Lewis, Hervé Lapuyade, Yann Deval, Yvan Maidon, Frédéric Darracq, Renaud Briand, Pascal Fouillat	A New Laser System for X-Rays Flashes Sensitivity Evaluation.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Xiaodong Zhang 0010, Kaushik Roy 0001	Power Constrained Test Scheduling with Low Power Weighted Random Testing.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou	Concurrent Detection of Soft Errors Based on Current Monitoring.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Ashish Syal, Victor Lee, André Ivanov, Josep Altet	CMOS Differential and Absolute Thermal Sensors.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto	Validation of a Software Dependability Tool via Fault Injection Experiments.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Ondrej Novák, Jiri Nosek	Test-per-Clock Testing of the Circuits with Scan.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Fabrice Monteiro, Abbas Dandache, Bernard Lepley	Fast Configurable Polynomial Division for Error Control Coding Applications.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Cristoforo Marzocca, Francesco Corsi	Mixed-Signal Circuit Classification in a Pseudorandom Testing Scheme.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Joakim Aidemark, Peter Folkesson, Johan Karlsson	Path-Based Error Coverage Prediction.	IOLTW	2001	DBLP DOI BibTeX RDF

Publications at "IOLTW"( http://dblp.L3S.de/Venues/IOLTW )