Search results for "SASP"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Liang Chen, Nicolas Boichat, Tulika Mitra	Customized MPSoC synthesis for task sequence.	SASP	2011	DBLP DOI BibTeX RDF
1	Anthony Chun, Jenny X. Chang, Zhen Fang, Ravishankar R. Iyer 0001, Michael Deisher	ISIS: An accelerator for Sphinx speech recognition.	SASP	2011	DBLP DOI BibTeX RDF
1		IEEE 9th Symposium on Application Specific Processors, SASP 2011, San Diego, CA, USA, June 5-6, 2011	SASP	2011	DBLP BibTeX RDF
1	Guohui Wang, Michael Wu 0001, Yang Sun 0001, Joseph R. Cavallaro	A massively parallel implementation of QC-LDPC decoder on GPU.	SASP	2011	DBLP DOI BibTeX RDF
1	Tom Vander Aa, Martin Palkovic, Matthias Hartmann, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre	A multi-threaded coarse-grained array processor for wireless baseband.	SASP	2011	DBLP DOI BibTeX RDF
1	Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration.	SASP	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Muhuan Huang, Yi Zou	3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications.	SASP	2011	DBLP DOI BibTeX RDF
1	Sergey Morozov 0001, Christian Tergino, Patrick Schaumont	System integration of Elliptic Curve Cryptography on an OMAP platform.	SASP	2011	DBLP DOI BibTeX RDF
1	Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout	How sensitive is processor customization to the workload's input datasets?	SASP	2011	DBLP DOI BibTeX RDF
1	Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	ARTE: An Application-specific Run-Time management framework for multi-core systems.	SASP	2011	DBLP DOI BibTeX RDF
1	Bo Zhou 0018, Xiaobo Sharon Hu, Danny Z. Chen	Memory-efficient volume ray tracing on GPU for radiotherapy.	SASP	2011	DBLP DOI BibTeX RDF
1	Rishvanth Kora Venugopal, J. Robert Heath, Daniel L. Lau	FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm.	SASP	2011	DBLP DOI BibTeX RDF
1	Adarsha Rao, S. K. Nandy 0001, Hristo Nikolov, Ed F. Deprettere	USHA: Unified software and hardware architecture for video decoding.	SASP	2011	DBLP DOI BibTeX RDF
1	Chen Huang 0005, Frank Vahid	Scalable object detection accelerators on FPGAs using custom design space exploration.	SASP	2011	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu	Integrating formal verification and high-level processor pipeline synthesis.	SASP	2011	DBLP DOI BibTeX RDF
1	Naim Harb, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Rabie Ben Atitallah	Dynamically reconfigurable architecture for a driver assistant system.	SASP	2011	DBLP DOI BibTeX RDF
1	Roto Le, R. Iris Bahar, Joseph L. Mundy	A novel parallel Tier-1 coder for JPEG2000 using GPUs.	SASP	2011	DBLP DOI BibTeX RDF
1	David Kesler, Biplab Deka, Rakesh Kumar 0002	A hardware acceleration technique for gradient descent and conjugate gradient.	SASP	2011	DBLP DOI BibTeX RDF
1	Abhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar, Hans Peter Graf	A parallel accelerator for semantic search.	SASP	2011	DBLP DOI BibTeX RDF
1	Muhammad Shafiq 0003, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	TARCAD: A template architecture for reconfigurable accelerator designs.	SASP	2011	DBLP DOI BibTeX RDF
1	Hongjian Li, Bing Ni, Man Hon Wong 0001, Kwong-Sak Leung	A fast CUDA implementation of agrep algorithm for approximate nucleotide sequence matching.	SASP	2011	DBLP DOI BibTeX RDF
1	Shuo-Hung Chen, Hsiao-Mei Lin, Hsin-Wen Wei, Yi-Cheng Chen, Chih-Tsun Huang, Yeh-Ching Chung	Hardware/software co-designed accelerator for vector graphics applications.	SASP	2011	DBLP DOI BibTeX RDF
1	Amin Farmahini Farahani, Anthony E. Gregerson, Michael J. Schulte, Katherine Compton	Modular high-throughput and low-latency sorting units for FPGAs in the Large Hadron Collider.	SASP	2011	DBLP DOI BibTeX RDF
1	Yi Shan, Tianji Wu, Yu Wang 0002, Bo Wang 0067, Zilong Wang, Ningyi Xu, Huazhong Yang	FPGA and GPU implementation of large scale SpMV.	SASP	2010	DBLP DOI BibTeX RDF
1	Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu	Efficient design and generation of a multi-facet arbiter.	SASP	2010	DBLP DOI BibTeX RDF
1	Ruby B. Lee, Yu-Yuan Chen	Processor accelerator for AES.	SASP	2010	DBLP DOI BibTeX RDF
1	Ahmed O. El-Rayis, Tughrul Arslan, Ahmet T. Erdogan	A processing engine for GPS correlation.	SASP	2010	DBLP DOI BibTeX RDF
1	Jelena Trajkovic, Daniel D. Gajski	Early performance-cost estimation of application-specific data path pipelining.	SASP	2010	DBLP DOI BibTeX RDF
1	Jason Loew, Dmitry Ponomarev 0001, Patrick H. Madden	Customized architectures for faster route finding in GPS-based navigation systems.	SASP	2010	DBLP DOI BibTeX RDF
1	Pei Liu 0003, Ahmed Hemani	A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics.	SASP	2010	DBLP DOI BibTeX RDF
1	Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Minimizing write activities to non-volatile memory via scheduling and recomputation.	SASP	2010	DBLP DOI BibTeX RDF
1	Antonino Tumeo, Oreste Villa	Accelerating DNA analysis applications on GPU clusters.	SASP	2010	DBLP DOI BibTeX RDF
1	Ji Kong, Peilin Liu, Xianmin Chen, Jin Wang, Xingguang Pan, Jun Wang, He Xiao, Zhenqi Wei, Rendong Ying	Next-generation consumer audio application specific embedded processor.	SASP	2010	DBLP DOI BibTeX RDF
1	Mathew Paul, Peter Petrov	I-cache configurability for temperature reduction through replicated cache partitioning.	SASP	2010	DBLP DOI BibTeX RDF
1	Michael Steffen, Joseph Zambreno	A hardware pipeline for accelerating ray traversal algorithms on streaming processors.	SASP	2010	DBLP DOI BibTeX RDF
1	David Novo, Angeliki Kritikakou, Praveen Raghavan, Liesbet Van der Perre, Jos Huisken, Francky Catthoor	Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance.	SASP	2010	DBLP DOI BibTeX RDF
1	Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung	Reconfigurable custom functional unit generation and exploitation in multiple-issue processors.	SASP	2010	DBLP DOI BibTeX RDF
1	Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura	An RTOS in hardware for energy efficient software-based TCP/IP processing.	SASP	2010	DBLP DOI BibTeX RDF
1	Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev	A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices.	SASP	2010	DBLP DOI BibTeX RDF
1	Nicholas Moore, Miriam Leeser, Laurie A. Smith King	Efficient template matching with variable size templates in CUDA.	SASP	2010	DBLP DOI BibTeX RDF
1	Dan Upton, Kim M. Hazelwood	Design of a custom VEE core in a chip multiprocessor.	SASP	2010	DBLP DOI BibTeX RDF
1	Khodor Ahmad Fawaz, Tughrul Arslan, Sami Khawam, Mark Muir, Ioannis Nousias, Iain Lindsay, Ahmet T. Erdogan	A dynamically reconfigurable asynchronous processor.	SASP	2010	DBLP DOI BibTeX RDF
1		IEEE 8th Symposium on Application Specific Processors, SASP 2010, Anaheim, CA, USA, June 13-14, 2010	SASP	2010	DBLP BibTeX RDF
1	Dominik Auras, Sylvain Girbal, Hugues Berry, Olivier Temam, Sami Yehia	CMA: Chip multi-accelerator.	SASP	2010	DBLP DOI BibTeX RDF
1	Amin Ansari, Dan Zhang 0004, Scott A. Mahlke	Parade: A versatile parallel architecture for accelerating pulse train clustering.	SASP	2009	DBLP DOI BibTeX RDF
1	Nam Duong, Rakesh Kumar	Register Multimapping: A technique for reducing register bank conflicts in processors with large register files.	SASP	2009	DBLP DOI BibTeX RDF
1	Jonghee M. Youn, Minwook Ahn, Daeho Kim, Jonghee W. Yoon, Yunheung Paek, Sechul Shin, Hochang Chae, Jeonghun Cho	A new addressing mode for the encoding space problem on embedded processors.	SASP	2009	DBLP DOI BibTeX RDF
1	Shoaib Akram 0001, Rakesh Kumar 0002, Deming Chen	Workload adaptive shared memory multicore processors with reconfigurable interconnects.	SASP	2009	DBLP DOI BibTeX RDF
1	Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh	A memory optimization technique for software-managed scratchpad memory in GPUs.	SASP	2009	DBLP DOI BibTeX RDF
1	Junguk Cho, Bridget Benson, Ryan Kastner	Hardware acceleration of multi-view face detection.	SASP	2009	DBLP DOI BibTeX RDF
1	Hyunchul Park 0001, Yongjun Park 0001, Scott A. Mahlke	A dataflow-centric approach to design low power control paths in CGRAs.	SASP	2009	DBLP DOI BibTeX RDF
1		Proceedings of the IEEE 7th Symposium on Application Specific Processors, SASP 2009, San Francisco, CA, USA , July 27-28, 2009	SASP	2009	DBLP BibTeX RDF
1	Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq	Driver assistance system design and its optimization for FPGA based MPSoC.	SASP	2009	DBLP DOI BibTeX RDF
1	Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada	A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs.	SASP	2009	DBLP DOI BibTeX RDF
1	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A reconfigurable beamformer for audio applications.	SASP	2009	DBLP DOI BibTeX RDF
1	Yuanrui Zhang, Mahmut T. Kandemir	A hardware-software codesign strategy for Loop intensive applications.	SASP	2009	DBLP DOI BibTeX RDF
1	Ganesh S. Dasika, Kevin Fan, Scott A. Mahlke	Power-efficient medical image processing using PUMA.	SASP	2009	DBLP DOI BibTeX RDF
1	Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu	FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs.	SASP	2009	DBLP DOI BibTeX RDF
1	Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne	Arithmetic optimization for custom instruction set synthesis.	SASP	2009	DBLP DOI BibTeX RDF
1	Bo Zhou 0018, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu	A multi-FPGA accelerator for radiation dose calculation in cancer treatment.	SASP	2009	DBLP DOI BibTeX RDF
1	Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne	Introducing control-flow inclusion to support pipelining in custom instruction set extensions.	SASP	2009	DBLP DOI BibTeX RDF
1	Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.	SASP	2009	DBLP DOI BibTeX RDF
1	Mathew Paul, Peter Petrov	Dynamic and application-driven I-cache partitioning for low-power embedded multitasking.	SASP	2009	DBLP DOI BibTeX RDF
1	Wei Han 0001, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan	Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.	SASP	2009	DBLP DOI BibTeX RDF
1	Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan Kastner	An FPGA Design Space Exploration Tool for Matrix Inversion Architectures.	SASP	2008	DBLP DOI BibTeX RDF
1	Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi	System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis.	SASP	2008	DBLP DOI BibTeX RDF
1	Kenshu Seto, Masahiro Fujita	Custom Instruction Generation with High-Level Synthesis.	SASP	2008	DBLP DOI BibTeX RDF
1	Xingdong Dai, Meghanad D. Wagh	An MDCT Hardware Accelerator for MP3 Audio.	SASP	2008	DBLP DOI BibTeX RDF
1	Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz	Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking.	SASP	2008	DBLP DOI BibTeX RDF
1	Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi	Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays.	SASP	2008	DBLP DOI BibTeX RDF
1	Hai Lin 0004, Guangyu Sun 0003, Yunsi Fei, Yuan Xie 0001, Anand Sivasubramaniam	Thermal-aware Design Considerations for Application-Specific Instruction Set Processor.	SASP	2008	DBLP DOI BibTeX RDF
1	Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman	Extensible On-Chip Peripherals.	SASP	2008	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato	AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications.	SASP	2008	DBLP DOI BibTeX RDF
1	Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu	Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor.	SASP	2008	DBLP DOI BibTeX RDF
1	Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker 0001	Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.	SASP	2008	DBLP DOI BibTeX RDF
1	Kwangyoon Lee, Alex Orailoglu	Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems.	SASP	2008	DBLP DOI BibTeX RDF
1	Wei Han 0001, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet Teyfik Erdogan	Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.	SASP	2008	DBLP DOI BibTeX RDF
1	Jelena Trajkovic, Daniel D. Gajski	Custom Processor Core Construction from C Code.	SASP	2008	DBLP DOI BibTeX RDF
1		Proceedings of the IEEE Symposium on Application Specific Processors, SASP 2008, held in conjunction with the DAC 2008, June 8-9, 2008, Anaheim, California, USA	SASP	2008	DBLP BibTeX RDF
1	Enric Musoll	Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating.	SASP	2008	DBLP DOI BibTeX RDF
1	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.	SASP	2008	DBLP DOI BibTeX RDF
1	Marcela Zuluaga, Nigel P. Topham	Resource Sharing in Custom Instruction Set Extensions.	SASP	2008	DBLP DOI BibTeX RDF
1	Josef B. Spjut, Solomon Boulos, Daniel M. Kopta, Erik Brunvand, Spencer S. Kellis	TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing.	SASP	2008	DBLP DOI BibTeX RDF
1	Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadron, John C. Lach	Accelerating Compute-Intensive Applications with GPUs and FPGAs.	SASP	2008	DBLP DOI BibTeX RDF

Publications at "SASP"( http://dblp.L3S.de/Venues/SASP )