Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Marc Herbstritt, Bernd Becker 0001, Christoph Scholl 0001	Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs.	MTV	2006	DBLP DOI BibTeX RDF
12	Jianmin Zhang, Ming Yan 0003, Sikun Li	Debug Support for Scalable System-on-Chip.	MTV	2006	DBLP DOI BibTeX RDF
12	Vijay Gangaram, Deepa Bhan, James K. Caldwell	Functional Test Selection for High Volume Manufacturing.	MTV	2006	DBLP DOI BibTeX RDF	Functional Test Sequences, Fault Simulation Acceleration, Untestable Fault Identification, Design Validation, Test Sequence Compaction
12	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	Diagnosing Silicon Failures Based on Functional Test Patterns.	MTV	2006	DBLP DOI BibTeX RDF	fault diagnosis, Silicon debug, design for debug
12	Heon-Mo Koo, Prabhat Mishra 0001, Jayanta Bhadra, Magdy S. Abadir	Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.	MTV	2006	DBLP DOI BibTeX RDF
12	Paolo Bernardi, Letícia Maria Veiras Bolzani, Alberto Manzone, Massimo Osella, Massimo Violante, Matteo Sonza Reorda	Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.	MTV	2006	DBLP DOI BibTeX RDF
12	Sean Safarpour, Andreas G. Veneris	Abstraction and Refinement Techniques in Automated Design Debugging.	MTV	2006	DBLP DOI BibTeX RDF
12		Program Committee.	MTV	2006	DBLP DOI BibTeX RDF
12	Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena	A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
12	Norman J. Rohrer, Cédric Lichtenau, Peter A. Sandon, Paul Kartschoke, Erwin B. Cohen, Miles G. Canada, Thomas Pflüger, Mathew I. Ringler, Rolf B. Hilgendorf, Stephen F. Geissler, Jeffrey S. Zimmerman	A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
12	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon	A dual-core 64-bit ultraSPARC microprocessor for dense server applications.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
12	Masakatsu Nakai, Satoshi Akui, Katsunori Seno, Tetsumasa Meguro, Takahiro Seki, Tetsuo Kondo, Akihiko Hashiguchi, Hirokazu Kawahara, Kazuo Kumano, Masayuki Shimura	Dynamic voltage and frequency management for a low-power embedded microprocessor.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
12	Jerzy Kotlinski	Microprocessor controller for EL-1 ID ellipsometer.	Ann. UMCS Informatica	2005	DBLP BibTeX RDF
12	Fulvio Corno, Ernesto Sánchez 0001, Giovanni Squillero	Evolving assembly programs: how games help microprocessor validation.	IEEE Trans. Evol. Comput.	2005	DBLP DOI BibTeX RDF
12	Takahiro Seki, Satoshi Akui, Katsunori Seno, Masakatsu Nakai, Tetsumasa Meguro, Tetsuo Kondo, Akihiko Hashiguchi, Hirokazu Kawahara, Kazuo Kumano, Masayuki Shimura	Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
12	Dave W. Victor, John M. Ludden, Richard D. Peterson, Bradley S. Nelson, W. Keith Sharp, James K. Hsu, Bing-Lun Chu, Michael L. Behm, Rebecca M. Gott, Audre D. Romonosky, Steven R. Farago	Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
12	Gautam Sarkar, Anindita Dasgupta, Anish Deb	Microprocessor-based simulation of sampled data systems with/without a hold device using a set of sample-and-hold functions and Dirac delta functions.	J. Frankl. Inst.	2005	DBLP DOI BibTeX RDF
12	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham	A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.	Formal Methods Syst. Des.	2005	DBLP DOI BibTeX RDF	efficient memory models, embedded memory verification, custom circuit verification, equivalence checking, symbolic trajectory evaluation
12	Hannu Olkkonen, Juuso T. Olkkonen, Peitsa Pesola	Efficient lifting wavelet transform for microprocessor and VLSI applications.	IEEE Signal Process. Lett.	2005	DBLP DOI BibTeX RDF
12	Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo	Microprocessor-based FPGA implementation of SPIHT image compression subsystems.	Microprocess. Microsystems	2005	DBLP DOI BibTeX RDF
12	M. A. Aguirre, Jonathan Noel Tombs, Vicente Baena Lecuyer, Jose Luis Mora, Juan Manuel Carrasco Solís, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo	Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems.	Microprocess. Microsystems	2005	DBLP DOI BibTeX RDF
12	Paul M. Belemjian, Okan Erdogan, Russell P. Kraft, John F. McDonald 0001	SiGe HBT Microprocessor Core Test Vehicle.	Proc. IEEE	2005	DBLP DOI BibTeX RDF
12	Matthias Menge	Mikroprozessor im Hardware-/Software-Codesign (Microprocessor by Hardware-/Software-Codesign).	it Inf. Technol.	2005	DBLP DOI BibTeX RDF
12	Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic.	DSN	2005	DBLP DOI BibTeX RDF
12	Robert P. Colwell	Where Intel's Microprocessor Architecture is Going.	ERSA	2005	DBLP BibTeX RDF
12	Magdy S. Abadir, Li-C. Wang (eds.)	Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA	MTV	2005	DBLP BibTeX RDF
12	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001	Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.	PATMOS	2005	DBLP DOI BibTeX RDF
12	Snaider L. Carrillo, Agenor Z. Polo, Mario P. Esmeral	Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3.	ReConFig	2005	DBLP DOI BibTeX RDF
12	Xiaoping Zhu, Teng-Tiow Tay	A Compiler-Controlled Instruction Cache Architecture for an Embedded Low Power Microprocessor.	CIT	2005	DBLP DOI BibTeX RDF
12	Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi	TED+: a data structure for microprocessor verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Bor-Chin Chang 0001, Chunlong Hu, Mark Ilg	Design and DSP microprocessor implementation of digital sinusoidal tracking controllers.	ACC	2005	DBLP DOI BibTeX RDF
12	Yue Luo, Lizy Kurian John	On sampling unit size in sampled microprocessor simulation.	IPCCC	2005	DBLP DOI BibTeX RDF
12	Leonidas G. Bleris, Mayuresh V. Kothare	Implementation of Model Predictive Control for Glucose Regulation on a General Purpose Microprocessor.	CDC/ECC	2005	DBLP DOI BibTeX RDF
12	Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat	Division by Constant for the ST100 DSP Microprocessor.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
12	Reza Azimi, Michael Stumm, Robert W. Wisniewski	Online performance analysis by statistical sampling of microprocessor performance counters.	ICS	2005	DBLP DOI BibTeX RDF
12	Aurangzeb Khan, Philip Watson, George Kuo, Due Le, Trung-Kien Nguyen, Steven Yang, P. Bennet, Pokai Huang, Jaspal Gill, Demin Wang, Irfan Ahmed, Peter Tran, Helder Mak, Oanh Kim, Frank Martin, Yimu Fan, D. Ge, Joseph Kung, Vincent Shek	A 90nm power optimization methodology and its' application to the ARM 1136SF-S microprocessor.	CICC	2005	DBLP DOI BibTeX RDF
12	Padraig J. O'Dowd, Philip D. Healy, John P. Morrison	A Condensed Graph Microprocessor to Drive Parallel Computing.	PDPTA	2005	DBLP BibTeX RDF
12	Olivier Caty, Peter Dahlgren, Ismet Bayraktaroglu	Microprocessor silicon debug based on failure propagation tracing.	ITC	2005	DBLP DOI BibTeX RDF
12	Peilin Song, Franco Stellari, Bill Huott, Otto Wagner, Uma Srinivasan 0002, Yuen H. Chan, Rick Rizzolo, H. J. Nam, James P. Eckhardt, Timothy G. McNamara, Ching-Lung Tong, Alan J. Weger, Moyra K. McManus	An advanced optical diagnostic technique of IBM z990 eServer microprocessor.	ITC	2005	DBLP DOI BibTeX RDF
12	Yann-Hang Lee, Aung Oo	Teaching microprocessor systems design using a SoC and Embedded Linux platform.	WCAE@ISCA	2005	DBLP DOI BibTeX RDF
12	Pradip Bose	Power-Aware, Reliable Microprocessor Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Kadir Erkan, Seda Postalcioglu, Emine Dogru Bolat	Implementation of Microprocessor Based pH Process Control.	CSC	2005	DBLP BibTeX RDF
12	Dominic Pajak	Specification of microprocessor instruction set architectures : ARM case study.		2005	RDF
12	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.	MTV	2005	DBLP DOI BibTeX RDF
12	Tobias Schubert 0001, Matthew D. T. Lewis, Bernd Becker 0001	PaMira - A Parallel SAT Solver with Knowledge Sharing.	MTV	2005	DBLP DOI BibTeX RDF
12		Acknowledgement.	MTV	2005	DBLP DOI BibTeX RDF
12	Nicola Bombieri, Andrea Fedeli, Franco Fummi	On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.	MTV	2005	DBLP DOI BibTeX RDF
12	John Mark Nolen, Rabi N. Mahapatra	A TDM Test Scheduling Method for Network-on-Chip Systems.	MTV	2005	DBLP DOI BibTeX RDF
12	Daniel Große, Ulrich Kühne, Rolf Drechsler	HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.	MTV	2005	DBLP DOI BibTeX RDF
12	Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt	An Introduction to the Plasma Language.	MTV	2005	DBLP DOI BibTeX RDF
12	Bin Xue, D. M. H. Walker	Is IDDQ Test of Microprocessors Feasible?	MTV	2005	DBLP DOI BibTeX RDF
12		Workshop Organizing Committee.	MTV	2005	DBLP DOI BibTeX RDF
12		Preface.	MTV	2005	DBLP DOI BibTeX RDF
12	David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla	Automated Extraction of Structural Information from SystemC-based IP for Validation.	MTV	2005	DBLP DOI BibTeX RDF
12		Program Committee.	MTV	2005	DBLP DOI BibTeX RDF
12	Wei Qin, Sharad Malik	A Study of Architecture Description Languages from a Model-based Perspective.	MTV	2005	DBLP DOI BibTeX RDF
12	Marc Herbstritt, Bernd Becker 0001	On SAT-based Bounded Invariant Checking of Blackbox Designs.	MTV	2005	DBLP DOI BibTeX RDF
12	Soohong P. Kim	Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors.	MTV	2005	DBLP DOI BibTeX RDF
12	Jennifer Dworak	An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects.	MTV	2005	DBLP DOI BibTeX RDF
12	Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler	Post-Verification Debugging of Hierarchical Designs.	MTV	2005	DBLP DOI BibTeX RDF
12	Prabhat Mishra 0001, Heon-Mo Koo, Zhuo Huang	Language-driven Validation of Pipelined Processors using Satisfiability Solvers.	MTV	2005	DBLP DOI BibTeX RDF
12	Brian Kahne, Magdy S. Abadir	Retiming Verification Using Sequential Equivalence Checking.	MTV	2005	DBLP DOI BibTeX RDF
12	Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner	A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
12	Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, Kaushik Roy 0001, T. N. Vijaykumar	DCG: deterministic clock-gating for low-power microprocessor design.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
12	Timothy J. Slegel, Erwin Pfeffer, Jeffrey A. Magee	The IBM eServer z990 microprocessor.	IBM J. Res. Dev.	2004	DBLP DOI BibTeX RDF
12	Dean G. Bair, Steven M. German, William D. Wollyung, Edward J. Kaminski Jr., James Schafer, Michael P. Mullen, William J. Lewis, Rebecca Wisniewski, Joerg Walter, Steven Mittermaier, Visda Vokhshoori, Robert J. Adkins, Michael Halas, Thomas Ruane, Ursel Hahn	Functional verification of the z990 superscalar, multibook microprocessor complex.	IBM J. Res. Dev.	2004	DBLP DOI BibTeX RDF
12	Kei Okada, Akira Fuyuno, Takeshi Morishita, Takashi Ogura, Yasumoto Ohkubo, Yasuyuki Kino, Masayuki Inaba, Hirochika Inoue	Device Distributed Approach to Expandable Robot System Using Intelligent Device with Super-Microprocessor.	J. Robotics Mechatronics	2004	DBLP DOI BibTeX RDF
12	Arthur Shoihet, Michael A. Slonim	New Topology For Soft Starting And Speed Regulation Of Wound Rotor Asynchronous Machine Controlled By Microprocessor.	J. Circuits Syst. Comput.	2004	DBLP DOI BibTeX RDF
12	Ali Chehab, Samer Hanna, Karim Y. Kabalan, Ali El-Hajj	8085 microprocessor simulation tool "8085 SimuKit".	Comput. Appl. Eng. Educ.	2004	DBLP DOI BibTeX RDF
12	Evelio J. González, Alberto F. Hamilton, Lorenzo Moreno Ruiz, Roberto L. Marichal, Santiago Torres Álvarez	A set of microprocessor-based procedures for an industrial engineering course.	Comput. Appl. Eng. Educ.	2004	DBLP DOI BibTeX RDF
12	Nikita Pashenkov, Ryuichi Iwamasa	One-Chip Solution to Intelligent Robot Control: Implementing Hexapod Subsumption Architecture Using a Contemporary Microprocessor	CoRR	2004	DBLP BibTeX RDF
12	Prabhat Mishra 0001, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir	A Top-Down Methodology for Microprocessor Validation.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
12		Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA	MTV	2004	DBLP BibTeX RDF
12	Carlo Brandolese, William Fornaciari, Fabio Salice	Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.	PATMOS	2004	DBLP DOI BibTeX RDF
12	Takashi Nakada, Hiroshi Nakashima	Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.	MASCOTS	2004	DBLP DOI BibTeX RDF
12	Pedro Trancoso	What to Adapt in a High-Performance Microprocessor.	DSD	2004	DBLP DOI BibTeX RDF
12	Russ Joseph, Zhigang Hu, Margaret Martonosi	Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization.	HPCA	2004	DBLP DOI BibTeX RDF
12	Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Jorge Campos, Hussain Al-Asaad	Mutation-based validation of high-level microprocessor implementations.	HLDVT	2004	DBLP DOI BibTeX RDF
12	Javier Sanchez-Pastor, Iván González 0004, Jorge López, Francisco J. Gomez-Arribas, Javier Martínez	A Remote Laboratory for Debugging FPGA-Based Microprocessor Prototypes.	ICALT	2004	DBLP DOI BibTeX RDF
12	Cynthia Trigas, Stefan Doll, Joachim Kruecken	MRAM and microprocessor system-in-package: technology stepping stone to advanced embedded devices.	CICC	2004	DBLP DOI BibTeX RDF
12	Hector Arteaga, Hussain Al-Asaad	Approaches for Monitoring Vectors on Microprocessor Buses.	ESA/VLSI	2004	DBLP BibTeX RDF
12	Helmut Bähring, Jörg Keller 0001, Wolfram Schiffmann	A combined virtual and remotely accessible microprocessor laboratory.	WCAE	2004	DBLP DOI BibTeX RDF
12	Ushaa Eswaran, Madhusudhana Rao Ganji, M. S. Thakur	Microprocessor Based Biosensors for Determination of Toxins and Pathogens in Restricted Areas of Human Intervention.	IC-AI	2004	DBLP BibTeX RDF
12	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon	A dual-core 64b ultraSPARC microprocessor for dense server applications.	DAC	2004	DBLP DOI BibTeX RDF	L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability
12	Michele Borgatti, Andrea Fedeli, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	A Verification Methodology for Reconfigurable Systems.	MTV	2004	DBLP DOI BibTeX RDF
12	Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.	MTV	2004	DBLP DOI BibTeX RDF
12	Xiuli Sun, Jinzhao Wu, Xiaoyu Song, Mila E. Majster-Cederbaum	Formal Specification of an Asynchronous Processor via Action Refinement.	MTV	2004	DBLP DOI BibTeX RDF	pipelines, microprocessors, asynchronous circuits, Action refinement
12	Tobias Schubert 0001, Bernd Becker 0001	PICHAFF2 - A Hierarchical Parallel SAT Solver.	MTV	2004	DBLP DOI BibTeX RDF
12	Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith 0001	Debugging Sequential Circuits Using Boolean Satisfiability.	MTV	2004	DBLP DOI BibTeX RDF
12	M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu	Identification of Gates for Covering all Critical Paths.	MTV	2004	DBLP DOI BibTeX RDF
12	Arkan Abdulrahman, Spyros Tragoudas	Compact ATPG for Concurrent SOC Testing.	MTV	2004	DBLP DOI BibTeX RDF
12		Program Committee.	MTV	2004	DBLP DOI BibTeX RDF
12	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner	Extreme Formal Modeling (XFM) for Hardware Models.	MTV	2004	DBLP DOI BibTeX RDF
12	Prabhat Mishra 0001, Nikil D. Dutt, Yaron Kashai	Functional Verification of Pipelined Processors: A Case Study.	MTV	2004	DBLP DOI BibTeX RDF
12		Workshop Organizing Committee.	MTV	2004	DBLP DOI BibTeX RDF
12		Acknowledgement.	MTV	2004	DBLP DOI BibTeX RDF
12		Preface.	MTV	2004	DBLP DOI BibTeX RDF
12	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
12	Eyal Bin, Laurent Fournier	Micro-Architecture Verification for Microprocessors.	MTV	2004	DBLP DOI BibTeX RDF