Search results for "leakage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.	PATMOS	2007	DBLP DOI BibTeX RDF
15	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.	DATE	2007	DBLP DOI BibTeX RDF
15	Sastry Konduri, Brajendra Panda, Wing-Ning Li	Monitoring Information Leakage During Query Aggregation.	ICDCIT	2007	DBLP DOI BibTeX RDF
15	Kerstin Lemke-Rust, Christof Paar	Analyzing Side Channel Leakage of Masked Implementations with Stochastic Methods.	ESORICS	2007	DBLP DOI BibTeX RDF	Boolean Masking, Multivariate Side Channel Analysis, Higher-Order Side Channel Analysis, Stochastic Methods, Side Channel Cryptanalysis
15	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.	VLSI Design	2007	DBLP DOI BibTeX RDF
15	De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang	Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.	DAC	2007	DBLP DOI BibTeX RDF
15	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Enabling fine-grain leakage management by voltage anchor insertion.	DATE	2006	DBLP DOI BibTeX RDF
15	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
15	Benjamin Aziz	Measuring the Speed of Information Leakage in Mobile Processes.	AMAST	2006	DBLP DOI BibTeX RDF
15	Somchai Chatvichienchai, Mizuho Iwaihara	Detecting Information Leakage in Updating XML Documents of Fine-Grained Access Control.	DEXA	2006	DBLP DOI BibTeX RDF
15	Ralf Salomon, Frank Sill	Biologically-Inspired Optimization of Circuit Performance and Leakage: A Comparative Study.	ARCS	2006	DBLP DOI BibTeX RDF
15	Ja Chun Ku, Yehea I. Ismail	Area optimization for leakage reduction and thermal stability in nanometer scale technologies.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Ismail Kadayif, Mahmut T. Kandemir, Feihui Li	Prefetching-aware cache line turnoff for saving leakage energy.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Elias Kougianos, Saraju P. Mohanty	Effective tunneling capacitance: a new metric to quantify transient gate leakage current.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Harmander Deogun, Dennis Sylvester, Kevin J. Nowka	Fine grained multi-threshold CMOS for enhanced leakage reduction.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Qing Wu, Subhasis Nandi	A Novel Approach to Calculate Squirrel Cage Induction Motor Rotor Leakage Inductance.	CCECE	2006	DBLP DOI BibTeX RDF
15	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
15	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
15	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	Shadi T. Khasawneh, Kanad Ghose	An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers.	PATMOS	2005	DBLP DOI BibTeX RDF
15	Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar	RG-SRAM: A Low Gate Leakage Memory Design.	ISVLSI	2005	DBLP DOI BibTeX RDF
15	Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles	Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.	DSD	2005	DBLP DOI BibTeX RDF
15	Rachid Echahed, Frédéric Prost	Handling declared information leakage: extended abstract.	WITS	2005	DBLP DOI BibTeX RDF
15	Xin Lu, Yuzhuo Fu	Reducing leakage power in instruction cache using WDC for embedded processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Panagiotis Katsaros	On the Design of Access Control to Prevent Sensitive Information Leakage in Distributed Object Systems: A Colored Petri Net Based Model.	OTM Conferences (2)	2005	DBLP DOI BibTeX RDF
15	Soheil Ghiasi	Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study.	ICCD	2005	DBLP DOI BibTeX RDF
15	Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo	On reducing leakage quantization noise of multistage Sigma-Delta modulator using nonlinear oscillation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi 0001, Takayasu Sakurai	Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).	ISCAS (4)	2005	DBLP DOI BibTeX RDF
15	Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson	A low-leakage twin-precision multiplier using reconfigurable power gating.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
15	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
15	Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa	DPA Leakage Models for CMOS Logic Circuits.	CHES	2005	DBLP DOI BibTeX RDF
15	Simon D. Byers	Information Leakage Caused by Hidden Data in Published Documents.	IEEE Secur. Priv.	2004	DBLP DOI BibTeX RDF	hidden data, data security, web publishing
15	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF
15	Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine	Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.	PATMOS	2004	DBLP DOI BibTeX RDF
15	Mahadevan Gomathisankaran, Akhilesh Tyagi	WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays.	ISVLSI	2004	DBLP DOI BibTeX RDF
15	Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi	Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.	DATE	2004	DBLP DOI BibTeX RDF
15	Pietro Babighian, Luca Benini, Enrico Macii	Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating.	DATE	2004	DBLP DOI BibTeX RDF
15	Xiangrong Wang, Jun Xu, Christopher H. Pham	An Effective Method to Detect Software Memory Leakage Leveraged from Neuroscience Principles Governing Human Memory Behavior.	ISSRE	2004	DBLP DOI BibTeX RDF
15	Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi	Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.	ICCAD	2004	DBLP DOI BibTeX RDF
15	Donald Chai, Andreas Kuehlmann	Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation.	ICCD	2004	DBLP DOI BibTeX RDF
15	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001	Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.	ISQED	2004	DBLP DOI BibTeX RDF
15	Stas Polonsky, Keith A. Jenkins, Alan J. Weger, Shinho Cho	CMOS IC diagnostics using the luminescence of OFF-state leakage currents.	ITC	2004	DBLP DOI BibTeX RDF
15	Farzan Farbiz, M. Farazian, M. Emadi, K. Sadeghi	Sizing Consideration for Leakage Control Transistor.	VLSI Design	2004	DBLP DOI BibTeX RDF
15	Nam Sung Kim, Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan	Leakage Current: Moore's Law Meets Static Power.	Computer	2003	DBLP DOI BibTeX RDF
15	Hiroomi Hikawa	Pulse mode neuron with leakage integrator and additive random noise.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Koushik K. Das, Richard B. Brown	Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology.	VLSI Design	2003	DBLP DOI BibTeX RDF
12	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
12	Jungwook Kim, Seong Tae Jhang, Chu Shik Jhon	Dynamic register-renaming scheme for reducing power-density and temperature.	SAC	2010	DBLP DOI BibTeX RDF	embedded operating systems for mobile computing, power-density minimization, renaming scheme, register file, thermal management
12	Yongchan Ban, Savithri Sundareswaran, David Z. Pan	Total sensitivity based dfm optimization of standard library cells.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, VLSI, sensitivity, DFM, lithography
12	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
12	Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella	An integrated thermal estimation framework for industrial embedded platforms.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	system-on-chip, power, estimation, thermal
12	Peng Zhou, JiangHe Yao, JiuLing Pei	Implementation of an energy-efficient scheduling scheme based on pipeline flux leak monitoring networks.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	dynamic modulation scaling, reclaiming scheme, sensor networks, real-time scheduling, EDF
12	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
12	Xiangrong Zhou, Chenjie Yu, Peter Petrov	Temperature-aware register reallocation for register file power-density minimization.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
12	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
12	Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila	Self-timed thermal sensing and monitoring of multicore systems.	DDECS	2009	DBLP DOI BibTeX RDF
12	Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu	Can SG-FET Replace FET in Sleep Mode Circuits?	NanoNet	2009	DBLP DOI BibTeX RDF	SG-FET, power gating, sleep transistor
12	Kotaro Fukui, Yuma Ishikawa, Keisuke Ohno, Nana Sakakibara, Masaaki Honda, Atsuo Takanishi	Three dimensional tongue with liquid sealing mechanism for improving resonance on an anthropomorphic talking robot.	IROS	2009	DBLP DOI BibTeX RDF
12	Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar	Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Mesut Meterelliyoz, Kaushik Roy 0001	Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Chunyan Mu, David Clark 0001	Quantitative Analysis of Secure Information Flow via Probabilistic Semantics.	ARES	2009	DBLP DOI BibTeX RDF
12	François-Xavier Standaert, François Koeune, Werner Schindler	How to Compare Profiled Side-Channel Attacks?.	ACNS	2009	DBLP DOI BibTeX RDF
12	Shafi Goldwasser	Cryptography without (Hardly Any) Secrets ?	EUROCRYPT	2009	DBLP DOI BibTeX RDF
12	Domenik Helms, Kai Hylla, Wolfgang Nebel	Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction.	ISLPED	2009	DBLP DOI BibTeX RDF	electro-thermal coupling, system level estimation, reliability, thermal modelling, IR-drop
12	Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin	Frequency and yield optimization using power gates in power-constrained designs.	ISLPED	2009	DBLP DOI BibTeX RDF	optimization, yield, power gate, frequency
12	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
12	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
12	Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan	Statistical decoupling capacitance allocation by efficient numerical quadrature method.	ISQED	2009	DBLP DOI BibTeX RDF
12	Berkant Ustaoglu	Comparing SessionStateReveal and EphemeralKeyReveal for Diffie-Hellman Protocols.	ProvSec	2009	DBLP DOI BibTeX RDF	leaking ephemeral secrets, postponed ephemeral key derivation, pseudo-static keys, Key agreement protocols
12	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Bardia Bozorgzadeh, Ali Afzali-Kusha	Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Jian Wang 0037, Rui Chen 0007, Pengyan Zhang, Ningjie Yu	Fault tree analysis in city lifeline system operations and management-theory and application.	ICIS	2009	DBLP DOI BibTeX RDF	city lifeline system, city operations and management, triangular fuzzy number, fault tree analysis
12	Lejla Batina, Benedikt Gierlichs, Kerstin Lemke-Rust	Differential Cluster Analysis.	CHES	2009	DBLP DOI BibTeX RDF	Differential Cluster Analysis, AES Hardware, Differential Power Analysis, Collision Attacks, Side-channel Cryptanalysis
12	Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh	A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.	CHES	2009	DBLP DOI BibTeX RDF
12	Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang	New spare cell design for IR drop minimization in Engineering Change Order.	DAC	2009	DBLP DOI BibTeX RDF	spare cell, IR drop, decoupling capacitor, ECO
12	Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph	Process variation characterization of chip-level multiprocessors.	DAC	2009	DBLP DOI BibTeX RDF	software, process variation, characterization
12	Jungseob Lee, Nam Sung Kim	Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.	DAC	2009	DBLP DOI BibTeX RDF	multicore processor, DVFS, power gating
12	Stephen Farrell	Portable Storage and Data Loss.	IEEE Internet Comput.	2008	DBLP DOI BibTeX RDF
12	Philippe Golle, Frank McSherry, Ilya Mironov	Data Collection with Self-Enforcing Privacy.	ACM Trans. Inf. Syst. Secur.	2008	DBLP DOI BibTeX RDF	privacy, data collection
12	Jin Sun 0006, Jun Li 0066, Dongsheng Ma, Janet Meiling Wang	Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	Frida Eng, Fredrik Gunnarsson, Fredrik Gustafsson	Frequency Domain Analysis of Signals With Stochastic Sampling Times.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
12	Karsten Nohl, David Evans 0001	Hiding in Groups: On the Expressiveness of Privacy Distributions.	SEC	2008	DBLP DOI BibTeX RDF
12	Basuki E. Priyanto, Troels B. Sørensen, Ole K. Jensen	In-Band Interference Effects on UTRA LTE Uplink Resource Block Allocation.	VTC Spring	2008	DBLP DOI BibTeX RDF
12	Jie Zhang 0007, Nishant Patil, Subhasish Mitra	Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.	DATE	2008	DBLP DOI BibTeX RDF
12	Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim 0007	Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution.	DATE	2008	DBLP DOI BibTeX RDF
12	Andrea Marongiu, Luca Benini, Andrea Acquaviva, Andrea Bartolini	Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology.	DSD	2008	DBLP DOI BibTeX RDF
12	Zhenghong Wang, Ruby B. Lee	A novel cache architecture with enhanced performance and security.	MICRO	2008	DBLP DOI BibTeX RDF
12	Zhibin Zhou 0001, Dijiang Huang	SRK: A Distributed RFID Data Access Control Mechanism.	ICC	2008	DBLP DOI BibTeX RDF
12	Tao Luo 0002, David Newmark, David Z. Pan	Total power optimization combining placement, sizing and multi-Vt through slack distribution management.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Jin Sun 0006, Yue Huang, Jun Li 0066, Janet Meiling Wang	Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Dafina Tanase, Niels Komen, Arie Draaijer, Gert-Jan Kleinrensink, Johannes Jeekel, Johan F. Lange, Paddy J. French	Tissue-Viability Monitoring Using an Oxygen-Tension Sensor.	BIOSTEC (Selected Papers)	2008	DBLP DOI BibTeX RDF	Oxygen-tension, tissue viability, sensor
12	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Stress aware layout optimization.	ISPD	2008	DBLP DOI BibTeX RDF
12	Kazumasa Omote, Kazuhiko Kato	Protection and Recovery of Disk Encryption Key Using Smart Cards.	ITNG	2008	DBLP DOI BibTeX RDF
12	Nicholas Allec, Zyad Hassan, Li Shang, Robert P. Dick, Ronggui Yang	ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
12	Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw	STEEL: a technique for stress-enhanced standard cell library design.	ICCAD	2008	DBLP DOI BibTeX RDF
12	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
12	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF