Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
51	Yingchao Zhao 0001, Chun Jason Xue, Minming Li, Bessie C. Hu	Energy-aware register file re-partitioning for clustered VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
51	Chung-Wen Huang, Kun-Yuan Hsieh, Jia-Jhe Li, Jenq Kuen Lee	Support of Paged Register Files for Improving Context Switching on Embedded Processors.	CSE (2)	2009	DBLP DOI BibTeX RDF
51	Jonathan K. Lee, Jens Palsberg, Fernando Magno Quintão Pereira	Aliased Register Allocation for Straight-Line Programs Is NP-Complete.	ICALP	2007	DBLP DOI BibTeX RDF
51	Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin	Compiler Directed Early Register Release.	IEEE PACT	2005	DBLP DOI BibTeX RDF
51	David Fang, Rajit Manohar	Non-Uniform Access Asynchronous Register Files.	ASYNC	2004	DBLP DOI BibTeX RDF
51	Yin Ma, Steve Carr 0001, Rong Ge	Low-Cost Register-Pressure Prediction for Scalar Replacement Using Pseudo-Schedules.	ICPP	2004	DBLP DOI BibTeX RDF
51	Rubén González 0001, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero	A Content Aware Integer Register File Organization.	ISCA	2004	DBLP DOI BibTeX RDF
51	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
51	Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson	Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining.	IEEE PACT	2000	DBLP DOI BibTeX RDF
51	David A. Berson, Rajiv Gupta 0001, Mary Lou Soffa	Integrated Instruction Scheduling and Register Allocation Techniques.	LCPC	1998	DBLP DOI BibTeX RDF
50	Xiaotong Zhuang, Santosh Pande	Allocating architected registers through differential encoding.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	architected register, differential encoding, Register allocation
49	Yi Qian, Steve Carr 0001, Philip H. Sweany	Loop fusion for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	clustered VLIW architectures, loop fusion
49	Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens	Communication Scheduling.	ASPLOS	2000	DBLP DOI BibTeX RDF
47	Jun Yan 0008, Wei Zhang 0002	Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.	HiPEAC	2007	DBLP DOI BibTeX RDF
47	Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello	Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How.	LCPC	2006	DBLP DOI BibTeX RDF
47	Evelyn Duesterwald, Rajiv Gupta 0001, Mary Lou Soffa	Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables.	CC	1992	DBLP DOI BibTeX RDF
47	Hai Lin 0004, Yunsi Fei	Utilizing custom registers in application-specific instruction set processors for register spills elimination.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	custom register, ASIP, register file
47	Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover	Code Compilation for an Explicitly Parallel Register-Sharing Architecture.	ICPP	2007	DBLP DOI BibTeX RDF	register sharing, explicitly parallel code, optimizations, multithreading, register allocation, Fine grain parallelization
47	Andrew Klapper, Jinzhong Xu	Register Synthesis for Algebraic Feedback Shift Registers Based on Non-Primes.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	register synthesis, N-adic numbers, stream cipher, pseudorandom generator, feedback shift register
47	Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao	A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Scheduling, register renaming, out-of-order issue, Register Pressure
47	Keith I. Farkas, Norman P. Jouppi, Paul Chow	Register File Design Considerations in Dynamically Scheduled Processors.	HPCA	1996	DBLP DOI BibTeX RDF	dynamic scheduling, register files, register renaming
47	Kanad Ghose, Kiran Raghavendra Desai, Peter M. Kogge	Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications.	EUROMICRO	1996	DBLP DOI BibTeX RDF	method lookup caches, dynamically-bound object-oriented applications, logical reference, method binding, context allocation, contemporary pipelined datapath, detailed register level simulation, object-oriented programming, object oriented programming languages, register windowing
46	Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin	Exploring the limits of early register release: Exploiting compiler analysis.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	compiler, energy efficiency, Low-power design, microarchitecture, register file
46	Taemin Kim, Xun Liu	Better than optimum?: register reduction using idle pipelined functional units.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	high level synthesis, register binding
46	Heiko Falk	WCET-aware register allocation based on graph coloring.	DAC	2009	DBLP DOI BibTeX RDF	register allocation, WCET
46	Hongbo Rong, Alban Douillet, Guang R. Gao	Register allocation for software pipelined multidimensional loops.	ACM Trans. Program. Lang. Syst.	2008	DBLP DOI BibTeX RDF	register allocation, Software pipelining
46	Ting-Wei Hou, Fuh-Gwo Chen	An anomaly in an interpreter using GCC source-code-level register allocation.	ACM SIGPLAN Notices	2007	DBLP DOI BibTeX RDF	GCC source-code-level register allocation, performance, interpreter
46	Joseph J. Sharkey, Dmitry V. Ponomarev	An L2-miss-driven early register deallocation for SMT processors.	ICS	2007	DBLP DOI BibTeX RDF	register files, simultaneous multithreading
46	Michel Raynal, Gadi Taubenfeld	The notion of a timed register and its application to indulgent synchronization.	SPAA	2007	DBLP DOI BibTeX RDF	test&set, timing assumption, universal object, wait-free implementation, consensus, mutual exclusion, timing constraint, contention manager, process crash, simplicity, atomic register, renaming, concurrent object, asynchronous shared memory system
46	David Ryan Koes, Seth Copen Goldstein	A global progressive register allocator.	PLDI	2006	DBLP DOI BibTeX RDF	progressive solver, register alocation
46	Hongbo Rong, Alban Douillet, Guang R. Gao	Register allocation for software pipelined multi-dimensional loops.	PLDI	2005	DBLP DOI BibTeX RDF	register allocation, software pipelining
46	Patrick Carribault, Albert Cohen 0001	Applications of storage mapping optimization to register promotion.	ICS	2004	DBLP DOI BibTeX RDF	array contraction, array folding, scheduling, pattern matching, string matching, tiling, blocking, itanium, register promotion
46	Hazem I. Shehata, Mark D. Aagaard	A general decomposition strategy for verifying register renaming.	DAC	2004	DBLP DOI BibTeX RDF	formal design verification, register renaming, pipelined circuits
46	Omri Traub, Glenn H. Holloway, Michael D. Smith 0001	Quality and Speed in Linear-scan Register Allocation.	PLDI	1998	DBLP DOI BibTeX RDF	binpacking, global register allocation, linear scan, graph coloring
46	Sandeep Sirsi, Aneesh Aggarwal	Exploring the Limits of Port Reduction in Centralized Register Files.	VLSI Design	2009	DBLP DOI BibTeX RDF
46	Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang	An Area-Efficient Approach to Improving Register File Reliability against Transient Errors.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
46	Rajkishore Barik, Vivek Sarkar	Enhanced Bitwidth-Aware Register Allocation.	CC	2006	DBLP DOI BibTeX RDF
46	Chung-Ju Wu, Sheng-Yuan Chen, Jenq Kuen Lee	Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files.	LCPC	2006	DBLP DOI BibTeX RDF
46	Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk 0001	Increasing Register File Immunity to Transient Errors.	DATE	2005	DBLP DOI BibTeX RDF
46	Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch	Design of superscalar processor with multi-bank register file.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
46	Hua Yang, Gang Cui, Xiao-Zong Yang	2L-MuRR: A Compact Register Renaming Scheme for SMT Processors.	ISPA	2005	DBLP DOI BibTeX RDF
46	Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev 0001, Kanad Ghose	Energy Efficient Register Renaming.	PATMOS	2003	DBLP DOI BibTeX RDF
46	Alex Settle, Daniel A. Connors, Gerolf Hoflehner, Daniel M. Lavery	Optimization for the Intel® Itanium ®Architectur Register Stack.	CGO	2003	DBLP DOI BibTeX RDF
46	Dae-Hwan Kim, Hyuk-Jae Lee	Register Allocation Based on a Reference Flow Analysis.	APLAS	2003	DBLP DOI BibTeX RDF
46	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Hierarchical Clustered Register File Organization for VLIW Processors.	IPDPS	2003	DBLP DOI BibTeX RDF
46	Peter Petrov, Alex Orailoglu	Compiler-Based Register Name Adjustment for Low-Power Embedded Processors.	ICCAD	2003	DBLP DOI BibTeX RDF
46	Erik Johansson, Konstantinos Sagonas	Linear Scan Register Allocation in a High-Performance Erlang Compiler.	PADL	2002	DBLP DOI BibTeX RDF
46	Teresa Monreal, Víctor Viñals, Antonio González 0001, Mateo Valero	Hardware Schemes for Early Register Release.	ICPP	2002	DBLP DOI BibTeX RDF
46	Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons	Register-sensitive selection, duplication, and sequencing of instructions.	ICS	2001	DBLP DOI BibTeX RDF
46	Teresa Monreal, Antonio González 0001, Mateo Valero, José González 0002, Víctor Viñals	Delaying Physical Register Allocation through Virtual-Physical Registers.	MICRO	1999	DBLP DOI BibTeX RDF
46	Dean M. Tullsen, John S. Seng	Storageless Value Prediction Using Prior Register Values.	ISCA	1999	DBLP DOI BibTeX RDF
46	Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi	The anatomy of the register file in a multiscalar processor.	MICRO	1994	DBLP DOI BibTeX RDF
46	Peter Steenkiste, John L. Hennessy	A Simple Interprocedural Register Allocation Algorithm and Its Effectiveness for Lisp.	ACM Trans. Program. Lang. Syst.	1989	DBLP DOI BibTeX RDF	LISP
46	David W. Wall	Global register allocation at link time.	SIGPLAN Symposium on Compiler Construction	1986	DBLP DOI BibTeX RDF
46	David W. Wall	Global register allocation at link time (with retrospective)	Best of PLDI	1986	DBLP DOI BibTeX RDF
46	Yaqiong Qiu, Yonghua Hu, Yang Li, Zhen Tang, Lin Shi	基于两类寄存器互为缓存方法的DSP寄存器分配溢出处理优化算法 (Optimization Algorithm of Complementary Register Usage Between Two Register Classesin Register Spilling for DSP Register Allocation).	计算机科学	2019	DBLP DOI BibTeX RDF
45	Sebastian Hack, Gerhard Goos	Copy coalescing by graph recoloring.	PLDI	2008	DBLP DOI BibTeX RDF	graph coloring, register allocation, ssa form
45	Yunhe Shi, David Gregg, Andrew Beatty, M. Anton Ertl	Virtual machine showdown: stack versus registers.	VEE	2005	DBLP DOI BibTeX RDF	register architecture, stack architecture, virtual machine, interpreter
44	Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon	Securing More Registers with Reduced Instruction Encoding Architectures.	RTCSA	2007	DBLP DOI BibTeX RDF
44	Teresa Monreal, Víctor Viñals, José González 0002, Antonio González 0001, Mateo Valero	Late Allocation and Early Release of Physical Registers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
44	Herbert H. J. Hum, Guang R. Gao	A Novel High-Speed Memory Organization for Fine-Grain Multi-Thread Computing.	PARLE (1)	1991	DBLP DOI BibTeX RDF
43	Xiangrong Zhou, Chenjie Yu, Peter Petrov	Temperature-aware register reallocation for register file power-density minimization.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
43	Xiangrong Zhou, Chenjie Yu, Peter Petrov	Compiler-driven register re-assignment for register file power-density and temperature reduction.	DAC	2008	DBLP DOI BibTeX RDF	power-density minimization, thermal management
43	Pablo Montesinos, Wei Liu 0014, Josep Torrellas	Using Register Lifetime Predictions to Protect Register Files against Soft Errors.	DSN	2007	DBLP DOI BibTeX RDF
43	Wann-Yun Shieh, Chien-Chen Chen	Exploiting Register-Usage for Saving Register-File Energy in Embedded Processors.	EUC	2005	DBLP DOI BibTeX RDF
43	Deepankar Bairagi, Santosh Pande, Dharma P. Agrawal	A Framework for Efficient Register Allocation through Selective Register Demotion.	LCR	2000	DBLP DOI BibTeX RDF
43	David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy	A Method for Register Allocation to Loops in Multiple Register File Architectures.	IPPS	1996	DBLP DOI BibTeX RDF
42	Rei Odaira, Takuya Nakaike, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani	Coloring-based coalescing for graph coloring register allocation.	CGO	2010	DBLP DOI BibTeX RDF	register allocation, register coalescing
42	Lal George, Andrew W. Appel	Iterated Register Coalescing.	ACM Trans. Program. Lang. Syst.	1996	DBLP DOI BibTeX RDF	copy propagation, graph coloring, register allocation, register coalescing
42	William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang	Tolerating data access latency with register preloading.	ICS	1992	DBLP DOI BibTeX RDF	VLIW/superscalar processor, load latency, register preload, register file, data dependence analysis
42	Lefteris M. Kirousis, Evangelos Kranakis, Paul M. B. Vitányi	Atomic Multireader Register.	WDAG	1987	DBLP DOI BibTeX RDF	regular, atomic, Register, reader, writer, shared register
42	Hongbo Rong	Tree register allocation.	MICRO	2009	DBLP DOI BibTeX RDF	register allocation, chordal graph
42	Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee	Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW
42	Christopher Zimmer 0001, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley	Facilitating compiler optimizations through the dynamic mapping of alternate register structures.	CASES	2007	DBLP DOI BibTeX RDF	register queues, compiler optimizations, software pipelining
42	Philip Brisk, Ajay Kumar Verma, Paolo Ienne	An optimistic and conservative register assignment heuristic for chordal graphs.	CASES	2007	DBLP DOI BibTeX RDF	static single assignment (ssa) form, chordal graph, register assignment
42	Koji Ohashi, Mineo Kaneko	Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	high-level synthesis, asynchronous circuit, datapath, register binding
42	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose	SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency.	PACT	2006	DBLP DOI BibTeX RDF	energy-efficiency, register files
42	Laura Pozzi, Paolo Ienne	Exploiting pipelining to relax register-file port constraints of instruction-set extensions.	CASES	2005	DBLP DOI BibTeX RDF	automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output
42	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
42	Xiaotong Zhuang, Tao Zhang 0037, Santosh Pande	Hardware-managed register allocation for embedded processors.	LCTES	2004	DBLP DOI BibTeX RDF	architected registers, physical registers, embedded systems, power consumption, register allocation
42	Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana	A retargetable register allocation framework for embedded processors.	LCTES	2004	DBLP DOI BibTeX RDF	register allocation, embedded processors
42	José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo	Power-Aware Compilation for Register File Energy Reduction.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	register file management, compiler support, energy aware
42	Nam Sung Kim, Trevor N. Mudge	The microarchitecture of a low power register file.	ISLPED	2003	DBLP DOI BibTeX RDF	write queue, low power, instruction level parallelism, register file, out-of-order processor
42	Volker Barthelmann	Inter-task register-allocation for static operating systems.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	context-switch optimization, optimizing for space, register allocation
42	Kameswari V. Garigipati, Cindy Norris	Evaluating the use of profiling by a region-based register allocator.	SAC	2002	DBLP DOI BibTeX RDF	region-based register allocation, profiling
42	Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar	Exploring the Number of Register Windows in ASIP Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows
42	Byung-Sun Yang, Soo-Mook Moon, Seongbae Park, Junpyo Lee, SeungIl Lee, Jinpyo Park, Yoo C. Chung, Suhyun Kim, Kemal Ebcioglu, Erik R. Altman	LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Java JIT compilation, register allocation
42	Madhavi Gopal Valluri, R. Govindarajan	Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
42	John Wood, Harold C. Grossman	Interprocedural register allocation for RISC machines.	ACM Southeast Regional Conference	1992	DBLP DOI BibTeX RDF	Interprocedural Register Allocation, RISC Computer, Webs, Graph Coloring
41	Fernando Magno Quintão Pereira, Jens Palsberg	SSA Elimination after Register Allocation.	CC	2009	DBLP DOI BibTeX RDF
41	Ge Zhang, Xu Yang, Yiwei Zhang	Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File.	NAS	2009	DBLP DOI BibTeX RDF
41	Ming Yang, Lixin Yu, Heping Peng	Energy Efficient Register File with Reduced Window Partition.	ICPADS	2008	DBLP DOI BibTeX RDF
41	Balaji V. Iyer, Thomas M. Conte	A Power Model for Register-Sharing Structures.	DIPES	2008	DBLP DOI BibTeX RDF
41	Miquel Pericàs, Rubén González 0001, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero	An Optimized Front-End Physical Register File with Banking and Writeback Filtering.	PACS	2004	DBLP DOI BibTeX RDF
41	Zhenyu Liu, Jiayue Qi	A Novel Rename Register Architecture and Performance Analysis.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
41	Johan Runeson, Sven-Olof Nyström	Retargetable Graph-Coloring Register Allocation for Irregular Architectures.	SCOPES	2003	DBLP DOI BibTeX RDF
41	Santithorn Bunchua, D. Scott Wills, Linda M. Wills	Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
41	Jessica H. Tseng, Krste Asanovic	Banked Multiported Register Files for High-Frequency Superscalar Microprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
41	Vlad Petric, Anne Bracy, Amir Roth	Three extensions to register integration.	MICRO	2002	DBLP DOI BibTeX RDF
41	Krishnan Kailas, Manoj Franklin, Kemal Ebcioglu	A Register File Architecture and Compilation Scheme for Clustered ILP Processors.	Euro-Par	2002	DBLP DOI BibTeX RDF