|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 4401 occurrences of 2030 keywords
|
|
|
Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
51 | Yingchao Zhao 0001, Chun Jason Xue, Minming Li, Bessie C. Hu |
Energy-aware register file re-partitioning for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 805-810, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Chung-Wen Huang, Kun-Yuan Hsieh, Jia-Jhe Li, Jenq Kuen Lee |
Support of Paged Register Files for Improving Context Switching on Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 352-357, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Jonathan K. Lee, Jens Palsberg, Fernando Magno Quintão Pereira |
Aliased Register Allocation for Straight-Line Programs Is NP-Complete. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 34th International Colloquium, ICALP 2007, Wroclaw, Poland, July 9-13, 2007, Proceedings, pp. 680-691, 2007, Springer, 978-3-540-73419-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin |
Compiler Directed Early Register Release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA, pp. 110-122, 2005, IEEE Computer Society, 0-7695-2429-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | David Fang, Rajit Manohar |
Non-Uniform Access Asynchronous Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 75-85, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Yin Ma, Steve Carr 0001, Rong Ge |
Low-Cost Register-Pressure Prediction for Scalar Replacement Using Pseudo-Schedules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 116-124, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Rubén González 0001, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero |
A Content Aware Integer Register File Organization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 314-324, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi |
Reducing the complexity of the register file in dynamic superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 237-248, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
51 | Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson |
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 3-12, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
51 | David A. Berson, Rajiv Gupta 0001, Mary Lou Soffa |
Integrated Instruction Scheduling and Register Allocation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 11th International Workshop, LCPC'98, Chapel Hill, NC, USA, August 7-9, 1998, Proceedings, pp. 247-262, 1998, Springer, 3-540-66426-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
50 | Xiaotong Zhuang, Santosh Pande |
Allocating architected registers through differential encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 29(2), pp. 9, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
architected register, differential encoding, Register allocation |
49 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Loop fusion for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 112-119, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clustered VLIW architectures, loop fusion |
49 | Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens |
Communication Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, November 12-15, 2000., pp. 82-92, 2000, ACM Press, 1-58113-317-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
47 | Jun Yan 0008, Wei Zhang 0002 |
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 57-70, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello |
Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006. Revised Papers, pp. 283-298, 2006, Springer, 978-3-540-72520-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Evelyn Duesterwald, Rajiv Gupta 0001, Mary Lou Soffa |
Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 4th International Conference on Compiler Construction, CC'92, Paderborn, Germany, October 5-7, 1992, Proceedings, pp. 192-206, 1992, Springer, 3-540-55984-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
47 | Hai Lin 0004, Yunsi Fei |
Utilizing custom registers in application-specific instruction set processors for register spills elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 323-328, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
custom register, ASIP, register file |
47 | Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover |
Code Compilation for an Explicitly Parallel Register-Sharing Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2007 International Conference on Parallel Processing (ICPP 2007), September 10-14, 2007, Xi-An, China, pp. 58, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register sharing, explicitly parallel code, optimizations, multithreading, register allocation, Fine grain parallelization |
47 | Andrew Klapper, Jinzhong Xu |
Register Synthesis for Algebraic Feedback Shift Registers Based on Non-Primes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 31(3), pp. 227-250, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
register synthesis, N-adic numbers, stream cipher, pseudorandom generator, feedback shift register |
47 | Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao |
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 78-89, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Scheduling, register renaming, out-of-order issue, Register Pressure |
47 | Keith I. Farkas, Norman P. Jouppi, Paul Chow |
Register File Design Considerations in Dynamically Scheduled Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 40-51, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dynamic scheduling, register files, register renaming |
47 | Kanad Ghose, Kiran Raghavendra Desai, Peter M. Kogge |
Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 441-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
method lookup caches, dynamically-bound object-oriented applications, logical reference, method binding, context allocation, contemporary pipelined datapath, detailed register level simulation, object-oriented programming, object oriented programming languages, register windowing |
46 | Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin |
Exploring the limits of early register release: Exploiting compiler analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 12:1-12:30, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, energy efficiency, Low-power design, microarchitecture, register file |
46 | Taemin Kim, Xun Liu |
Better than optimum?: register reduction using idle pipelined functional units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 327-332, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
high level synthesis, register binding |
46 | Heiko Falk |
WCET-aware register allocation based on graph coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 726-731, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
register allocation, WCET |
46 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 30(4), pp. 23:1-23:68, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register allocation, Software pipelining |
46 | Ting-Wei Hou, Fuh-Gwo Chen |
An anomaly in an interpreter using GCC source-code-level register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 42(4), pp. 9-13, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
GCC source-code-level register allocation, performance, interpreter |
46 | Joseph J. Sharkey, Dmitry V. Ponomarev |
An L2-miss-driven early register deallocation for SMT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 21th Annual International Conference on Supercomputing, ICS 2007, Seattle, Washington, USA, June 17-21, 2007, pp. 138-147, 2007, ACM, 978-1-59593-768-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register files, simultaneous multithreading |
46 | Michel Raynal, Gadi Taubenfeld |
The notion of a timed register and its application to indulgent synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007, pp. 200-209, 2007, ACM, 978-1-59593-667-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
test&set, timing assumption, universal object, wait-free implementation, consensus, mutual exclusion, timing constraint, contention manager, process crash, simplicity, atomic register, renaming, concurrent object, asynchronous shared memory system |
46 | David Ryan Koes, Seth Copen Goldstein |
A global progressive register allocator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada, June 11-14, 2006, pp. 204-215, 2006, ACM, 1-59593-320-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
progressive solver, register alocation |
46 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multi-dimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, Chicago, IL, USA, June 12-15, 2005, pp. 154-167, 2005, ACM, 1-59593-056-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining |
46 | Patrick Carribault, Albert Cohen 0001 |
Applications of storage mapping optimization to register promotion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004, pp. 247-256, 2004, ACM, 1-58113-839-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
array contraction, array folding, scheduling, pattern matching, string matching, tiling, blocking, itanium, register promotion |
46 | Hazem I. Shehata, Mark D. Aagaard |
A general decomposition strategy for verifying register renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 234-237, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
formal design verification, register renaming, pipelined circuits |
46 | Omri Traub, Glenn H. Holloway, Michael D. Smith 0001 |
Quality and Speed in Linear-scan Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), Montreal, Canada, June 17-19, 1998, pp. 142-151, 1998, ACM, 0-89791-987-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
binpacking, global register allocation, linear scan, graph coloring |
46 | Sandeep Sirsi, Aneesh Aggarwal |
Exploring the Limits of Port Reduction in Centralized Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 535-540, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang |
An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (1) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 1, May 21-23, 2007, Niagara Falls, Canada, pp. 798-803, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Rajkishore Barik, Vivek Sarkar |
Enhanced Bitwidth-Aware Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 15th International Conference, CC 2006, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2006, Vienna, Austria, March 30-31, 2006, Proceedings, pp. 263-276, 2006, Springer, 3-540-33050-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Chung-Ju Wu, Sheng-Yuan Chen, Jenq Kuen Lee |
Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006. Revised Papers, pp. 251-266, 2006, Springer, 978-3-540-72520-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk 0001 |
Increasing Register File Immunity to Transient Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 586-591, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch |
Design of superscalar processor with multi-bank register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3507-3510, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Hua Yang, Gang Cui, Xiao-Zong Yang |
2L-MuRR: A Compact Register Renaming Scheme for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Third International Symposium, ISPA 2005, Nanjing, China, November 2-5, 2005, Proceedings, pp. 407-418, 2005, Springer, 3-540-29769-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev 0001, Kanad Ghose |
Energy Efficient Register Renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 219-228, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Alex Settle, Daniel A. Connors, Gerolf Hoflehner, Daniel M. Lavery |
Optimization for the Intel® Itanium ®Architectur Register Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 115-124, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Dae-Hwan Kim, Hyuk-Jae Lee |
Register Allocation Based on a Reference Flow Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APLAS ![In: Programming Languages and Systems, First Asian Symposium, APLAS 2003, Beijing, China, November 27-29, 2003, Proceedings, pp. 394-409, 2003, Springer, 3-540-20536-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Hierarchical Clustered Register File Organization for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 77, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Peter Petrov, Alex Orailoglu |
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 523-528, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Erik Johansson, Konstantinos Sagonas |
Linear Scan Register Allocation in a High-Performance Erlang Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADL ![In: Practical Aspects of Declarative Languages, 4th International Symposium, PADL 2002, Portland, OR, USA, January 19-20, 2002, Proceedings, pp. 101-119, 2002, Springer, 3-540-43092-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Teresa Monreal, Víctor Viñals, Antonio González 0001, Mateo Valero |
Hardware Schemes for Early Register Release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 5-13, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons |
Register-sensitive selection, duplication, and sequencing of instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001, pp. 277-288, 2001, ACM, 1-58113-410-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
46 | Teresa Monreal, Antonio González 0001, Mateo Valero, José González 0002, Víctor Viñals |
Delaying Physical Register Allocation through Virtual-Physical Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 186-192, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Dean M. Tullsen, John S. Seng |
Storageless Value Prediction Using Prior Register Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 270-279, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi |
The anatomy of the register file in a multiscalar processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 181-190, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
46 | Peter Steenkiste, John L. Hennessy |
A Simple Interprocedural Register Allocation Algorithm and Its Effectiveness for Lisp. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 11(1), pp. 1-32, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
LISP |
46 | David W. Wall |
Global register allocation at link time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the 1986 SIGPLAN Symposium on Compiler Construction, Palo Alto, California, USA, June 25-27, 1986, pp. 264-275, 1986, ACM, 0-89791-197-0. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
46 | David W. Wall |
Global register allocation at link time (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 192-204, 1986, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
46 | Yaqiong Qiu, Yonghua Hu, Yang Li, Zhen Tang, Lin Shi |
基于两类寄存器互为缓存方法的DSP寄存器分配溢出处理优化算法 (Optimization Algorithm of Complementary Register Usage Between Two Register Classesin Register Spilling for DSP Register Allocation). ![Search on Bibsonomy](Pics/bibsonomy.png) |
计算机科学 ![In: 计算机科学 46(6), pp. 196-200, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
45 | Sebastian Hack, Gerhard Goos |
Copy coalescing by graph recoloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation, Tucson, AZ, USA, June 7-13, 2008, pp. 227-237, 2008, ACM, 978-1-59593-860-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
graph coloring, register allocation, ssa form |
45 | Yunhe Shi, David Gregg, Andrew Beatty, M. Anton Ertl |
Virtual machine showdown: stack versus registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 1st International Conference on Virtual Execution Environments, VEE 2005, Chicago, IL, USA, June 11-12, 2005, pp. 153-163, 2005, ACM, 1-59593-047-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register architecture, stack architecture, virtual machine, interpreter |
44 | Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon |
Securing More Registers with Reduced Instruction Encoding Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 417-425, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Teresa Monreal, Víctor Viñals, José González 0002, Antonio González 0001, Mateo Valero |
Late Allocation and Early Release of Physical Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(10), pp. 1244-1259, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Herbert H. J. Hum, Guang R. Gao |
A Novel High-Speed Memory Organization for Fine-Grain Multi-Thread Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE '91: Parallel Architectures and Languages Europe, Volume I: Parallel Architectures and Algorithms, Eindhoven, The Netherlands, June 10-13, 1991, Proceedings, pp. 34-51, 1991, Springer, 3-540-54151-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
43 | Xiangrong Zhou, Chenjie Yu, Peter Petrov |
Temperature-aware register reallocation for register file power-density minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 26:1-26:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Xiangrong Zhou, Chenjie Yu, Peter Petrov |
Compiler-driven register re-assignment for register file power-density and temperature reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 750-753, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
power-density minimization, thermal management |
43 | Pablo Montesinos, Wei Liu 0014, Josep Torrellas |
Using Register Lifetime Predictions to Protect Register Files against Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, 25-28 June 2007, Edinburgh, UK, Proceedings, pp. 286-296, 2007, IEEE Computer Society, 0-7695-2855-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Wann-Yun Shieh, Chien-Chen Chen |
Exploiting Register-Usage for Saving Register-File Energy in Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 37-46, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Deepankar Bairagi, Santosh Pande, Dharma P. Agrawal |
A Framework for Efficient Register Allocation through Selective Register Demotion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCR ![In: Languages, Compilers, and Run-Time Systems for Scalable Computers, 5th International Workshop, LCR 2000, Rochester, NY, USA, May 25-27, 2000, Selected Papers, pp. 57-69, 2000, Springer, 3-540-41185-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy |
A Method for Register Allocation to Loops in Multiple Register File Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 28-33, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
42 | Rei Odaira, Takuya Nakaike, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani |
Coloring-based coalescing for graph coloring register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 160-169, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
register allocation, register coalescing |
42 | Lal George, Andrew W. Appel |
Iterated Register Coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 18(3), pp. 300-324, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
copy propagation, graph coloring, register allocation, register coalescing |
42 | William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang |
Tolerating data access latency with register preloading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992, pp. 104-113, 1992, ACM, 0-89791-485-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
VLIW/superscalar processor, load latency, register preload, register file, data dependence analysis |
42 | Lefteris M. Kirousis, Evangelos Kranakis, Paul M. B. Vitányi |
Atomic Multireader Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 2nd International Workshop, Amsterdam, The Netherlands, July 8-10, 1987, Proceedings, pp. 278-296, 1987, Springer, 3-540-19366-9. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
regular, atomic, Register, reader, writer, shared register |
42 | Hongbo Rong |
Tree register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 67-77, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
register allocation, chordal graph |
42 | Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee |
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(3), pp. 269-288, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW |
42 | Christopher Zimmer 0001, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley |
Facilitating compiler optimizations through the dynamic mapping of alternate register structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 165-169, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register queues, compiler optimizations, software pipelining |
42 | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
An optimistic and conservative register assignment heuristic for chordal graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 209-217, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
static single assignment (ssa) form, chordal graph, register assignment |
42 | Koji Ohashi, Mineo Kaneko |
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 481-484, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-level synthesis, asynchronous circuit, datapath, register binding |
42 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose |
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 265-274, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
energy-efficiency, register files |
42 | Laura Pozzi, Paolo Ienne |
Exploiting pipelining to relax register-file port constraints of instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 2-10, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output |
42 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Register Constrained Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(5), pp. 417-430, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code |
42 | Xiaotong Zhuang, Tao Zhang 0037, Santosh Pande |
Hardware-managed register allocation for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 192-201, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
architected registers, physical registers, embedded systems, power consumption, register allocation |
42 | Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana |
A retargetable register allocation framework for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 202-210, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
register allocation, embedded processors |
42 | José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo |
Power-Aware Compilation for Register File Energy Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 31(6), pp. 451-467, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
register file management, compiler support, energy aware |
42 | Nam Sung Kim, Trevor N. Mudge |
The microarchitecture of a low power register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 384-389, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
write queue, low power, instruction level parallelism, register file, out-of-order processor |
42 | Volker Barthelmann |
Inter-task register-allocation for static operating systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 149-154, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
context-switch optimization, optimizing for space, register allocation |
42 | Kameswari V. Garigipati, Cindy Norris |
Evaluating the use of profiling by a region-based register allocator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), March 10-14, 2002, Madrid, Spain, pp. 953-957, 2002, ACM, 1-58113-445-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
region-based register allocation, profiling |
42 | Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar |
Exploring the Number of Register Windows in ASIP Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 233-238, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows |
42 | Byung-Sun Yang, Soo-Mook Moon, Seongbae Park, Junpyo Lee, SeungIl Lee, Jinpyo Park, Yoo C. Chung, Suhyun Kim, Kemal Ebcioglu, Erik R. Altman |
LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 128-138, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Java JIT compilation, register allocation |
42 | Madhavi Gopal Valluri, R. Govindarajan |
Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 78-83, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods |
42 | John Wood, Harold C. Grossman |
Interprocedural register allocation for RISC machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 30th Annual Southeast Regional Conference, 1992, Raleigh, North Carolina, USA, April 8-10, 1992, pp. 188-195, 1992, ACM, 0-89791-506-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
Interprocedural Register Allocation, RISC Computer, Webs, Graph Coloring |
41 | Fernando Magno Quintão Pereira, Jens Palsberg |
SSA Elimination after Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 18th International Conference, CC 2009, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009, York, UK, March 22-29, 2009. Proceedings, pp. 158-173, 2009, Springer, 978-3-642-00721-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Ge Zhang, Xu Yang, Yiwei Zhang |
Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: International Conference on Networking, Architecture, and Storage, NAS 2009, 9-11 July 2009, Zhang Jia Jie, Hunan, China, pp. 386-391, 2009, IEEE Computer Society, 978-0-7695-3741-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Ming Yang, Lixin Yu, Heping Peng |
Energy Efficient Register File with Reduced Window Partition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 14th International Conference on Parallel and Distributed Systems, ICPADS 2008, Melbourne, Victoria, Australia, December 8-10, 2008, pp. 99-104, 2008, IEEE Computer Society, 978-0-7695-3434-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Balaji V. Iyer, Thomas M. Conte |
A Power Model for Register-Sharing Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIPES ![In: Distributed Embedded Systems: Design, Middleware and Resources, IFIP 20th World Computer Congress, TC10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008), September 7-10, 2008, Milano, Italy, pp. 131-142, 2008, Springer, 978-0-387-09660-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Miquel Pericàs, Rubén González 0001, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero |
An Optimized Front-End Physical Register File with Banking and Writeback Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers, pp. 1-14, 2004, Springer, 3-540-29790-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Zhenyu Liu, Jiayue Qi |
A Novel Rename Register Architecture and Performance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 503-514, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Johan Runeson, Sven-Olof Nyström |
Retargetable Graph-Coloring Register Allocation for Irregular Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 240-254, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Santithorn Bunchua, D. Scott Wills, Linda M. Wills |
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 532-535, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Jessica H. Tseng, Krste Asanovic |
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 62-71, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Vlad Petric, Anne Bracy, Amir Roth |
Three extensions to register integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 37-47, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Krishnan Kailas, Manoj Franklin, Kemal Ebcioglu |
A Register File Architecture and Compilation Scheme for Clustered ILP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 500-511, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
Displaying result #101 - #200 of 5677 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ >>] |
|