Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter	A reconfigurable unit for a clustered programmable-reconfigurable processor.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, technology scaling, reconfigurable processor
15	Anne Bracy, Prashant Prahlad, Amir Roth	Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth.	MICRO	2004	DBLP DOI BibTeX RDF
15	Lu Peng 0001, Jih-Kwon Peir, Konrad Lai	Signature Buffer: Bridging Performance Gap between Registers and Caches.	HPCA	2004	DBLP DOI BibTeX RDF
15	Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal	Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors.	PACS	2004	DBLP DOI BibTeX RDF
15	Ljiljana Dilparic, D. K. Arvind 0001	Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices.	ASAP	2004	DBLP DOI BibTeX RDF
15	Benjamin C. Lee, Richard W. Vuduc, James Demmel, Katherine A. Yelick	Performance Models for Evaluation and Automatic Tuning of Symmetric Sparse Matrix-Vector Multiply.	ICPP	2004	DBLP DOI BibTeX RDF
15	Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das	Evaluating the Imagine Stream Architecture.	ISCA	2004	DBLP DOI BibTeX RDF
15	Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton	Continual flow pipelines.	ASPLOS	2004	DBLP DOI BibTeX RDF	CFP, non-blocking, latency tolerance, instruction window
15	Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus	On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cross-parity check, on-line BIST, multiple soft-error detection, self-repair
15	Weihaw Chuang, Brad Calder, Jeanne Ferrante	Phi-Predication for Light-Weight If-Conversion.	CGO	2003	DBLP DOI BibTeX RDF
15	Joshua Redstone, Susan J. Eggers, Henry M. Levy	Mini-Threads: Increasing TLP on Small-Scale SMT Processors.	HPCA	2003	DBLP DOI BibTeX RDF
15	Srikumar Ramalingam, Suresh K. Lodha	Adaptive Enhancement of 3D Scenes using Hierarchical Registration of Texture-Mapped 3D models.	3DIM	2003	DBLP DOI BibTeX RDF	3D model registration, scale-sensitive algorithms, hierarchical registration, image registration, 3D Reconstruction
15	Chik How Tan, Xun Yi, Chee Kheong Siew	A CCA2 Secure Key Encapsulation Scheme Based on 3rd Order Shift Registers.	ACISP	2003	DBLP DOI BibTeX RDF	adaptive chosen-ciphertext attack, Public key cryptosystem, shift registers
15	Amitabh Menon, S. K. Nandy 0001, Mahesh Mehendale	Multivoltage scheduling with voltage-partitioned variable storage.	ISLPED	2003	DBLP DOI BibTeX RDF	multivoltage, high level synthesis, datapath synthesis
15	Christoforos E. Kozyrakis, David A. Patterson 0001	Overcoming the Limitations of Conventional Vector Processors.	ISCA	2003	DBLP DOI BibTeX RDF
15	Martin Burtscher, Benjamin G. Zorn	Hybrid Load-Value Predictors.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	load-value predictor, performance metrics, Value prediction, value locality, hybrid predictor
15	Deshanand P. Singh, Stephen Dean Brown	Constrained clock shifting for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
15	Miroslav N. Velev	Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer.	DATE	2002	DBLP DOI BibTeX RDF
15	Jesús Corbal, Roger Espasa, Mateo Valero	Three-dimensional memory vectorization for high bandwidth media memory systems.	MICRO	2002	DBLP DOI BibTeX RDF
15	Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara	Design for Two-Pattern Testability of Controller-Data Path Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
15	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
15	Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus	On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check.	IOLTW	2002	DBLP DOI BibTeX RDF
15	Tsuyoshi Ebina, Fumiko Matsumoto, Hiroyuki Ohno	Fax Registration of Information about Disaster Victims.	User Interfaces for All	2002	DBLP DOI BibTeX RDF
15	Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic	Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines.	ISCA	2002	DBLP DOI BibTeX RDF	Dynamic Leakage Reduction
15	J. Adam Butts, Gurindar S. Sohi	Dynamic dead-instruction detection and elimination.	ASPLOS	2002	DBLP DOI BibTeX RDF
15	Yoon-chan Jhi, Ki-Chang Kim, Kemal Ebcioglu, Yong Surk Lee	A Prolog Tailoring Technique on an Epilog Tailored Procedure.	Ershov Memorial Conference	2001	DBLP DOI BibTeX RDF
15	Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala	CARS: A New Code Generation Framework for Clustered ILP Processors.	HPCA	2001	DBLP DOI BibTeX RDF
15	Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara	Hybrid BIST Using Partially Rotational Scan.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
15	Hyunyoung Lee, Jennifer L. Welch	Applications of Probabilistic Quorums to Iterative Algorithms.	ICDCS	2001	DBLP DOI BibTeX RDF
15	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically allocating processor resources between nearby and distant ILP.	ISCA	2001	DBLP DOI BibTeX RDF
15	Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce	The Intel IA-64 Compiler Code Generator.	IEEE Micro	2000	DBLP DOI BibTeX RDF
15	Soma Chaudhuri, Martha J. Kosa, Jennifer L. Welch	One-write algorithms for multivalued regular and atomic registers.	Acta Informatica	2000	DBLP DOI BibTeX RDF
15	Margarida F. Jacome, Gustavo de Veciana	Lower bound on latency for VLIW ASIP datapaths.	ICCAD	1999	DBLP DOI BibTeX RDF
15	C. John Glossner, Stamatis Vassiliadis	Delft-Java Dynamic Translation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
15	Faith E. Fich, Maurice Herlihy, Nir Shavit	On the Space Complexity of Randomized Synchronization.	J. ACM	1998	DBLP DOI BibTeX RDF	lower bounds, consensus, space complexity
15	Leonie Simpson, Jovan Dj. Golic, Ed Dawson	A Probabilistic Correlation Attack on the Shrinking Generator.	ACISP	1998	DBLP DOI BibTeX RDF	Cryptography, Stream ciphers, Correlation attacks, Shrinking generator
15	Silvina Hanono, Srinivas Devadas	Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
15	Milo M. K. Martin, Amir Roth, Charles N. Fischer	Exploiting Dead Value Information.	MICRO	1997	DBLP DOI BibTeX RDF
15	O. A. Petlin, Stephen B. Furber	Built-In Self-Testing of Micropipelines.	ASYNC	1997	DBLP DOI BibTeX RDF	Built-in self-test, Design for test, Asynchronous design, Micropipelines
15	Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham	Allocating Lifetimes to Queues in Software Pipelined Architectures.	Euro-Par	1997	DBLP DOI BibTeX RDF
15	Sriram Vajapeyam, Tulika Mitra	Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences.	ISCA	1997	DBLP DOI BibTeX RDF
15	Sandip K. Biswas, Sampath Kannan	Minimizing Space Usage in Evaluation of Expression Trees.	FSTTCS	1995	DBLP DOI BibTeX RDF
15	Bernhard Eschermann	An implicitly testable boundary scan TAP controller.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	test controller, BIST, self-test, boundary scan, synthesis for testability, controller design
15	Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki J. Murakami, Shinji Tomita	Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture.	ICS	1992	DBLP DOI BibTeX RDF
15	Leon Stok	Interconnect optimisation during data path allocation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
15	Norman P. Jouppi, Jonathan Bertoni, David W. Wall	A Unified Vector/Scalar Floating-Point Architecture.	ASPLOS	1989	DBLP DOI BibTeX RDF
15	Pierre G. Paulin, John P. Knight	Scheduling and Binding Algorithms for High-Level Synthesis.	DAC	1989	DBLP DOI BibTeX RDF
15	Thomas Philip	Using animated color graphics to illustrate software and hardware organizations (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
15	Sibylle Mund, Dieter Gollmann, Thomas Beth	Some Remarks on the Cross Correlation Analysis of Pseudo Random Generators.	EUROCRYPT	1987	DBLP DOI BibTeX RDF
15	William R. Bush, A. Dain Samples, David M. Ungar, Paul N. Hilfinger	Compiling Smalltalk-80 to a RISC.	ASPLOS	1987	DBLP DOI BibTeX RDF	RISC, Smalltalk-80
11	Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa	CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
11	Jinwu Chen, Yitong Zhao, Tianzhu Xiong, Xin Si	An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Zhang Jiang, Ying Chen, Xiaoli Gong, Jin Zhang 0003, Wenwen Wang 0001, Pen-Chung Yew	JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation.	ACM Trans. Archit. Code Optim.	2024	DBLP DOI BibTeX RDF
11	Simon Dierl, Paul Fiterau-Brostean, Falk Howar, Bengt Jonsson 0001, Konstantinos Sagonas, Fredrik Tåquist	Scalable Tree-based Register Automata Learning.	CoRR	2024	DBLP DOI BibTeX RDF
11	Elizaveta Sivak, Paulina Pankowska, Adriënne Mendrik, Tom Emery, Javier Garcia-Bernardo, Seyit Hocuk, Kasia Karpinska, Angelica Maineri, Joris Mulder, Malvina Nissim, Gert Stulp	Combining the Strengths of Dutch Survey and Register Data in a Data Challenge to Predict Fertility (PreFer).	CoRR	2024	DBLP DOI BibTeX RDF
11	Frederik Dermot Pustelnik, Xhani Marvin Saß, Jean-Pierre Seifert	Whispering Pixels: Exploiting Uninitialized Register Accesses in Modern GPUs.	CoRR	2024	DBLP DOI BibTeX RDF
11	Xiaofeng Guan, Hao Zhou, Guoqing Bao, Handong Li, Liang Zhu, Jianguo Yao	PresCount: Effective Register Allocation for Bank Conflict Reduction.	CGO	2024	DBLP DOI BibTeX RDF
11	Youngseok Baek, Bontae Koo	The High-Performance Convolution Design and Implementation Using Parallel Memory Processing and Shift Register Pipeline.	ICEIC	2024	DBLP DOI BibTeX RDF
11	Yen-Yu Chen, Hao-Yu Wu, Iris Hui-Ru Jiang, Cheng-Hong Tsai, Chien-Cheng Wu	Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops.	ISPD	2024	DBLP DOI BibTeX RDF
11	Yipeng Wang 0017, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni	30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Simon Dierl, Paul Fiterau-Brostean, Falk Howar, Bengt Jonsson 0001, Konstantinos Sagonas, Fredrik Tåquist	Scalable Tree-based Register Automata Learning.	TACAS (2)	2024	DBLP DOI BibTeX RDF
11	Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa	SRIL: Securing Registers from Information Leakage at Register Transfer Level.	VLSID	2024	DBLP DOI BibTeX RDF
11	Lucas Wilkinson, Kazem Cheshmi, Maryam Mehri Dehnavi	Register Tiling for Unstructured Sparsity in Neural Network Inference.	Proc. ACM Program. Lang.	2023	DBLP DOI BibTeX RDF
11	Tao Zhang 0081, Zhanpeng He, Zhihua Chen	A Decoupling Matrix-Based Learning Control Scheme for the Machine Directional Register of Roll-to-Roll Systems.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
11	Thomas Feliciani, Jochem Tolsma, Andreas Flache	Ethnic segregation and spatial patterns of attitudes: studying the link using register data and social simulation.	J. Comput. Soc. Sci.	2023	DBLP DOI BibTeX RDF
11	Kai Lehniger, Peter Langendörfer	Through the Window: Exploitation and Countermeasures of the ESP32 Register Window Overflow.	Future Internet	2023	DBLP DOI BibTeX RDF
11	Sarwono Sutikno, Septafiansyah Dwi Putra, Fajar Wijitrisnanto, Muhamad Erza Aminanto	Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features.	IEEE Access	2023	DBLP DOI BibTeX RDF
11	Zongnan Liang, Jiawei Nian, Hongjin Liu, Xuru Wang, Mengfei Yang	C-DMR: a cache-based fault-tolerant protection method for register file.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
11	Veronika Laippala, Samuel Rönnqvist, Miika Oinonen, Aki-Juhani Kyröläinen, Anna Salmela, Douglas Biber, Jesse Egbert, Sampo Pyysalo	Register identification from the unrestricted open Web using the Corpus of Online Registers of English.	Lang. Resour. Evaluation	2023	DBLP DOI BibTeX RDF
11	Van Nhan Nguyen, Jong-Wook Lee	A 4.7-ps Resolution Recirculating Cyclic Vernier TDC Using DWA-Based Mismatch Correction and a Register-Based Time Amplifier.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
11	Saleh Abdel-Hafeez	Programmable Feedback Shift Register.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
11	Kuozhong Zhang, Zhimin Zhang 0004, Guang-Ming Tang, Xiaochun Ye	Design of a Compact Superconducting RSFQ Register File.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, George Michelogiannakis	Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Piia Hyvämäki, Sami Sneck, Merja Meriläinen, Minna Pikkarainen, Maria Kääriäinen, Miia Jansson	Interorganizational health information exchange-related patient safety incidents: A descriptive register-based qualitative study.	Int. J. Medical Informatics	2023	DBLP DOI BibTeX RDF
11	Silvia Bonomi, Antonella Del Pozzo, Maria Potop-Butucaru, Sébastien Tixeuil	Optimal self-stabilizing mobile byzantine-tolerant regular register with bounded timestamps.	Theor. Comput. Sci.	2023	DBLP DOI BibTeX RDF
11	David A. Levin, Chandan Tankala	Fast mixing of a randomized shift-register Markov chain.	J. Appl. Probab.	2023	DBLP DOI BibTeX RDF
11	Qiang Zhang, Lei Xu 0003, Baowen Xu	RegCPython: A Register-based Python Interpreter for Better Performance.	ACM Trans. Archit. Code Optim.	2023	DBLP DOI BibTeX RDF
11	Yu Fu, Jingqiang Lin, Dengguo Feng, Wei Wang 0314, Mingyu Wang, Wenjie Wang	RegKey: A Register-based Implementation of ECC Signature Algorithms Against One-shot Memory Disclosure.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
11	Celia Soler Uguet, Nora Aranberri	Exploring politeness control in NMT: fine-tuned vs. multi-register models in Castilian Spanish.	Proces. del Leng. Natural	2023	DBLP BibTeX RDF
11	Shao-Xiang Go, Qiang Wang, Kejie Huang, Tae Hoon Lee, Natasa Bajalovic, Desmond K. Loke	Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by Phase-Change Memory Materials.	Adv. Intell. Syst.	2023	DBLP DOI BibTeX RDF
11	Dongwei Pang, Lingling Wei, Shiwei Wu, Biao Deng, Yongfeng Gui, Zongming Duan, Gang Wang 0032	A ku-band common-leg transceiver with built-in configurable register in 130-nm CMOS technology for phased-array systems.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
11	Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González 0001	A Lightweight, Compiler-Assisted Register File Cache for GPGPU.	CoRR	2023	DBLP DOI BibTeX RDF
11	Antonella Del Pozzo, Antoine Lavandier, Alexandre Rapetti	Preliminaries paper: Byzantine Tolerant Strong Auditable Atomic Register.	CoRR	2023	DBLP DOI BibTeX RDF
11	Lewis Tseng, Neo Zhou, Cole Dumas, Tigran Bantikyan, Roberto Palmieri	Distributed Multi-writer Multi-reader Atomic Register with Optimistically Fast Read and Write.	CoRR	2023	DBLP DOI BibTeX RDF
11	Vamsi K. Vytla, Larry Doolittle	Newad: A register map automation tool for Verilog.	CoRR	2023	DBLP DOI BibTeX RDF
11	Michal R. Przybylek	A note on encoding infinity in ZFA with applications to register automata.	CoRR	2023	DBLP DOI BibTeX RDF
11	Andrew J. Adiletta, M. Caner Tol, Yarkin Doröz, Berk Sunar	Mayhem: Targeted Corruption of Register and Stack Variables.	CoRR	2023	DBLP DOI BibTeX RDF
11	Sadaf Bashir, Salma Yaqoob, Suhaib Ahmed	Design of QCA based N-bit single layer shift register using efficient JK Flip Flop for nano-communication applications.	Nano Commun. Networks	2023	DBLP DOI BibTeX RDF
11	Sheng Xiao, Yong Chen, Jing He, Xi Yang	Read-Write Dependency Aware Register Allocation.	Comput. Syst. Sci. Eng.	2023	DBLP DOI BibTeX RDF
11	Malin Berglund, Sara Olaison, Eva Westman, P. O. Eriksson, Lena Steger, Åsa Bonnard	Validation of the Swedish Quality Register for Ear Surgery - SwedEar.	BMC Medical Informatics Decis. Mak.	2023	DBLP DOI BibTeX RDF
11	Bernd Lorenz, Vesna Steyer	Terminologie der Information und Dokumentation Grundwortschatz, 3., neu bearbeitete Ausgabe (TID 3.1). Axel Ermert, Monika Hagedorn-Saupe, Barbara Müller-Heiden, Marlies Ockenfeld (Redaktion). Fachgruppe Arbeitskreis Terminologie und Sprachfragen (AKTS) der Deutschen Gesellschaft für Information und Wissen (DGI). - Frankfurt am Main 2023, (DGI-Schrift Informationswissenschaft - 13; ISSN 0940 6662). - XII + 144 Seiten, Register, Verzeichnis englischer und französischer Benennungen. - ISBN Gebundene Ausgabe 978-3-925474-74-3, ISBN E-Book (PDF) 978-3-925474-75-0, 19,80 Euro (für DGI-Mitglieder 15,80 Euro).	Inf. Wiss. Prax.	2023	DBLP DOI BibTeX RDF
11	Yoshiaki Takata, Akira Onishi, Ryoma Senda, Hiroyuki Seki	A Subclass of Mu-Calculus with the Freeze Quantifier Equivalent to Register Automata.	IEICE Trans. Inf. Syst.	2023	DBLP DOI BibTeX RDF
11	Matthieu Ruthven, Marc E. Miquel, Andrew P. King	A segmentation-informed deep learning framework to register dynamic two-dimensional magnetic resonance images of the vocal tract during speech.	Biomed. Signal Process. Control.	2023	DBLP DOI BibTeX RDF
11	Vikas Ramesh Kamath, R. Chokkanathapuram Sundaram, Raunak Banthia, Ananya Gopal	PIM Null-Register Packing.	RFC	2023	DBLP DOI BibTeX RDF
11	Heidi Rimer, Melina Sofie Jensen, Sara Elisabeth Dahlsgaard-Wallenius, Lise Eckhoff, Peter Thye-Rønn, Charlotte Kristiansen, Malene Grubbe Hildebrandt, Oke Gerke	2-[18F]FDG-PET/CT in Cancer of Unknown Primary Tumor - A Retrospective Register-Based Cohort Study.	J. Imaging	2023	DBLP DOI BibTeX RDF
11	Barbara Balon, Krzysztof Kalinowski, Iwona Paprocka	Production Planning Using a Shared Resource Register Organized According to the Assumptions of Blockchain Technology.	Sensors	2023	DBLP DOI BibTeX RDF
11	Elham Ebrahimpour, Shahram Babaie	A Lightweight authentication approach based on linear feedback shift register and majority function for internet of things.	Peer Peer Netw. Appl.	2023	DBLP DOI BibTeX RDF
11	Jaroslav Hrdina, Dietmar Hildenbrand, Ales Návrat, Christian Steinmetz, Rafael Alves, Carlile Lavor, Petr Vasík, Ivan Eryganov	Quantum Register Algebra: the mathematical language for quantum computing.	Quantum Inf. Process.	2023	DBLP DOI BibTeX RDF
11	Kai Lehniger, Peter Langendörfer	Window Canaries: Re-Thinking Stack Canaries for Architectures With Register Windows.	IEEE Trans. Dependable Secur. Comput.	2023	DBLP DOI BibTeX RDF
11	M. H. Bandukara, Nikos Tzevelekos	On-the-fly bisimulation equivalence checking for fresh-register automata.	J. Syst. Archit.	2023	DBLP DOI BibTeX RDF