Search results for "ASP-DAC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Yi-Siang Su, Tsung-Yi Ho, Der-Tsai Lee	A routability-driven flow routing algorithm for programmable microfluidic devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Matthias Jung 0001, Deepak M. Mathew, Christian Weis, Norbert Wehn	Efficient reliability management in SoCs - an approximate DRAM perspective.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler	BDD minimization for approximate computing.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Xing Wei, Yi Diao, Yu-Liang Wu	To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar	Logic and memory design using spin-based circuits.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho	Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung	Recent research development and new challenges in analog layout synthesis.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Hrishikesh Jayakumar, Arnab Raha, Younghyun Kim 0001, Soubhagya Sutar, Woo Suk Lee, Vijay Raghunathan	Energy-efficient system design for IoT devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy 0001	Computing with coupled Spin Torque Nano Oscillators.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang I Vai, Sio-Hang Pun, Rui Paulo Martins	Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Tetsuaki Matsunawa, Bei Yu 0001, David Z. Pan	Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Petra R. Maier, Veit B. Kleeberger	Embedded software reliability testing by unit-level fault injection.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Deokjin Joo, Taewhan Kim	Clock buffer polarity assignment utilizing useful clock skews for power noise reduction.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Sebastian Ottlik, Jan Micha Borrmann, Sadik Asbach, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann 0001	Trace-based context-sensitive timing simulation considering execution path variations.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, Yuan Xie 0001	Architecture design with STT-RAM: Opportunities and challenges.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Xian Zhang 0001, Guangyu Sun 0003, Yaojun Zhang, Yiran Chen 0001, Hai Li 0001, Wujie Wen, Jia Di	A novel PUF based on cell error rate distribution of STT-RAM.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa	A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Bin Lin, Zhenkun Yang, Kai Cong, Fei Xie	Generating high coverage tests for SystemC designs using symbolic execution.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Jacob Wurm, Khoa Hoang, Orlando Arias, Ahmad-Reza Sadeghi, Yier Jin	Security analysis on consumer and industrial IoT devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Nikolay Matyunin, Jakub Szefer, Sebastian Biedermann, Stefan Katzenbeisser 0001	Covert channels using mobile device's magnetic field sensors.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Anastasis Keliris, Charalambos Konstantinou, Nektarios Georgios Tsoutsos, Raghad Baiad, Michail Maniatakos	Enabling multi-layer cyber-security assessment of Industrial Control Systems through Hardware-In-The-Loop testbeds.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei	Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang	Negotiation-based track assignment considering local nets.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Louis Y.-Z. Lin, Charles H.-P. Wen	Speed binning with high-quality structural patterns from functional timing analysis (FTA).	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Dongsheng Yang 0002, Wei Deng 0001, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa	An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Lei Yang 0018, Weichen Liu, Weiwen Jiang, Mengquan Li, Juan Yi, Edwin Hsing-Mean Sha	FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Huizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, Qingfeng Zhuge	Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Khondker Z. Ahmed, Monodeep Kar, Saibal Mukhopadhyay	(Invited paper) energy delivery for self-powered IoT devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang	Circular-contour-based obstacle-aware macro placement.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Fengxian Jiao, Sheqin Dong	Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee	Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli	Majority-based synthesis for nanotechnologies.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Zhi-Wen Lin, Yao-Wen Chang	Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Daohang Shi, Edward Tashjian, Azadeh Davoodi	Dynamic planning of local congestion from varying-size vias for global routing layer assignment.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen	Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo	A variable-voltage low-power technique for digital circuit system.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Yidi Liu, Benjamin Carrión Schäfer	Optimization of behavioral IPs in multi-processor system-on-chips.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Kent W. Nixon, Xiang Chen 0010, Yiran Chen 0001	Footfall - GPS polling scheduler for power saving on wearable devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Yibo Lin, Bei Yu 0001, Yi Zou, Zhuo Li 0001, Charles J. Alpert, David Z. Pan	Stitch aware detailed placement for multiple e-beam lithography.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita	Formally analyzing fault tolerance in datapath designs using equivalence checking.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu	Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates).	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Bo Wang 0012, Man Kay Law, Saqib Mohamad, Amine Bermak	A 2.2µW 15b incremental delta-sigma ADC with output-driven input segmentation.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Xinfei Guo, Mircea R. Stan	Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst	Dynamic admission control for real-time networks-on-chips.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Fa Wang, Shihui Yin, Minhee Jun, Xin Li 0001, Tamal Mukherjee, Rohit Negi, Larry T. Pileggi	Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Andrés Takach	Design and verification using high-level synthesis.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori	Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Ryan Berryhill, Andreas G. Veneris	A complete approach to unreachable state diagnosability via property directed reachability.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Andrew Hennessy, Yu Zheng 0011, Swarup Bhunia	JTAG-based robust PCB authentication for protection against counterfeiting attacks.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Zana Ghaderi, Eli Bozorgzadeh	Aging-aware high-level physical planning for reconfigurable systems.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Xin Huang 0003, Valeriy Sukharev, Taeyoung Kim 0001, Hai-Bao Chen, Sheldon X.-D. Tan	Electromigration recovery modeling and analysis under time-dependent current and temperature stressing.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Jian Deng, Haotian Liu, Kim Batselier, Yu-Kwong Kwok, Ngai Wong	STORM: A nonlinear model order reduction method via symmetric tensor decomposition.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Zhe Yuan, Yongpan Liu, Hehe Li, Huazhong Yang	CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Kent W. Nixon, Xiang Chen 0010, Zhi-Hong Mao, Yiran Chen 0001	SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimization.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan	Every test makes a difference: Compressing analog tests to decrease production costs.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Minkyu Song, Joseph Sankman, Jayeol Lee, Dongsheng Brian Ma	A 200-MHz 4-phase fully integrated voltage regulator with local ground sensing dual loop ZDS hysteretic control using 6.5nH package bondwire inductors on 65nm bulk CMOS.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo	Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Chi-Ruo Wu, Wei Wen, Tsung-Yi Ho, Yiran Chen 0001	Thermal optimization for memristor-based hybrid neuromorphic computing systems.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin	A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi	Extending trace history through tapered summaries in post-silicon validation.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Xin He, Guihai Yan, Yinhe Han 0001, Xiaowei Li 0001	ACR: Enabling computation reuse for approximate computing.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou	Chain-based pin count minimization for general-purpose digital microfluidic biochips.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Swagath Venkataramani, Kaushik Roy 0001, Anand Raghunathan	Efficient embedded learning for IoT devices.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer 0002, Hans-Joachim Wunderlich, Bernd Becker 0001	Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Santanu Sarma, Tiago Mück, Majid Shoushtari, Abbas BanaiyanMofrad, Nikil D. Dutt	Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Hyoungseok Moon, Taewhan Kim	Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Mohammad Abdullah Al Faruque, Korosh Vatanparvar	Modeling, analysis, and optimization of Electric Vehicle HVAC systems.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Yizi Gu, Yongpan Liu, Yiqun Wang, Hehe Li, Huazhong Yang	NVPsim: A simulator for architecture explorations of nonvolatile processors.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li 0006	MCSSim: A memory channel storage simulator.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath	Learning-based prediction of embedded memory timing failures during initial floorplan design.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li 0005	Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1		21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016	ASP-DAC	2016	DBLP BibTeX RDF
1	Kuan Fan, Ming-Jen Yang, Chung-Yang Huang	Automatic abstraction refinement of TR for PDR.	ASP-DAC	2016	DBLP DOI BibTeX RDF
1	Ta-Yang Huang, Chia-Jui Chang, Chung-Wei Lin, Sudip Roy 0001, Tsung-Yi Ho	Intra-vehicle network routing algorithm for wiring weight and wireless transmit power minimization.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Nima Aghaee, Zebo Peng, Petru Eles	An integrated temperature-cycling acceleration and test technique for 3D stacked ICs.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Minjie Lv, Hongbin Sun 0001, Jingmin Xin, Nanning Zheng 0001	Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury	BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Bei Yu 0001, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng 0001	Machine learning and pattern matching in physical design.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi 0001, Shigeki Nojima, Satoshi Tanaka	Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang 0003, Chen Li 0015	Adaptive remaining hop count flow control: Consider the interaction between packets.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Wulong Liu, Guoqing Chen, Yu Wang 0002, Huazhong Yang	Modeling and optimization of low power resonant clock mesh.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori	Stress-aware P/G TSV planning in 3D-ICs.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro	Dual-output wireless power delivery system for small size large volume wireless memory card.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Lian Zeng, Takahiro Watanabe	A performance enhanced dual-switch Network-on-Chip architecture.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Lingxiao Wei, Jie Zhang 0046, Feng Yuan, Yannan Liu, Junfeng Fan, Qiang Xu 0001	Vulnerability analysis for crypto devices against probing attack.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Zipeng Li, Tsung-Yi Ho, Krishnendu Chakrabarty	Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay	AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Mimi Xie, Chen Pan, Jingtong Hu, Chengmo Yang, Yiran Chen 0001	Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Yu-Wei Wu, Yiyu Shi 0001, Sudip Roy 0001, Tsung-Yi Ho	Obstacle-avoiding wind turbine placement for power-loss and wake-effect optimization.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Mojtaba Ebrahimi, Razi Seyyedi, Liang Chen 0014, Mehdi Baradaran Tahoori	Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Ji Li 0006, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram	Negotiation-based task scheduling and storage control algorithm to minimize user's electric bills under dynamic prices.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang 0001	Contact pitch and location prediction for Directed Self-Assembly template verification.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Soroush Khaleghi, Kai Da Zhao, Wenjing Rao	IC Piracy prevention via Design Withholding and Entanglement.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno	Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Sixing Lu, Minjun Seo, Roman Lysecky	Timing-based anomaly detection in embedded systems.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou	Design of a scalable many-core processor for embedded applications.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Volker Meyer zu Bexten, Markus Tristl, Göran Jerke, Hartmut Marquardt, Dina Medhat	Physical verification flow for hierarchical analog ic design constraints.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Jiaxing Zhang, Sanyuan Tang, Gunar Schirner	Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded software.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Daifeng Guo, Yuelin Du, Martin D. F. Wong	Polynomial time optimal algorithm for stencil row planning in e-beam lithography.	ASP-DAC	2015	DBLP DOI BibTeX RDF
1	Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems.	ASP-DAC	2015	DBLP DOI BibTeX RDF

Publications at "ASP-DAC"( http://dblp.L3S.de/Venues/ASP-DAC )