Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
29 | Randal E. Bryant |
Multipliers and Dividers: Insights on Arithmetic Circuits Verification (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 1-3, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Sathiamoorthy Subbarayan |
Efficient Reasoning for Nogoods in Constraint Solvers with BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADL ![In: Practical Aspects of Declarative Languages, 10th International Symposium, PADL 2008, San Francisco, CA, USA, January 7-8, 2008., pp. 53-67, 2008, Springer, 978-3-540-77441-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Hasan Amjad |
LCF-Style Propositional Simplification with BDDs and SAT Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 21st International Conference, TPHOLs 2008, Montreal, Canada, August 18-21, 2008. Proceedings, pp. 55-70, 2008, Springer, 978-3-540-71065-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Stefan Edelkamp, Peter Kissmann |
Limits and Possibilities of BDDs in State Space Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KI ![In: KI 2008: Advances in Artificial Intelligence, 31st Annual German Conference on AI, KI 2008, Kaiserslautern, Germany, September 23-26, 2008. Proceedings, pp. 46-53, 2008, Springer, 978-3-540-85844-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 131-136, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Ryutaro Kurai, Shin-ichi Minato, Thomas Zeugmann |
N-Gram Analysis Based on Zero-Suppressed BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JSAI ![In: New Frontiers in Artificial Intelligence, JSAI 2006 Conference and Workshops, Tokyo, Japan, June 5-9 2006, Revised Selected Papers, pp. 289-300, 2006, Springer, 3-540-69901-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Sathiamoorthy Subbarayan |
Integrating CSP Decomposition Techniques and BDDs for Compiling Configuration Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPAIOR ![In: Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, Second International Conference, CPAIOR 2005, Prague, Czech Republic, May 30 - June 1, 2005, Proceedings, pp. 351-365, 2005, Springer, 3-540-26152-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Shin-ichi Minato |
Efficient Database Analysis Using VSOP Calculator Based on Zero-Suppressed BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JSAI Workshops ![In: New Frontiers in Artificial Intelligence, Joint JSAI 2005 Workshop Post-Proceedings, pp. 169-181, 2005, Springer, 3-540-35470-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Shan-Tai Chen, Shun-Shii Lin, Li-Te Huang, Chun-Jen Wei |
Towards the Exact Minimization of BDDs-An Elitism-Based Distributed Evolutionary Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Heuristics ![In: J. Heuristics 10(3), pp. 337-355, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DEBEA, EBEA, paralleled algorithm, evolutionary algorithm, Binary Decision Diagram, heuristic algorithm |
29 | Aarti Gupta, Malay K. Ganai, Chao Wang 0001, Zijiang Yang 0006, Pranav Ashar |
Abstraction and BDDs Complement SAT-Based BMC in DiVer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 15th International Conference, CAV 2003, Boulder, CO, USA, July 8-12, 2003, Proceedings, pp. 206-209, 2003, Springer, 3-540-40524-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski |
Fast Computation of Data Correlation Using BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10122-10129, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Sherief Reda, Rolf Drechsler, Alex Orailoglu |
On the Relation between SAT and BDDs for Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 394-399, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Shin-ichi Minato |
Zero-suppressed BDDs and their applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 156-170, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Boolean function, BDD, Combinatorial problem, VLSI CAD, ZBDD |
29 | Michael J. C. Gordon |
Reachability Programming in HOL98 Using BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 13th International Conference, TPHOLs 2000, Portland, Oregon, USA, August 14-18, 2000, Proceedings, pp. 179-196, 2000, Springer, 3-540-67863-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi |
An Application of Genetic Algorithms and BDDs to Functional Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 48-56, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Armin Biere, Edmund M. Clarke, Richard Raimi, Yunshan Zhu |
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings, pp. 60-71, 1999, Springer, 3-540-66202-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Wolfgang Günther 0001, Rolf Drechsler |
Minimization of BDDs using linear transformations based on evolutionary techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 387-390, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Rolf Drechsler, Nicole Drechsler, Wolfgang Günther 0001 |
Fast Exact Minimization of BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 200-205, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
29 | Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz |
Approximate Reachability with BDDs Using Overlapping Projections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 451-456, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
29 | Andreas Hett, Rolf Drechsler, Bernd Becker 0001 |
Fast and efficient construction of BDDs by reordering based synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 168-175, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Zhuxing Zhao, Zhongcheng Li, Yinghua Min |
Waveform Polynomial Manipulation Using Bdds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 136-141, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
waveform polynomial manipulation, design verification and test, middle size circuits, complexity, data structure, high level synthesis, timing, logic design, combinational circuit, logic synthesis, binary decision diagram, directed acyclic graph, digital circuit, Boolean process |
29 | Jean Goubault |
Proving with BDDs and Control of Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CADE ![In: Automated Deduction - CADE-12, 12th International Conference on Automated Deduction, Nancy, France, June 26 - July 1, 1994, Proceedings, pp. 499-513, 1994, Springer, 3-540-58156-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis |
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 47-52, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Transistor networks, logic synthesis, BDDs, Logical effort |
29 | Alain Griffault, Aymeric Vincent |
The Mec 5 Model-Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings, pp. 488-491, 2004, Springer, 3-540-22342-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
AltaRica, model-checking, BDDs, calculus |
29 | Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers |
Efficient Pattern Mapping for Deterministic Logic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 48-56, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BDDs, Logic BIST |
29 | Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah |
FORCE: a fast and easy-to-implement variable-ordering heuristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 116-119, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
partitioning, placement, SAT, BDDs, hypergraph, CNF, pre-processing, backtrack search, variable order |
29 | Ilia Polian, Irith Pomeranz, Bernd Becker 0001 |
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 2-14, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
n-detection, BDDs, formal techniques, Fault dominance |
29 | Valeria Bertacco, Kunle Olukotun |
Efficient state representation for symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 99-104, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
formal verification, BDDs, symbolic simulation |
29 | Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton |
Combinational Verification based on High-Level Functional Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 803-808, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Combinational verification, Domain transformations, BDDs |
29 | Michele Favalli, Marcello Dalpasso |
Symbolic Handling of Bridging Fault Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(3), pp. 271-276, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault simulation, bridging faults, binary decision diagrams (BDDs) |
29 | Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross |
Efficient variable ordering and partial representation algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 81-86, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partial representation algorithm, ordered partial decision diagrams, information-theoretic criteria, CAD problems, VLSI, data structures, data structures, entropy, Boolean functions, Boolean function, logic CAD, BDDs, variable ordering, truth table |
20 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 198-204, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Ken Friis Larsen |
A MuDDy Experience-ML Bindings to a BDD Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSL ![In: Domain-Specific Languages, IFIP TC 2 Working Conference, DSL 2009, Oxford, UK, July 15-17, 2009, Proceedings, pp. 45-57, 2009, Springer, 978-3-642-03033-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Jochen Eisinger, Felix Klaedtke |
Don't care words with an application to the automata-based approach for real addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 33(1-3), pp. 85-115, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Mixed linear arithmetic over the integers and reals, Verification of infinite-state systems, Decision procedure, Automata theory |
20 | Hyondeuk Kim, HoonSang Jin, Kavita Ravi, Petr Spacek, John Pierce, Robert P. Kurshan, Fabio Somenzi |
Application of Formal Word-Level Analysis to Constrained Random Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 487-490, 2008, Springer, 978-3-540-70543-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Stefan Edelkamp, Peter Kissmann |
Partial Symbolic Pattern Databases for Optimal Sequential Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KI ![In: KI 2008: Advances in Artificial Intelligence, 31st Annual German Conference on AI, KI 2008, Kaiserslautern, Germany, September 23-26, 2008. Proceedings, pp. 193-200, 2008, Springer, 978-3-540-85844-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Marcílio Mendonça, Andrzej Wasowski, Krzysztof Czarnecki 0001, Donald D. Cowan |
Efficient compilation techniques for large scale feature models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, 7th International Conference, GPCE 2008, Nashville, TN, USA, October 19-23, 2008, Proceedings, pp. 13-22, 2008, ACM, 978-1-60558-267-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal verification, model-driven development, software-product lines, configuration, feature modeling |
20 | Hamid Shojaei, Twan Basten, Marc Geilen, Phillip Stanley-Marbell |
SPaC: a symbolic pareto calculator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 179-184, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
binay decision diagram, pareto algeba, embedded systems |
20 | Esben Rune Hansen |
Encoding CSPs with Zero-Suppressed Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI (1) ![In: 20th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2008), November 3-5, 2008, Dayton, Ohio, USA, Volume 1, pp. 477-485, 2008, IEEE Computer Society, 978-0-7695-3440-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Zhi-Hong Tao, Conghua Zhou, Zhong Chen, Lifu Wang |
Bounded Model Checking of CTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(1), pp. 39-43, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
symbolic model checking, bounded model checking, QBF, CTL* |
20 | P. W. Chandana Prasad, Ali Assi 0001, Azam Beg |
Binary Decision Diagrams and neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 39(3), pp. 301-320, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
BDD complexity, Neural network, Binary decision diagrams, Complexity estimation |
20 | Gianfranco Ciardo, Gerald Lüttgen, Andrew S. Miner |
Exploiting interleaving semantics in symbolic state-space generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 31(1), pp. 63-100, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Symbolic state-space exploration, Decision diagrams, Kronecker algebra, Interleaving semantics |
20 | Tarik Hadzic, John N. Hooker |
Cost-Bounded Binary Decision Diagrams for 0-1 Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPAIOR ![In: Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 4th International Conference, CPAIOR 2007, Brussels, Belgium, May 23-26, 2007, Proceedings, pp. 84-98, 2007, Springer, 978-3-540-72396-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Gérard Basler, Daniel Kroening, Georg Weissenbacher |
SAT-Based Summarization for Boolean Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 14th International SPIN Workshop, Berlin, Germany, July 1-3, 2007, Proceedings, pp. 131-148, 2007, Springer, 978-3-540-73369-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Natasa Miskov-Zivanov, Diana Marculescu |
Circuit Reliability Analysis Using Symbolic Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2638-2649, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Gregor Snelting, Torsten Robschink, Jens Krinke |
Efficient path conditions in dependence graphs for software safety analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Softw. Eng. Methodol. ![In: ACM Trans. Softw. Eng. Methodol. 15(4), pp. 410-457, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
program slicing, information flow control, Safety analysis, path condition |
20 | Jochen Eisinger, Felix Klaedtke |
Don't Care Words with an Application to the Automata-Based Approach for Real Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 18th International Conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006, Proceedings, pp. 67-80, 2006, Springer, 3-540-37406-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Felipe Machado, Teresa Riesgo, Yago Torroja |
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 645-657, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Ming-Hong Su, Chun-Yao Wang |
High level equivalence symmetric input identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 249-253, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Karim Boutaleb, Philippe Jégou, Cyril Terrioux |
(No)good Recording and ROBDDs for Solving Structured (V)CSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 18th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2006), 13-15 November 2006, Arlington, VA, USA, pp. 297-304, 2006, IEEE Computer Society, 0-7695-2728-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Prakash Mohan Peranandam, Pradeep Kumar Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel |
Fast falsification based on symbolic bounded property checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1077-1082, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fast falsification, guiding, property checking |
20 | Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura |
Average Path Length of Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(9), pp. 1041-1053, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
average path length, worst-case path length, APL, Binary decision diagrams, BDD |
20 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combining ordered best-first search with branch and bound for exact BDD minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10), pp. 1515-1529, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Nils Klarlund |
Relativizations for the Logic-Automata Connection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
High. Order Symb. Comput. ![In: High. Order Symb. Comput. 18(1-2), pp. 79-120, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Rüdiger Ebendt, Rolf Drechsler |
Exact BDD Minimization for Path-Related Objective Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 299-315, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | John Whaley, Dzintars Avots, Michael Carbin, Monica S. Lam |
Using Datalog with Binary Decision Diagrams for Program Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APLAS ![In: Programming Languages and Systems, Third Asian Symposium, APLAS 2005, Tsukuba, Japan, November 2-5, 2005, Proceedings, pp. 97-118, 2005, Springer, 3-540-29735-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Parosh Aziz Abdulla, Johann Deneux, Lisa Kaati, Marcus Nilsson |
Minimization of Non-deterministic Automata with Large Alphabets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 10th International Conference, CIAA 2005, Sophia Antipolis, France, June 27-29, 2005, Revised Selected Papers, pp. 31-42, 2005, Springer, 3-540-31023-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Monica S. Lam, John Whaley, V. Benjamin Livshits, Michael C. Martin, Dzintars Avots, Michael Carbin, Christopher Unkel |
Context-sensitive program analysis as database queries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODS ![In: Proceedings of the Twenty-fourth ACM SIGACT-SIGMOD-SIGART Symposium on Principles of Database Systems, June 13-15, 2005, Baltimore, Maryland, USA, pp. 1-12, 2005, ACM, 1-59593-062-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | David Ward, Fabio Somenzi |
Automatic Generation of Hints for Symbolic Traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 207-221, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Sebastian Kinder, Görschwin Fey, Rolf Drechsler |
Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 250-255, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Tarik Hadzic, Henrik Reif Andersen |
Interactive Reconfiguration in Power Supply Restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CP ![In: Principles and Practice of Constraint Programming - CP 2005, 11th International Conference, CP 2005, Sitges, Spain, October 1-5, 2005, Proceedings, pp. 767-771, 2005, Springer, 3-540-29238-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Kairong Qian, Albert Nymeyer, Steven Susanto |
Experiments with Multiple Abstraction Heuristics in Symbolic Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SARA ![In: Abstraction, Reformulation and Approximation, 6th International Symposium, SARA 2005, Airth Castle, Scotland, UK, July 26-29, 2005, Proceedings, pp. 290-304, 2005, Springer, 3-540-27872-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Jun Yuan 0007, Adnan Aziz, Carl Pixley, Ken Albin |
Simplifying Boolean constraint solving for random simulation-vector generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3), pp. 412-420, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | HoonSang Jin, Mohammad Awedh, Fabio Somenzi |
CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings, pp. 519-522, 2004, Springer, 3-540-22342-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Andrew S. Miner, David Parker 0001 |
Symbolic Representations and Analysis of Large Probabilistic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Validation of Stochastic Systems ![In: Validation of Stochastic Systems - A Guide to Current Research, pp. 296-338, 2004, Springer, 3-540-22265-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combining ordered best-first search with branch and bound for exact BDD minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 875-878, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Sumit Gulwani, George C. Necula |
Path-Sensitive Analysis for Linear Arithmetic and Uninterpreted Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 11th International Symposium, SAS 2004, Verona, Italy, August 26-28, 2004, Proceedings, pp. 328-343, 2004, Springer, 3-540-22791-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening |
A SAT-based algorithm for reparameterization in symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 524-529, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SAT checkers, safety property checking, bounded model checking, symbolic simulation, parametric representation |
20 | Nikhil Saluja, Sunil P. Khatri |
A robust algorithm for approximate compatible observability don't care (CODC) computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 422-427, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
compatible observability don't cares (CODC), multi-level logic optimization, logic synthesis |
20 | Wolfgang Günther 0001, Rolf Drechsler |
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(9), pp. 1196-1209, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
formal verification, Binary decision diagram, minimization, linear transformation |
20 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
An improved branch and bound algorithm for exact BDD minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12), pp. 1657-1663, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combination of Lower Bounds in Exact BDD Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10758-10763, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | K. Rustan M. Leino |
A SAT Characterization of Boolean-Program Correctness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 10th International SPIN Workshop. Portland, OR, USA, May 9-10, 2003, Proceedings, pp. 104-120, 2003, Springer, 3-540-40117-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | John V. Franco, Michal Kouril, John S. Schlipf, Jeffrey Ward, Sean A. Weaver, Michael R. Dransfield, W. Mark Vanfleet |
SBSAT: a State-Based, BDD-Based Satisfiability Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 6th International Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 Selected Revised Papers, pp. 398-410, 2003, Springer, 3-540-20851-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Guoqiang Wang, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli |
Structural Detection of Symmetries in Boolean Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 498-503, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Dirk Beyer 0001, Andreas Noack |
Can Decision Diagrams Overcome State Space Explosion in Real-Time Verification? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2003, 23rd IFIP WG 6.1 International Conference, Berlin, Germany, September 29 - October 2, 2003, Proceedings, pp. 193-208, 2003, Springer, 3-540-20175-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Albert Nymeyer, Kairong Qian |
Heuristic Search Algorithms Based on Symbolic Data Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Conference on Artificial Intelligence ![In: AI 2003: Advances in Artificial Intelligence, 16th Australian Conference on Artificial Intelligence, Perth, Australia, December 3-5, 2003, Proceedings, pp. 966-979, 2003, Springer, 3-540-20646-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
shortest path, Heuristic search, binary decision diagrams |
20 | Jun Yuan 0007, Ken Albin, Adnan Aziz, Carl Pixley |
Simplifying Boolean constraint solving for random simulation-vector generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 123-127, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley |
Simplifying Circuits for Formal Verification Using Parametric Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 52-69, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Sava Krstic, John Matthews |
Verifying BDD Algorithms through Monadic Interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VMCAI ![In: Verification, Model Checking, and Abstract Interpretation, Third International Workshop, VMCAI 2002, Venice, Italy, January 21-22, 2002, Revised Papers, pp. 182-195, 2002, Springer, 3-540-43631-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Marta Z. Kwiatkowska, Gethin Norman, David Parker 0001 |
PRISM: Probabilistic Symbolic Model Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Performance Evaluation / TOOLS ![In: Computer Performance Evaluation, Modelling Techniques and Tools 12th International Conference, TOOLS 2002, London, UK, April 14-17, 2002, Proceedings, pp. 200-204, 2002, Springer, 3-540-43539-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Tuba Yavuz-Kahveci, Tevfik Bultan |
Heuristics for Efficient Manipulation of Composite Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FroCoS ![In: Frontiers of Combining Systems, 4th International Workshop, FroCoS 2002, Santa Margherita Ligure, Italy, April 8-10, 2002, Proceedings, pp. 57-71, 2002, Springer, 3-540-43381-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Randal E. Bryant, Yirng-An Chen |
Verification of arithmetic circuits using binary moment diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 137-155, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Formal verification, Computer arithmetic, Decision diagrams |
20 | Per Bjesse, Tim Leonard, Abdel Mokkedem |
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings, pp. 454-464, 2001, Springer, 3-540-42345-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Automatic Vector Generation Using Constraints and Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 107-120, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constraint, probability, partitioning, BDD, biasing, vector generation |
20 | Christoph Scholl 0001, Bernd Becker 0001 |
On the Generation of Multiplexer Circuits for Pass Transistor Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 372-378, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Parosh Aziz Abdulla, Per Bjesse, Niklas Eén |
Symbolic Reachability Analysis Based on SAT-Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for Construction and Analysis of Systems, 6th International Conference, TACAS 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 411-425, 2000, Springer, 3-540-67282-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Wolfgang Günther 0001, Rolf Drechsler |
ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1130-1137, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Chris Wilson, David L. Dill, Randal E. Bryant |
Symbolic Simulation with Approximate Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 470-485, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Yuan Lu 0004, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita |
Efficient variable ordering using aBDD based sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 687-692, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Gianpiero Cabodi, Stefano Quer, Fabio Somenzi |
Optimizing sequential verification by retiming transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 601-606, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Nils Klarlund |
A Theory of Restrictions for Logics and Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings, pp. 406-417, 1999, Springer, 3-540-66202-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Xinyu Zang, Hairong Sun, Kishor S. Trivedi |
Dependability Analysis of Distributed Computer Systems with Imperfect Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 330-337, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Enric Pastor, Jordi Cortadella, Marco A. Peña |
Structural Methods to Improve the Symbolic Analysis of Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICATPN ![In: Application and Theory of Petri Nets 1999, 20th International Conference, ICATPN '99, Williamsburg, Virginia, USA, June 21-25, 1999, Proceedings, pp. 26-45, 1999, Springer, 3-540-66132-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Armin Biere, Edmund M. Clarke, Yunshan Zhu |
Multiple State and Single State Tableaux for Combining Local and Global Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Correct System Design ![In: Correct System Design, Recent Insight and Advances, (to Hans Langmaack on the occasion of his retirement from his professorship at the University of Kiel), pp. 163-179, 1999, Springer, 3-540-66624-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Kavita Ravi, Fabio Somenzi |
Hints to accelerate Symbolic Traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 250-264, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Masahito Kurihara, Hisashi Kondo |
Heuristics and Experiments on BDD Representation of Boolean Functions for Expert Systems in Software Verification Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Joint Conference on Artificial Intelligence ![In: Advanced Topics in Artificial Intelligence, 12th Australian Joint Conference on Artificial Intelligence, AI '99, Sydney, Australia, December 6-10, 1999, Proceedings, pp. 353-364, 1999, Springer, 3-540-66822-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Gianpiero Cabodi, Paolo Camurati, Stefano Quer |
Auxiliary variables for BDD-based representation and manipulation of Boolean functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(3), pp. 309-340, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
finite state machines, binary decision diagrams, reachability analysis, functional decompositions |
20 | Jayram S. Thathachar |
On the Limitations of Ordered Representations of Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 10th International Conference, CAV '98, Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings, pp. 232-243, 1998, Springer, 3-540-64608-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
20 | Krzysztof Bilinski, Erik L. Dagless |
Efficient Approach to Symbolic State Exploration of Complex Parallel Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 132-142, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|