Search results for "CML"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo	Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
22	Gilbert Matig-a, Mehmet R. Yuce, Jean-Michel Redoute	Design of a CML Transceiver With Self-Immunity to EMI in 0.18-µm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
22	Hua Chen, Guiliang Guo, Qiangtao Lai, Yulin Zhang, Jingyu Han, Yuepeng Yan	0.3-4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
22	Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka	25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.	ISCAS	2017	DBLP DOI BibTeX RDF
22	Xing-Yuan Wang 0001, Hui-li Zhang, Xue-Mei Bao	Color image encryption scheme using CML and DNA sequence operations.	Biosyst.	2016	DBLP DOI BibTeX RDF
22	Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park	A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
22	Ikchan Jang, Yoonmyung Lee, SoYoung Kim, Jintae Kim	Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
22	Muhammad Waqas Chaudhary, Andy Heinig	Co-design of CML IO and Interposer channel for low area and power signaling.	DDECS	2016	DBLP DOI BibTeX RDF
22	Yong Fu, Zhiping Wen 0001, Lei Chen 0010	A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology.	ICCIP	2016	DBLP BibTeX RDF
22	Andrei Halanay, Doina Cândea, Ileana Rodica Radulescu	Stability analysis of equilibria in a delay differentialequations model of CML including asymmetric division and treatment.	Math. Comput. Simul.	2015	DBLP DOI BibTeX RDF
22	Diego A. Hollmann, Maximiliano Cristiá, Claudia S. Frydman	CML-DEVS: A specification language for DEVS conceptual models.	Simul. Model. Pract. Theory	2015	DBLP DOI BibTeX RDF
22	Alexandre Mota 0001, Adalberto Farias, Jim Woodcock 0001, Peter Gorm Larsen	Model checking CML: tool development and industrial applications.	Formal Aspects Comput.	2015	DBLP DOI BibTeX RDF
22	Jun Luo, Lei Zhang 0033, Li Zhang 0046, Yan Wang 0023, Zhiping Yu	Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
22	Debesh Bhatta, Suvadeep Banerjee, Abhijit Chatterjee	A Noise Aware CML Latch Modelling for Large System Simulation.	VLSID	2015	DBLP DOI BibTeX RDF
22		Concurrent Mapping and Localization (CML).	Computer Vision, A Reference Guide	2014	DBLP DOI BibTeX RDF
22	Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang	A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
22	Oliver Schrape, Markus Appel, Frank Winkler 0001, Milos Krstic	Low-power design methodology for CML and ECL circuits.	PATMOS	2014	DBLP DOI BibTeX RDF
22	Jim Woodcock 0001, Ana Cavalcanti 0001, John S. Fitzgerald, Simon Foster 0001, Peter Gorm Larsen	Contracts in CML.	ISoLA (2)	2014	DBLP DOI BibTeX RDF
22	Jim Woodcock 0001	Engineering UToPiA - Formal Semantics for CML.	FM	2014	DBLP DOI BibTeX RDF
22	Ashok Jaiswal, Dominik walk, Yuan Fang, Klaus Hofmann	Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes.	SoCC	2014	DBLP DOI BibTeX RDF
22	Hemanth Naick B., Om Prakash Sharma, Muthuvel Suresh Kumar, Baskaran Rajasekaran	Identification of Potent Inhibitors for Resistant Form of Chronic Myelogenous Leukaemia (CML).	IWBBIO	2014	DBLP BibTeX RDF
22	Xiaoyan Gui, Michael M. Green	Design of CML Ring Oscillators With Low Supply Sensitivity.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
22	Abhimanyu Kapoor, Yan Hu, Rizwan Bashirullah	A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
22	Yun-Hwan Jung, Yong Sin Kim, Yohan Hong, Ju Eon Kim, Kwang-Hyun Baek	Low-power pipelined phase accumulator using CMOS-CML hybrid F/Fs for pre-skewing operation.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
22	Ma Dolores Sotelo Herrera, Jesús San Martín, Lucía Cerrada	Saddle-Node bifurcation Cascades and associated Traveling Waves in Weakly Coupling CML.	Int. J. Bifurc. Chaos	2012	DBLP DOI BibTeX RDF
22	Weerapong Phadungsukanan, Markus Kraft, Joe Townsend, Peter Murray-Rust	The semantics of Chemical Markup Language (CML) for computational chemistry: CompChem.	J. Cheminformatics	2012	DBLP DOI BibTeX RDF
22	Minjae Lee	A 20GHz variability-aware robust, high-speed and low-power MOS CML latch.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
22	Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura	Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control.	MWSCAS	2012	DBLP DOI BibTeX RDF
22	Jim Woodcock 0001, Ana Cavalcanti 0001, John S. Fitzgerald, Peter Gorm Larsen, Alvaro Miyazawa, Simon Perry	Features of CML: A formal modelling language for Systems of Systems.	SoSE	2012	DBLP DOI BibTeX RDF
22		CML.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
22	Bedr'Eddine Ainseba, Chahrazed Benosman	CML dynamics: Optimal control of age-structured stem cell population.	Math. Comput. Simul.	2011	DBLP DOI BibTeX RDF
22	Peter Murray-Rust, Henry S. Rzepa	CML: Evolution and design.	J. Cheminformatics	2011	DBLP DOI BibTeX RDF
22	Joe Townsend, Peter Murray-Rust	CMLLite: a design philosophy for CML.	J. Cheminformatics	2011	DBLP DOI BibTeX RDF
22	Peter Murray-Rust, Joe Townsend, Sam E. Adams, Weerapong Phadungsukanan, Jens Thomas	The semantics of Chemical Markup Language (CML): dictionaries and conventions.	J. Cheminformatics	2011	DBLP DOI BibTeX RDF
22	Chunyuan Zhou, Lei Zhang 0033, Li Zhang 0046, Yan Wang 0023, Zhiping Yu, He Qian	Injection-Locking-Based Power and Speed Optimization of CML Dividers.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
22	Andreas Axholt, Henrik Sjöland	A 2.25mW inductor-less 24 GHz CML frequency divider in 90nm CMOS.	ECCTD	2011	DBLP DOI BibTeX RDF
22	Hongrui Wang, Dajie Zeng, Dongxu Yang, Li Zhang 0046, Lei Zhang 0033, Yan Wang 0023, He Qian, Zhiping Yu	Understanding dynamic behavior of mm-wave CML divider with injection-locking concept.	ISCAS	2011	DBLP DOI BibTeX RDF
22	A. Perumal, T. K. Bhattacharyya	Design of 1 V CMOS VCO followed by proposed source degeneration based CML flip-flops for 2.4 GHz short range wireless applications.	ICWET	2011	DBLP DOI BibTeX RDF
22	Ivan Zelinka	Evolutionary Control of CML Systems.	Evolutionary Algorithms and Chaotic Systems	2010	DBLP DOI BibTeX RDF
22	Wanchang Jiang, Cong Huo	CML model based max-subset shedding for sensor streams multi-joins under limited resources.	FSKD	2010	DBLP DOI BibTeX RDF
22	Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu	A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
22	Elisa Russo	Multimedia Representation of Music Pieces Encoded in Symbolic Format: an Approach Based on Csound, MPEG-4, SuperCollider, CML, Chuck, IEEE 1599.	J. Multim.	2009	DBLP DOI BibTeX RDF
22	Anthony Chan Carusone, Horace Cheng, Faisal A. Musa	A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
22	Shohdy Abdelkader, M. Omar, Mohamed Dessouky	1-V, High Speed, Low Leakage CMOS CML Multiplexer.	ISCAS	2009	DBLP DOI BibTeX RDF
22	Utku Seckin, Chih-Kong Ken Yang	A Comprehensive Delay Model for CMOS CML Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
22	Chih-Hsing Lin, Ching-Te Chiu	A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias.	ICECS	2008	DBLP DOI BibTeX RDF
22	KyungHoon Kim, SangSic Yoon, KiChang Kwean, DaeHan Kwon, SunSuk Yang, MunPhil Park, YongKi Kim, ByongTae Chung	A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network.	ESSCIRC	2008	DBLP DOI BibTeX RDF
22	Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart	Wideband mmWave CML static divider in 65nm SOI CMOS technology.	CICC	2008	DBLP DOI BibTeX RDF
22	Daeik D. Kim, Jonghae Kim, Choongyeun Cho	A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS.	ISSCC	2008	DBLP DOI BibTeX RDF
22	Antonio Punzo	Considerations on the Impact of Ill-Conditioned Configurations in the CML Approach.	GfKl	2008	DBLP DOI BibTeX RDF
22	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
22	Ju Young Jeong	Systematic design method for low power, high speed LTPS TFT based CML inverter/buffer.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
22	Soumya Chandramouli, Franklin Bien, Hyoungsoo Kim, Edward Gebara, Joy Laskar	A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS.	ESSCIRC	2007	DBLP DOI BibTeX RDF
22	Deyi Pi, Byung-Kwan Chun, Payam Heydari	A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers.	CICC	2007	DBLP DOI BibTeX RDF
22	Daihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik D. Kim, Robert Trzcinski, Duane S. Boning	Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS.	ISSCC	2007	DBLP DOI BibTeX RDF
22	Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu	Design of ultra low power CML MUXs and latches with forward body bias.	SoCC	2007	DBLP DOI BibTeX RDF
22	Massimo Alioto, Gaetano Palumbo	Design strategies of cascaded CML gates.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
22	Jean-Olivier Plouchart, Jonghae Kim, Victor Karam, Robert Trzcinski, Jeff Gross	Performance Variations of a 66GHz Static CML Divider in 90nm CMOS.	ISSCC	2006	DBLP DOI BibTeX RDF
22	Ullas Singh, Michael M. Green	High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
22	Massimo Alioto, Gaetano Palumbo	Modelling and design considerations on CML gates under high-current effects.	Int. J. Circuit Theory Appl.	2005	DBLP DOI BibTeX RDF
22	Ryoichi Mizuno, Yoshinori Dobashi, Tomoyuki Nishita	Modeling of Volcanic Clouds using CML.	J. Inf. Sci. Eng.	2004	DBLP BibTeX RDF
22	Fabricio Chalub, Christiano Braga	A Modular Rewriting Semantics for CML.	J. Univers. Comput. Sci.	2004	DBLP DOI BibTeX RDF
22	Yasmine Arafa, Kaveh Richard Kamyab Tehrani, Ebrahim Mamdani	Toward a Unified Scripting Language: Lessons Learned from Developing CML and AML.	Life-like characters	2004	DBLP BibTeX RDF
22	Massimo Alioto, Rosario Mita, Gaetano Palumbo	Performance evaluation of the low-voltage CML D-latch topology.	Integr.	2003	DBLP DOI BibTeX RDF
22	Peter Murray-Rust, Henry S. Rzepa	Chemical Markup, XML, and the World Wide Web. 4. CML Schema.	J. Chem. Inf. Comput. Sci.	2003	DBLP DOI BibTeX RDF
22	Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Mohamed Talbi, Asit Ray, Lawrence F. Wagner	A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology.	ESSCIRC	2003	DBLP DOI BibTeX RDF
22	Takuya Imai, Keiji Konishi, Hideki Kokame, Kentaro Hirata	Experimental Evidence for Spatiotemporal Stability and Control of a One-Way Open CML.	Int. J. Bifurc. Chaos	2002	DBLP DOI BibTeX RDF
22	John Brecht, Mark Chung, Roy Pea	CML: the ClassSync modeling language.	CSCL	2002	DBLP BibTeX RDF
22	Massimo Alioto, Rosario Mita, Gaetano Palumbo	Analysis and comparison of low-voltage CML D-latch.	ICECS	2002	DBLP DOI BibTeX RDF
22	William Ferreira 0001, Matthew Hennessy	A Behavioural Theory of First-Order CML.	Theor. Comput. Sci.	1999	DBLP DOI BibTeX RDF
22	William Ferreira 0001, Matthew Hennessy, Alan Jeffrey	A Theory of Weak Bisimulation for Core CML.	J. Funct. Program.	1998	DBLP DOI BibTeX RDF
22	Vikram Devdas, André Ivanov	Non-Intrusive Testing of High-Speed CML Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
22	Massimo Alioto, Gaetano Palumbo	Design of CML gate with the best propagation delay.	ICECS	1998	DBLP DOI BibTeX RDF
22	Mourad Debbabi	A Model-Based Concurrent Specification Language Over CML: Semantic Foundations.	Parallel Process. Lett.	1997	DBLP DOI BibTeX RDF
22	Hans Rischel, Hongyan Sun	Design and prototyping of real-time systems using CSP and CML.	RTS	1997	DBLP DOI BibTeX RDF
22	Kirsten Lackner Solberg Gasser, Flemming Nielson, Hanne Riis Nielson	Systematic Realisation of Control Flow Analyses for CML.	ICFP	1997	DBLP DOI BibTeX RDF	ML, Concurrent C
22	Khaled M. Sharaf, Mohamed I. Elmasry	Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
22	Flemming Nielson, Hanne Riis Nielson	From CML to its Process Algebra.	Theor. Comput. Sci.	1996	DBLP DOI BibTeX RDF
22	Mourad Debbabi	A Concurrent, Specification Language over CML.	PDPTA	1995	DBLP BibTeX RDF
22	Khaled M. Sharaf, Mohamed I. Elmasry	An accurate analytical propagation delay model for high-speed CML bipolar circuits.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
22	A. Kazeminejad, Keivan Navi, Daniel Etiemble	CML Current Mode Full Adders for 2.5-V Power Supply.	ISMVL	1994	DBLP DOI BibTeX RDF
22	Guus Schreiber, Bob J. Wielinga, Hans Akkermans, Walter Van de Velde, Anjo Anjewierden	CML: The CommonKADS Conceptual Modelling Language.	EKAW	1994	DBLP DOI BibTeX RDF
22	Khaled M. Sharaf, Mohamed I. Elmasry	Low-power differential CML and ECL BiCMOS circuit techniques.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
22	David Ben-Arieh	Concurrent modeling language (CML) for discrete process modeling, simulation and control.	J. Intell. Manuf.	1992	DBLP DOI BibTeX RDF
22	Hamdy S. Soliman, John B. Johnston	Dynamic Genericity in Imperative Languages: Example in CML.	ICCI	1992	DBLP BibTeX RDF
22	John H. Reppy	CML: A Higher-Order Concurrent Language.	PLDI	1991	DBLP DOI BibTeX RDF	ML
22	David A. Bourne	CML: A Meta-Interpreter for Manufacturing.	AI Mag.	1986	DBLP BibTeX RDF
22	Ian Sommerville	Software For Engineering Problems edited by R.A. Adey, CML Publications, Southampton, U.K., 1983, 150 pp. (£15.00).	Robotica	1983	DBLP DOI BibTeX RDF
14	Zeng-Wei Hong, Kai-Yi Chin, Jim-Min Lin	Developing embodied agent-based user interface by using interactive drama markup language.	ICUIMC	2009	DBLP DOI BibTeX RDF	ECA-based user interface, branching narrations, embodied conversational agent, interactive drama, markup language
14	Jianhua Zhao, Philip L. H. Yu, Qibao Jiang	ML estimation for factor analysis: EM or non-EM?	Stat. Comput.	2008	DBLP DOI BibTeX RDF	Maximum likelihood estimation, Factor analysis, EM, CM, ECME
14	Stephan Henzler, Siegmar Koeppe	Design and Application of Power Optimized High-Speed CMOS Frequency Dividers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Lan Zhang 0007, Ying-Chang Liang, Yan Xin 0001	Joint Beamforming and Power Allocation for Multiple Access Channels in Cognitive Radio Networks.	IEEE J. Sel. Areas Commun.	2008	DBLP DOI BibTeX RDF
14	Yen-Sung Michael Lee, Shahriar Mirabbasi	Design of an active-inductor-based termination circuit for high-speed I/O.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Matthew Fluet, Mike Rainey, John H. Reppy, Adam Shaw, Yingqi Xiao	Manticore: a heterogeneous parallel language.	DAMP	2007	DBLP DOI BibTeX RDF
14	Guo-Jun Qi, Xian-Sheng Hua 0001, Yong Rui, Jinhui Tang 0001, Tao Mei 0001, Hong-Jiang Zhang	Correlative multi-label video annotation.	ACM Multimedia	2007	DBLP DOI BibTeX RDF	concept correlation, video annotation, multi-labeling
14	Myilone Anandarajah, Ricky Robinson, Jadwiga Indulska	Hoarding Context Information with Context Clusters.	PerCom Workshops	2007	DBLP DOI BibTeX RDF
14	Matthew Fluet, Nic Ford, Mike Rainey, John H. Reppy, Adam Shaw, Yingqi Xiao	Status report: the manticore project.	ML	2007	DBLP DOI BibTeX RDF	ML, concurrent languages, data-parallel languages
14	Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio	A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Boo-Young Choi, Jung-Won Han, Sung Min Park 0001, Kang-Yeob Park, Wonseok Oh 0003, J.-C. Choi	A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Ling Yuan, Weining Ni, Yin Shi, Foster F. Dai	A 10-bit 2GHz Current-Steering CMOS D/A Converter.	ISCAS	2007	DBLP DOI BibTeX RDF