Search results for "DLL"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera	A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias.	APCCAS	2020	DBLP DOI BibTeX RDF
19	Le An, Marco Castelluccio, Foutse Khomh	An empirical study of DLL injection bugs in the Firefox ecosystem.	Empir. Softw. Eng.	2019	DBLP DOI BibTeX RDF
19	Sabir Ali Mondal, Pradip Mandal, Hafizur Rahaman 0001	Fast locking, startup-circuit free, low area, 32-phase analog DLL.	Integr.	2019	DBLP DOI BibTeX RDF
19	Khaled Rouabah, Salim Atia, Mustapha Flissi, Mohamed Salim Bouhlel, Salah Eddine Mezaache	Efficient technique for DLL S-curve side zero-crossings cancellation in global positioning system/Galileo receiver.	IET Signal Process.	2019	DBLP DOI BibTeX RDF
19	Ahmed Elian, Ibrahim M. Elfadel, Ayman Shabra	A Reconfigurable DLL-Based Digital-to-Time Converter Using Charge Pump Current Interpolation and Digital Predistortion Linearization.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
19	Jinseop Noh, Dong-Woo Jee	A DLL based clock multiplier using rotational DCDL and PRNG for spur reduction.	IEICE Electron. Express	2019	DBLP DOI BibTeX RDF
19	Dusan Obradovic, Milos Cabrilo, Ivan Milosavljevic, Dusan Krcum, Veljko Mihajlovic	A 250 - 800-MHz Multiplying DLL for Reference Frequency Generation with Improved Phase Noise.	EUROCON	2019	DBLP DOI BibTeX RDF
19	Wei Chu, Shi-Yu Huang	A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling.	NEWCAS	2019	DBLP DOI BibTeX RDF
19	Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh	A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.	ISSCC	2019	DBLP DOI BibTeX RDF
19	Nico Angeli, Oliver Bachmann, Klaus Hofmann	A 2.5 GHz All-Digital Multiphase DLL and Phase Shifter in 65 nm CMOS using a Scalable Phase-to-Digital Converter.	ISCAS	2019	DBLP DOI BibTeX RDF
19	Stephanie Dick, Daniel Volmar	Dll hell: software dependencies, failure, and the maintenance of microsoft windows.	IEEE Ann. Hist. Comput.	2018	DBLP DOI BibTeX RDF
19	Yang Chen, Wenyuan Li	Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
19	Jin Wu, Youzhi Zhang 0003, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun	Low-jitter DLL applied for two-segment TDC.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
19	Baptiste Wicht, Jean Hennebert, Andreas Fischer 0002	DLL: A Blazing Fast Deep Neural Network Library.	CoRR	2018	DBLP BibTeX RDF
19	Zhiqiang Huang, Bingwei Jiang, Howard C. Luong	A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
19	Jongsun Kim, Sangwoo Han	A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
19	Hee-am Shin, Young-Jae Min	A unified DLL-controlled active rectifier in 6.78 MHz resonant-coupling wireless power receivers for space-limited portable and wearable applications.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
19	Baptiste Wicht, Andreas Fischer 0002, Jean Hennebert	DLL: A Fast Deep Neural Network Library.	ANNPR	2018	DBLP DOI BibTeX RDF
19	Dongjun Park, Jongsun Kim	A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs.	ISCAS	2018	DBLP DOI BibTeX RDF
19	Zhe Liu 0038, Liheng Lou, Zhongyuan Fang, Kai Tang 0002, Ting Guo, Yuanjin Zheng	A DLL-based Configurable Multi-Phase Clock Generator for True-Time-Delay Wideband FMCW Phased-Array in 40nm CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
19	Yu-Chi Wei, Shi-Yu Huang	A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL.	ISOCC	2018	DBLP DOI BibTeX RDF
19	Matan Gal-Katziri, Ali Hajimiri	A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization.	A-SSCC	2018	DBLP DOI BibTeX RDF
19	Ching-Che Chung, Chien-Ying Yu	An area-efficient and wide-range digital DLL for per-pin deskew applications.	Turkish J. Electr. Eng. Comput. Sci.	2017	DBLP DOI BibTeX RDF
19	Sangjin Byun	Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
19	Yang Chen, Wenyuan Li, Zhigong Wang	A 40-Gb/s 3-tap forward feedback equalizer with DLL-based delay time calibration.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
19	Junsub Yoon, Seo Weon Heo, Jongsun Kim	A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
19	Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou	DLL-Assisted Clock Synchronization Method for Multi-Die ICs.	ICCD	2017	DBLP DOI BibTeX RDF
19	Shijia Zhu, Yu Wang, Fan Ye, Jun Xu	A clock interpolation structure using DLL for clock distribution in ADC.	ASICON	2017	DBLP DOI BibTeX RDF
19	Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen	A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
19	Mina Kim, Seojin Choi, Taeho Seong, Jaehyouk Choi	A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
19	Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin Hyuk Kim, Seong-Ook Jung	High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
19	Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung	All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
19	Shao-Ku Kao, Yi-Hsien Hsieh, Hsiang-Chi Cheng	An all-digital DLL with duty-cycle correction using reusable TDC.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
19	J. A. Guinea	Bang-bang cycle-slip detector improves jitter-tolerance in SONET PLL/DLL CDR.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
19	Yan Li, Cao Zhen, Shaohua Liu, Lai Jiang, Hang Yu	A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT.	Mob. Networks Appl.	2016	DBLP DOI BibTeX RDF
19	Xiongwei Xie, Weichao Wang	Lightweight Examination of DLL Environments in Virtual Machines to Detect Malware.	SCC@AsiaCCS	2016	DBLP DOI BibTeX RDF
19	Luís Duarte, Luís Rodrigues, Luis Nero Alves, Carlos Ribeiro, Monica Figueiredo	DLL architecture for OFDM based VLC transceivers in FPGA.	CSNDSP	2016	DBLP DOI BibTeX RDF
19	Erkan Bayram, Oner Hanay, Renato Negra	A 4.5 mW, 0.01148 mm2 frequency multiplier based on DLL with output frequency from 4 to 6 GHz.	NORCAS	2016	DBLP DOI BibTeX RDF
19	Yann Deval, Francois Rivet	A balanced logic routing block for Factorial-DLL based Frequency Generation.	SBCCI	2016	DBLP DOI BibTeX RDF
19	Zhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong	2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL.	ISSCC	2016	DBLP DOI BibTeX RDF
19	Chen Li 0015, Sheng Ma, Lu Wang 0019, Zicong Wang, Xia Zhao 0004, Yang Guo 0003	DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.	ICCD	2016	DBLP DOI BibTeX RDF
19	Benyuanyi Liu, Wengao Lu, Dahe Liu, Shanzhe Yu, Yacong Zhang, Zhongjian Chen	A novel low-power readout structure with 1/2 sub-scan time-delay-integration and DLL-based A/D for 1024×6 infrared focal plane array.	ISCAS	2016	DBLP DOI BibTeX RDF
19	Jongsun Kim, Bongho Bae	A fast-locking clock multiplying DLL.	ISOCC	2016	DBLP DOI BibTeX RDF
19	Dandan Zhang, Hai-Gang Yang, Wen-rui Zhu, Wei Li, Zhihong Huang, Lin Li, Tianyi Li 0007	A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
19	Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu	A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
19	Sarang Kazeminia, Sobhan Sofimowloodi, Khayrollah Hadidi	A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
19	Sihem Zitouni, Djamel Chikouche, Khaled Rouabah, Karim Mokrani	Analytical Models of Correlation Functions, DLL Discriminator Outputs and Multipath Envelope Errors for CosBOC(m, n) Modulated Signals in Coherent and Non-coherent Configurations.	Wirel. Pers. Commun.	2015	DBLP DOI BibTeX RDF
19	Shao-Ku Kao, Jen-Hou Wu, Hsiang-Chi Cheng	All-digital controlled boost DC-DC converter with all-digital DLL-based calibration.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
19	Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi	A digitally assisted 20MHz-600MHz 16-phase DLL enhanced with dynamic gain control loop.	ECCTD	2015	DBLP DOI BibTeX RDF
19	Joan Mauricio, Francesc Moll	Local variations compensation with DLL-based Body Bias Generator for UTBB FD-SOI technology.	NEWCAS	2015	DBLP DOI BibTeX RDF
19	Won-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok-Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung-Hwan Choi, Seong-Jin Jang, Joo-Sun Choi	17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.	ISSCC	2015	DBLP DOI BibTeX RDF
19	Mina Kim, Seojin Choi, Jaehyouk Choi	A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells.	VLSIC	2015	DBLP DOI BibTeX RDF
19	Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen	A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique.	ISCAS	2015	DBLP DOI BibTeX RDF
19	Yuequan Liu, Yuan Wang 0001, Song Jia, Xing Zhang 0002	180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance.	ISCAS	2015	DBLP DOI BibTeX RDF
19	Vladimir Mashkovtsev, Ali Attaran, Rashid Rashidzadeh	DLL based test solution for interposers in 2.5-D ICs.	ISCAS	2015	DBLP DOI BibTeX RDF
19	Haizheng Guo, Tadeusz Kwasniewski	A DLL fractional M/N frequency synthesizer.	CCECE	2015	DBLP DOI BibTeX RDF
19	Haizheng Guo, Tadeusz Kwasniewski	A DLL-based period synthesis.	CCECE	2015	DBLP DOI BibTeX RDF
19	Rashid Rashidzadeh, Esrafil Jedari, Tareq Muhammad Supon, Vladimir Mashkovtsev	A DLL-based test solution for through silicon via (TSV) in 3D-stacked ICs.	ITC	2015	DBLP DOI BibTeX RDF
19	Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim	A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.	A-SSCC	2015	DBLP DOI BibTeX RDF
19	Sung-Yong Kim, Xuefan Jin, Jung-Hoon Chun, Kee-Won Kwon	A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy.	A-SSCC	2015	DBLP DOI BibTeX RDF
19	Jacek Jasielski, Stanislaw W. Kuta, Wojciech Kolodziejski, Witold Machowski	Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL.	MIXDES	2015	DBLP DOI BibTeX RDF
19	Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe	A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
19	Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta	A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
19	Govind S. Patel, S. Sharma	Predicting the jitter of PLL-DLL Based frequency synthesizers.	Int. J. Wavelets Multiresolution Inf. Process.	2014	DBLP DOI BibTeX RDF
19	Yong-Hwan Moon, In-Seok Kong, Young-Soo Ryu, Jin-Ku Kang	A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
19	Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour	Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
19	Zong-Yi Chen, Chung-Chih Hung	DLL-based pulse-width modulation digital-to-analog converter for continuous-time sigma delta modulators.	MWSCAS	2014	DBLP DOI BibTeX RDF
19	Aytac Atac, Ralf Wunderlich, Stefan Heinen	A low power DLL based clock multiplier for multistandard wireless smart grid communication.	CSNDSP	2014	DBLP DOI BibTeX RDF
19	Yann Deval, P. O. Lucas de Peslouan, Thierry Taris, M. De Matos, Didier Belot	The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation.	NEWCAS	2014	DBLP DOI BibTeX RDF
19	Dong Hoon Baek, Byungsub Kim, Hong-June Park, Jae-Yoon Sim	2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface.	ISSCC	2014	DBLP DOI BibTeX RDF
19	Ji Won Hwang	Joint DLL and PHY layer design in wireless communications.		2014	RDF
19	Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim	A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
19	Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim	A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
19	Mohammad Gholami, Gholamreza Ardeshir	Analysis of DLL Jitter due to Voltage-Controlled Delay Line.	Circuits Syst. Signal Process.	2013	DBLP DOI BibTeX RDF
19	Mohammad Gholami	A Novel Low Power Architecture for DLL-Based Frequency Synthesizers.	Circuits Syst. Signal Process.	2013	DBLP DOI BibTeX RDF
19	Herman Jalli Ng, Alexander Fischer, Reinhard Feger, Rainer Stuhlberger, Linus Maurer, Andreas Stelzer	A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
19	Zhikuang Cai, Tailong Xu, Haiyan Sun, Longxing Shi	A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
19	Dandan Zhang, Haigang Yang, Zhujia Chen, Wei Li, Zhihong Huang, Lijiang Gao, Wen-rui Zhu	A fast-locking digital DLL with a high resolution time-to-digital converter.	CICC	2013	DBLP DOI BibTeX RDF
19	Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Won Lee, Seong-Ook Jung	All-digital 90° phase-shift DLL with a dithering jitter suppression scheme.	CICC	2013	DBLP DOI BibTeX RDF
19	San-Jeow Cheng, Yuan Gao 0011, Wei-Da Toh, Yuanjin Zheng, Minkyu Je, Chun-Huat Heng	A 110pJ/b multichannel FSK/GMSK/QPSK/p/4-DQPSK transmitter with phase-interpolated dual-injection DLL-based synthesizer employing hybrid FIR.	ISSCC	2013	DBLP DOI BibTeX RDF
19	Dong-Woo Jee, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim	A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms.	ISSCC	2013	DBLP DOI BibTeX RDF
19	Shuli Geng, Ni Xu, Jun Li 0024, Xueyi Yu, Woogeun Rhee, Zhihua Wang 0001	A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation.	ISCAS	2013	DBLP DOI BibTeX RDF
19	Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro	A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL.	ISCAS	2013	DBLP DOI BibTeX RDF
19	Siyu Yang, Deping Huang, Xiaoke Wen, Lei Chen, Jinghong Chen	A radiation-hardened DLL with fine resolution and DCC for DDR2 memory interface in 0.13 μm CMOS.	ISCAS	2013	DBLP DOI BibTeX RDF
19	Chorng-Sii Hwang, Ting-Li Chu, Po-Hsun Chen	DLL-based programmable clock multiplier using differential toggle-pulsed latch.	SoCC	2013	DBLP DOI BibTeX RDF
19	Yuwen Wang, Fan Ye 0001, Junyan Ren	A DLL based low-phase-noise clock multiplier with offset-tolerant PFD.	ASICON	2013	DBLP DOI BibTeX RDF
19	Haizheng Guo, Xinjie Wang, Tadeusz Kwasniewski	Spur analysis and reduction of edge combining DLL-based frequency multiplier.	CCECE	2013	DBLP DOI BibTeX RDF
19	Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic	A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
19	Yuqi Liu, Yihang Ran, Ting Ke, Xiulin Hu	Characterization of Code Tracking Error of Coherent DLL Under CW Interference.	Wirel. Pers. Commun.	2012	DBLP DOI BibTeX RDF
19	Al-Hussein A. El-Shafie, Serag El-Din Habib	An all-digital DLL using novel harmonic-free and multi-bit SAR techniques.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
19	Takashi Kawamoto, Kazuhiro Ueda, Takayuki Noto	480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications.	J. Electr. Comput. Eng.	2012	DBLP DOI BibTeX RDF
19	Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung	A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
19	Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung	Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
19	Yizhi Han, Woogeun Rhee, Zhihua Wang 0001	A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL.	MWSCAS	2012	DBLP DOI BibTeX RDF
19	Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour	A process variation tolerant DLL-based UWB frequency synthesizer.	MWSCAS	2012	DBLP DOI BibTeX RDF
19	Jonas Fritzin, Behzad Mesgarzadeh, Atila Alvandpour	A Class-D stage with harmonic suppression and DLL-based phase generation.	MWSCAS	2012	DBLP DOI BibTeX RDF
19	Monica Figueiredo, Rui L. Aguiar	Uncertainty in DLL deskewing schemes.	ICECS	2012	DBLP DOI BibTeX RDF
19	Jae-Wook Kwon, Xuefan Jin, Gyoo-Cheol Hwang, Jung-Hoon Chun, Kee-Won Kwon	A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface.	ESSCIRC	2012	DBLP DOI BibTeX RDF
19	Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen	A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
19	Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim	A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.	ISSCC	2012	DBLP DOI BibTeX RDF