Search results for "ESPRESSO"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang	An efficient combinationality check technique for the synthesis of cyclic combinational circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Seraj Ahmad, Rabi N. Mahapatra	M-trie: an efficient approach to on-chip logic minimization.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Anna Bernasconi 0001, Valentina Ciriani, Fabrizio Luccio, Linda Pagli	Three-level logic minimization based on function regularities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Petr Fiser, Jan Hlavicka, Hana Kubátová	FC-Min: A Fast Multi-Output Boolean Minimizer.	DSD	2003	DBLP DOI BibTeX RDF
17	Muthukumar Venkatesan, Henry Selvaraj	Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation.	VLSI Design	2003	DBLP DOI BibTeX RDF
17	Alan Mishchenko, Tsutomu Sasao	Large-scale SOP minimization using decomposition and functional properties.	DAC	2003	DBLP DOI BibTeX RDF	SOP minimization, disjoint-support decomposition, orthodox functions, BDDs, divide-and-conquer strategy
17	Roman L. Lysecky, Frank Vahid	On-chip logic minimization.	DAC	2003	DBLP DOI BibTeX RDF	on-chip logic minimization, on-chip synthesis, embedded systems, dynamic optimization, system-on-a-chip, logic minimization
17	Fan Mo, Robert K. Brayton	Whirlpool PLAs: a regular logic structure and their synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Sheri A. Mickelson, John A. Taylor, Mike Dvorak	Simplifying the Task of Generating Climate Simulations and Visualizations.	International Conference on Computational Science (2)	2002	DBLP DOI BibTeX RDF
17	Anna Bernasconi 0001, Valentina Ciriani, Fabrizio Luccio, Linda Pagli	Fast three-level logic minimization based on autosymmetry.	DAC	2002	DBLP DOI BibTeX RDF	autosymmetry, three-level logic, synthesis
17	Petr Fiser, Jan Hlavicka	On the Use of Mutations in Boolean Minimization.	DSD	2001	DBLP DOI BibTeX RDF
17	Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj	A variable partition approach for disjoint decomposition.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
17	Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Negative thinking in branch-and-bound: the case of unate covering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
17	Jyh-Mou Tseng, Jing-Yang Jou	Two-level logic minimization for low power.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	two-level logic minimization, low power design, logic synthesis, programmable logic array
17	Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Symbolic two-level minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Yibin Ye, Kaushik Roy 0001	A Graph-Based Synthesis Algorithm for AND/XOR Networks.	DAC	1997	DBLP DOI BibTeX RDF
17	Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof	Local ratio cut and set covering partitioning for huge logic emulation systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
17	Steven M. Nowick, David L. Dill	Exact two-level minimization of hazard-free logic with multiple-input changes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
17	R. Iris Bahar, Fabio Somenzi	Boolean techniques for low power driven re-synthesis.	ICCAD	1995	DBLP DOI BibTeX RDF
17	B. Gurunath, Nripendra N. Biswas	An algorithm for multiple output minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
17	Alan J. Coppola	New Methods in the Analysis of Logic Minimization Data and Algorithms.	DAC	1989	DBLP DOI BibTeX RDF
17	Chin-Long Wey, Tsin-Yuan Chang	PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.	DAC	1988	DBLP BibTeX RDF
17	L. B. Nguyen, M. A. Perkowdki, N. B. Goldstein	PALMINI - Fast Boolean Minimizer for Personal Computers.	DAC	1987	DBLP DOI BibTeX RDF
17	Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin	The McBOOLE logic minimizer.	DAC	1985	DBLP DOI BibTeX RDF