Search results for "HDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang 0016	VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.	ITNG	2006	DBLP DOI BibTeX RDF
20	Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson	An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets.	ASAP	2006	DBLP DOI BibTeX RDF
20	Donglin Li, Otmane Aït Mohamed	MDG-Based Verification of the Look-Aside Interface.	CCECE	2006	DBLP DOI BibTeX RDF
20	Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin	Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks.	CHES	2006	DBLP DOI BibTeX RDF
20	Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin	High-Level Synthesis for Self-Timed Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Moonvin Song, Yunmo Chung	SoC Design of Speaker Connection System by Efficient Cosimulation.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede	Extended abstract: a race-free hardware modeling language.	MEMOCODE	2005	DBLP DOI BibTeX RDF
20	Tun Li, Yang Guo 0003, GongJie Liu, Sikun Li	Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.	DSD	2005	DBLP DOI BibTeX RDF
20	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Qiu-Zhong Wu, Yi-He Sun	An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization.	ESTIMedia	2005	DBLP DOI BibTeX RDF
20	Mohammed Javed Absar, Pol Marchal, Francky Catthoor	Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation.	ESTIMedia	2005	DBLP DOI BibTeX RDF
20	Tejas M. Bhatt, Dennis McCain	Matlab as a development environment for FPGA design.	DAC	2005	DBLP DOI BibTeX RDF	system design flows, rapid prototyping
20	Tero Rissa, Adam Donlin, Wayne Luk	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
20	He Hu 0001, Da-you Liu, Xiaoyong Du 0001	Semi-automatic hardware design using ontologies.	ICARCV	2004	DBLP DOI BibTeX RDF
20	Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti 0001	An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments.	MICAI	2004	DBLP DOI BibTeX RDF
20	Daniel Kroening, Edmund M. Clarke	Checking consistency of C and Verilog using predicate abstraction and induction.	ICCAD	2004	DBLP DOI BibTeX RDF
20	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	bubble logic, simulation, views, hardware description languages, quantum algorithms, quantum circuits, entanglement
20	Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang 0006, Gong Ouyang, Rob Sharpe, John W. Rockway	Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.	ISQED	2004	DBLP DOI BibTeX RDF
20	Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu	Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits.	IWDC	2004	DBLP DOI BibTeX RDF
20	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
20	Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene	A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification.	DATE	2003	DBLP DOI BibTeX RDF
20	Li Shen 0002	RTL Concurrent Fault Simulation.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, high-level testing, circuit modeling
20	Jonathan Ballagh, James Hwang, H. Ma, Brent Milne, Nabeel Shirazi, Vinay Singh, Jeffrey D. Stroomer	Specifying Control Logic for DSP Applications in FPGA.	FPL	2003	DBLP DOI BibTeX RDF
20	Ryuichi Takahashi, Hajime Ohiwa	Situated Learning on FPGA for Superscalar Microprocessor Design Education.	SBCCI	2003	DBLP DOI BibTeX RDF
20	Amjad Gawanmeh, Sofiène Tahar, Kirsten Winter	Interfacing ASM with the MDG Tool.	Abstract State Machines	2003	DBLP DOI BibTeX RDF
20	Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro	Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
20	Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez	Accurate VHDL-based simulation of Sigma-Delta modulators.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
20	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program slicing for VHDL.	Int. J. Softw. Tools Technol. Transf.	2002	DBLP DOI BibTeX RDF	Model checking, Formal verification, VHDL, Program slicing, Hardware description languages
20	Christophe Paoli, Marie-Laure Nivet, Jean François Santucci, Antoine Campana	Path-Oriented Test Data Generation of Behavioral VHDL Description.	DELTA	2002	DBLP DOI BibTeX RDF	High level design validation, simulation-based validation, software testing techniques, constraint logic programming language, VHDL
20	Stefan Höreth	A word-level graph manipulation package.	Int. J. Softw. Tools Technol. Transf.	2001	DBLP DOI BibTeX RDF	Word-level, TUDD, BDD, Decision diagrams, BMD
20	Luis Entrena, Celia López, Emilio Olías	Automatic Insertion of Fault-Tolerant Structures at the RT Level.	IOLTW	2001	DBLP DOI BibTeX RDF
20	Yanbing Li, Miriam Leeser	HML, a novel hardware description language and its translation to VHDL.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
20	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
20	Ryuichi Takahashi, Noriyoshi Yoshida	Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1.	MSE	1999	DBLP DOI BibTeX RDF
20	Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul	Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test.	VTS	1999	DBLP DOI BibTeX RDF
20	Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung	Virtual Chip: Making Functional Models Work on Real Target Systems.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
20	Brian T. Graham	An Interpretation of NODEN in HOL.	TPHOLs	1994	DBLP DOI BibTeX RDF
20	Hiroto Yasuura, Nagisa Ishiura	Semantics of a Hardware Design Language for Japanese Standardization.	DAC	1989	DBLP DOI BibTeX RDF
20	Jean Christophe Madre, Jean-Paul Billon	Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour.	DAC	1988	DBLP BibTeX RDF
19	Deheng Yang, Jiayu He, Xiaoguang Mao, Tun Li, Yan Lei, Xin Yi, Jiang Wu	Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
19	Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu 0001	HDLdebugger: Streamlining HDL debugging with Large Language Models.	CoRR	2024	DBLP DOI BibTeX RDF
19	Madam Chakradar, Alok Aggarwal, Xiaochun Cheng, Anuj Rani, Manoj Kumar 0009, Achyut Shankar	A Non-invasive Approach to Identify Insulin Resistance with Triglycerides and HDL-c Ratio Using Machine learning.	Neural Process. Lett.	2023	DBLP DOI BibTeX RDF
19	Vishwanath Bijalwan, Vijay Bhaskar Semwal, Ghanapriya Singh, Tapan Kumar Mandal	HDL-PSR: Modelling Spatio-Temporal Features Using Hybrid Deep Learning Approach for Post-Stroke Rehabilitation.	Neural Process. Lett.	2023	DBLP DOI BibTeX RDF
19	Hooman Hematkhah, Yousef Seifi Kavian, Ehsan Namjoo	PoCH: automatic HDL code generator tool for Polar channel coding decoders in multimedia communication systems.	Multim. Tools Appl.	2023	DBLP DOI BibTeX RDF
19	Sharad B. Jadhav, N. K. Deshmukh, V. T. Humbe	HDL-PI: hybrid DeepLearning technique for person identification using multimodal finger print, iris and face biometric features.	Multim. Tools Appl.	2023	DBLP DOI BibTeX RDF
19	Aditya Rajagopal, Diederik Adriaan Vink, Jianyi Cheng, Yann Herklotz	GSA to HDL: Towards principled generation of dynamically scheduled circuits.	CoRR	2023	DBLP DOI BibTeX RDF
19	Frans Skarman, Oscar Gustafsson	Spade: An Expression-Based HDL With Pipelines.	CoRR	2023	DBLP DOI BibTeX RDF
19	Nicolo Vladi Biesuz, Rimsky Caballero, Davide Cieri, Nico Giangiacomi, Francesco Gonnella, Guillermo Loustau De Linares, Andrew Peck	Hog 2023.1: a collaborative management tool to handle Git-based HDL repository.	CoRR	2023	DBLP DOI BibTeX RDF
19	Anik Mallik, Sanjoy Kundu, Md. Ashikur Rahman	An FPGA-Based Semi-Automated Traffic Control System Using Verilog HDL.	CoRR	2023	DBLP DOI BibTeX RDF
19	Shailja Thakur, Jason Blocklove, Hammond Pearce, Benjamin Tan 0001, Siddharth Garg, Ramesh Karri	AutoChip: Automating HDL Generation Using LLM Feedback.	CoRR	2023	DBLP DOI BibTeX RDF
19	Xiaodan Xing, Javier Del Ser, Yinzhe Wu 0001, Yang Li 0010, Jun Xia, Lei Xu, David N. Firmin, Peter Gatehouse, Guang Yang 0006	HDL: Hybrid Deep Learning for the Synthesis of Myocardial Velocity Maps in Digital Twins for Cardiac Analysis.	IEEE J. Biomed. Health Informatics	2023	DBLP DOI BibTeX RDF
19	Davi A. Mendes, Gabriel Reves, M. A. Pastrana, Pedro H. L. S. P. Domingues, Helon V. H. Ayala, Alan Conci Kubrusly, Daniel M. Muñoz, Carlos H. Llanos	A Comparative Analysis of HDL and HLS for Accelerating Machine Learning based Strain Estimation with Ultrasonic Guided Waves.	SBESC	2023	DBLP DOI BibTeX RDF
19	Jianjun Xu, Jiayu He, Jingyan Zhang, Deheng Yang, Jiang Wu, Xiaoguang Mao	Validating the Redundancy Assumption for HDL from Code Clone's Perspective.	ISPD	2023	DBLP DOI BibTeX RDF
19	Frans Skarman, Lucas Klemmer, Oscar Gustafsson, Daniel Große	Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis.	FDL	2023	DBLP DOI BibTeX RDF
19	Lekshmi S. Ajay, Sreenidhi Prabha Rajeev	Comparative Analysis of Data Compression using Canonical Huffman and Golomb Rice Encoding in Verilog HDL and Implementation in FPGA.	ICCCNT	2023	DBLP DOI BibTeX RDF
19	Pawel Szczepankowski, Wojciech Sleszynski, Tomasz Bajdecki	A Direct Modulation for Matrix Converters Based on the One-Cycle Atomic Operation Developed in Verilog HDL.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
19	Carter Kelly, Benjamin Wilkinson, Amr H. Abd-Elrahman, Orlando Cordero, H. Andrew Lassiter	Accuracy Assessment of Low-Cost Lidar Scanners: An Analysis of the Velodyne HDL-32E and Livox Mid-40's Temporal Stability.	Remote. Sens.	2022	DBLP DOI BibTeX RDF
19	Onur Kilinççeker, Ercument Turk, Fevzi Belli, Moharram Challenger	Model-based ideal testing of hardware description language (HDL) programs.	Softw. Syst. Model.	2022	DBLP DOI BibTeX RDF
19	Bayley King, Rashmi Jha, Temesguen Kebede, David Kapp	Securing 3rd-Party HDL IP: a Feasibility Study Using Evolutionary Methods.	J. Hardw. Syst. Secur.	2022	DBLP DOI BibTeX RDF
19	Xiaodan Xing, Javier Del Ser, Yinzhe Wu 0001, Yang Li 0010, Jun Xia, Lei Xu, David N. Firmin, Peter Gatehouse, Guang Yang 0006	HDL: Hybrid Deep Learning for the Synthesis of Myocardial Velocity Maps in Digital Twins for Cardiac Analysis.	CoRR	2022	DBLP DOI BibTeX RDF
19	Charles Gouert, Nektarios Georgios Tsoutsos	Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
19	Manoj Srinivas Botla, Jai Bala Srujan Melam, Raja Stuthi Paul Pedapati, Srijanee Mookherji, Vanga Odelu, Rajendra Prasath	Comparative Study of HDL algorithms for Intrusion Detection System in Internet of Vehicles.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
19	Safi Ullah, Muazzam Ali Khan, Jawad Ahmad 0001, Sajjad Shaukat Jamal, Zil E. Huma, Muhammad Tahir Hassan, Nikolaos Pitropakis, Arshad, William J. Buchanan	HDL-IDS: A Hybrid Deep Learning Architecture for Intrusion Detection in the Internet of Vehicles.	Sensors	2022	DBLP DOI BibTeX RDF
19	Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan	Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs.	MEMOCODE	2022	DBLP DOI BibTeX RDF
19	K. N. Raja Praveen, Gadug Sudhamsu	Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers.	IC3I	2022	DBLP DOI BibTeX RDF
19	K. N. Raja Praveen, Gadug Sudhamsu	Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers.	IC3I	2022	DBLP DOI BibTeX RDF
19	Frans Skarman, Oscar Gustafsson	Spade: An HDL Inspired by Modern Software Languages.	FPL	2022	DBLP DOI BibTeX RDF
19	Hye-Hyun Lee, Yeon-Seob Song, Kang-Yoon Lee	Modeling of nano-scale PLL using Verilog HDL.	ICTC	2022	DBLP DOI BibTeX RDF
19	Jakob Wenzel 0002, Christian Hochberger	Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis.	RSP	2022	DBLP DOI BibTeX RDF
19	Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan	Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code.	RTAS	2022	DBLP DOI BibTeX RDF
19	Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuya Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue	An HDL Simulator with Direct Register Access for Improving Code Coverage.	AsiaJCIS	2022	DBLP DOI BibTeX RDF
19	Saman Fröhlich	A Fully Fledged HDL Design Flow for In-Memory Computing with Approximation Support		2022	RDF
19	Enrico Reggiani, Emanuele Del Sozzo, Davide Conficconi, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio	Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.	ACM Trans. Reconfigurable Technol. Syst.	2021	DBLP DOI BibTeX RDF
19	Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima	Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing.	Integr.	2021	DBLP DOI BibTeX RDF
19	Talal Bonny	Chaotic or Hyper-chaotic Oscillator? Numerical Solution, Circuit Design, MATLAB HDL-Coder Implementation, VHDL Code, Security Analysis, and FPGA Realization.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
19	Daniel Gutierrez-Galan, Juan Pedro Dominguez-Morales, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno	OpenNAS: Open Source Neuromorphic Auditory Sensor HDL code generator for FPGA implementations.	Neurocomputing	2021	DBLP DOI BibTeX RDF
19	Samed Al, Murat Dener	STL-HDL: A new hybrid network intrusion detection system for imbalanced dataset on big data environment.	Comput. Secur.	2021	DBLP DOI BibTeX RDF
19	Friedrich Bauer, Felix Braun, Daniel Hauer, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima Taherinejad, Philipp-Sebastian Vogt	MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGA.	FPL	2021	DBLP DOI BibTeX RDF
19	Seema Singh Saharan, Pankaj Nagar, Kate Townsend Creasy, Eveline O. Stock, James Feng, Mary J. Malloy, John P. Kane	Application of Machine Learning Ensemble Super Learner for analysis of the cytokines transported by high density lipoproteins (HDL) of smokers and nonsmokers.	CSCI	2021	DBLP DOI BibTeX RDF
19	Young-Hoon Kim, Hyungsik Ju, Ik-Jae Chun, Chan-Bok Jeong, Moon-Sik Lee	Design of Low-latency Synthesizable PUCCH Demodulation Unit Using Simulink HDL Coder.	ICTC	2021	DBLP DOI BibTeX RDF
19	Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su	Implement 32-bit RISC-V Architecture Processor using Verilog HDL.	ISPACS	2021	DBLP DOI BibTeX RDF
19	Ryan Kabrick, John D. Leidel, David Donofrio	Toward HDL Extensions for Rapid AI/ML Accelerator Generation.	HPEC	2021	DBLP DOI BibTeX RDF
19	Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi	Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester.	DTIS	2021	DBLP DOI BibTeX RDF
19	Michael Christensen 0001	Programming Language Techniques for Improving ISA and HDL Design.		2021	RDF
19	Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann	Verilog HDL and its ancestors and descendants.	Proc. ACM Program. Lang.	2020	DBLP DOI BibTeX RDF
19	Makoto Kato, Naoya Onizawa, Takahiro Hanyu	Design Automation of Invertible Logic Circuit from a Standard HDL Description.	FLAP	2020	DBLP BibTeX RDF
19	Roberto Millon, Emmanuel Frati, Enzo Rucci	A Comparative Study between HLS and HDL on SoC for Image Processing Applications.	CoRR	2020	DBLP BibTeX RDF
19	Junya Miura, Hiromu Miyazaki, Kenji Kise	A portable and Linux capable RISC-V computer system in Verilog HDL.	CoRR	2020	DBLP BibTeX RDF
19	Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001	Efficient Fault Injection based on Dynamic HDL Slicing Technique.	CoRR	2020	DBLP BibTeX RDF
19	Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001	Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing.	CoRR	2020	DBLP BibTeX RDF
19	Joël Cathébras, Roselyne Chotin	A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAs.	WAIFI	2020	DBLP DOI BibTeX RDF
19	Ryoki Kamesaka, Yukinobu Hoshino	Design of the convolution layer using HDL and evaluation of delay time using a camera signal.	FUZZ-IEEE	2020	DBLP DOI BibTeX RDF
19	Mattia Stighezza, Valentina Bianchi, Ilaria De Munari	HDL Code Generation from SIMULINK Environment for Li-Ion Cells State of Charge and Parameter Estimation.	ApplePies	2020	DBLP DOI BibTeX RDF
19	Guo-Ming Sung, Chun-Ting Lee, Chao-Rong Chen	IoT-Based Home Care System with a FPGA Development Board by Using RS-485 Interface and Verilog HDL.	SMC	2020	DBLP DOI BibTeX RDF
19	Roberta Avanzato, Gabriele Nicotra	An efficient HDL IP-core Generator for OFDM modulators.	SYSTEM	2020	DBLP BibTeX RDF
19	Charles Gouert, Nektarios Georgios Tsoutsos	Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain.	DAC	2020	DBLP DOI BibTeX RDF
19	Lucas Lui Motta, Byron Alejandro Acuña Acurio, Nathália Figueiredo Tinoco Aniceto, Luís Geraldo P. Meloni	Design and implementation of a digital down/up conversion directly from/to RF channels in HDL.	Integr.	2019	DBLP DOI BibTeX RDF
19	Ya Li, Peng Jin, Fangjie Hou, Yujie Zhou	Association Between TG-to-HDL-C Ratio and In-Stent Stenosis Under Optical Coherence Tomography Guidance.	J. Medical Syst.	2019	DBLP DOI BibTeX RDF
19	S. Navid Shahrouzi, Darshika G. Perera	HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools.	PACRIM	2019	DBLP DOI BibTeX RDF
19	Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001	Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing.	NORCAS	2019	DBLP DOI BibTeX RDF