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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 429 occurrences of 291 keywords
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Results
Found 709 publication records. Showing 709 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang 0016 |
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 245-249, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson |
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 323-330, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Donglin Li, Otmane Aït Mohamed |
MDG-Based Verification of the Look-Aside Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1064-1068, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin |
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 399-413, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin |
High-Level Synthesis for Self-Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1410-1413, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Moonvin Song, Yunmo Chung |
SoC Design of Speaker Connection System by Efficient Cosimulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1083-1086, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede |
Extended abstract: a race-free hardware modeling language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 255-256, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Tun Li, Yang Guo 0003, GongJie Liu, Sikun Li |
Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 17-25, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 323-326, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Qiu-Zhong Wu, Yi-He Sun |
An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 67-72, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Mohammed Javed Absar, Pol Marchal, Francky Catthoor |
Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, USA, pp. 75-80, 2005, IEEE Computer Society, 0-7803-9347-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Tejas M. Bhatt, Dennis McCain |
Matlab as a development environment for FPGA design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 607-610, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system design flows, rapid prototyping |
20 | Tero Rissa, Adam Donlin, Wayne Luk |
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 253-258, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | He Hu 0001, Da-you Liu, Xiaoyong Du 0001 |
Semi-automatic hardware design using ontologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 8th International Conference on Control, Automation, Robotics and Vision, ICARCV 2004, Kunming, China, 6-9 December 2004, Proceedings, pp. 792-797, 2004, IEEE, 0-7803-8653-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti 0001 |
An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICAI ![In: MICAI 2004: Advances in Artificial Intelligence, Third Mexican International Conference on Artificial Intelligence, Mexico City, Mexico, April 26-30, 2004, Proceedings, pp. 735-745, 2004, Springer, 3-540-21459-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Daniel Kroening, Edmund M. Clarke |
Checking consistency of C and Verilog using predicate abstraction and induction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 66-72, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Mihai Udrescu, Lucian Prodan, Mircea Vladutiu |
Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 96-110, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bubble logic, simulation, views, hardware description languages, quantum algorithms, quantum circuits, entanglement |
20 | Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang 0006, Gong Ouyang, Rob Sharpe, John W. Rockway |
Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 244-249, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu |
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDC ![In: Distributed Computing - IWDC 2004, 6th International Workshop, Kolkata, India, December 27-30, 2004, Proceedings, pp. 353-360, 2004, Springer, 3-540-24076-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11102-11103, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene |
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20095-20100, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Li Shen 0002 |
RTL Concurrent Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 502, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
concurrent fault simulation, fault model, RTL, high-level testing, circuit modeling |
20 | Jonathan Ballagh, James Hwang, H. Ma, Brent Milne, Nabeel Shirazi, Vinay Singh, Jeffrey D. Stroomer |
Specifying Control Logic for DSP Applications in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 1099-1102, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Ryuichi Takahashi, Hajime Ohiwa |
Situated Learning on FPGA for Superscalar Microprocessor Design Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 243-, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Amjad Gawanmeh, Sofiène Tahar, Kirsten Winter |
Interfacing ASM with the MDG Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Abstract State Machines ![In: Abstract State Machines, Advances in Theory and Practice, 10th International Workshop, ASM 2003, Taormina, Italy, March 3-7, 2003, Proceedings, pp. 278-292, 2003, Springer, 3-540-00624-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro |
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 9-11 June 2003, San Diego, CA, USA, pp. 179-185, 2003, IEEE Computer Society, 0-7695-1943-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Rafael Castro-López, Francisco V. Fernández 0001, Fernando Medeiro, Ángel Rodríguez-Vázquez |
Accurate VHDL-based simulation of Sigma-Delta modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 632-635, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum |
Program slicing for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(1), pp. 125-137, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Model checking, Formal verification, VHDL, Program slicing, Hardware description languages |
20 | Christophe Paoli, Marie-Laure Nivet, Jean François Santucci, Antoine Campana |
Path-Oriented Test Data Generation of Behavioral VHDL Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 382-386, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
High level design validation, simulation-based validation, software testing techniques, constraint logic programming language, VHDL |
20 | Stefan Höreth |
A word-level graph manipulation package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 182-192, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Word-level, TUDD, BDD, Decision diagrams, BMD |
20 | Luis Entrena, Celia López, Emilio Olías |
Automatic Insertion of Fault-Tolerant Structures at the RT Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 48-50, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Yanbing Li, Miriam Leeser |
HML, a novel hardware description language and its translation to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(1), pp. 1-8, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin |
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 475-483, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Ryuichi Takahashi, Noriyoshi Yoshida |
Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 71-73, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 182-188, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung |
Virtual Chip: Making Functional Models Work on Real Target Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 170-173, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
20 | Brian T. Graham |
An Interpretation of NODEN in HOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Higher Order Logic Theorem Proving and Its Applications, 7th International Workshop, Valletta, Malta, September 19-22, 1994, Proceedings, pp. 221-234, 1994, Springer, 3-540-58450-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
20 | Hiroto Yasuura, Nagisa Ishiura |
Semantics of a Hardware Design Language for Japanese Standardization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 836-839, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
20 | Jean Christophe Madre, Jean-Paul Billon |
Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 205-210, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
19 | Deheng Yang, Jiayu He, Xiaoguang Mao, Tun Li, Yan Lei, Xin Yi, Jiang Wu |
Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5), pp. 1594-1607, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu 0001 |
HDLdebugger: Streamlining HDL debugging with Large Language Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2403.11671, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
19 | Madam Chakradar, Alok Aggarwal, Xiaochun Cheng, Anuj Rani, Manoj Kumar 0009, Achyut Shankar |
A Non-invasive Approach to Identify Insulin Resistance with Triglycerides and HDL-c Ratio Using Machine learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Process. Lett. ![In: Neural Process. Lett. 55(1), pp. 93-113, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Vishwanath Bijalwan, Vijay Bhaskar Semwal, Ghanapriya Singh, Tapan Kumar Mandal |
HDL-PSR: Modelling Spatio-Temporal Features Using Hybrid Deep Learning Approach for Post-Stroke Rehabilitation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Process. Lett. ![In: Neural Process. Lett. 55(1), pp. 279-298, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Hooman Hematkhah, Yousef Seifi Kavian, Ehsan Namjoo |
PoCH: automatic HDL code generator tool for Polar channel coding decoders in multimedia communication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 82(24), pp. 36739-36768, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Sharad B. Jadhav, N. K. Deshmukh, V. T. Humbe |
HDL-PI: hybrid DeepLearning technique for person identification using multimodal finger print, iris and face biometric features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 82(19), pp. 30039-30064, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Aditya Rajagopal, Diederik Adriaan Vink, Jianyi Cheng, Yann Herklotz |
GSA to HDL: Towards principled generation of dynamically scheduled circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.11048, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Frans Skarman, Oscar Gustafsson |
Spade: An Expression-Based HDL With Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.03079, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Nicolo Vladi Biesuz, Rimsky Caballero, Davide Cieri, Nico Giangiacomi, Francesco Gonnella, Guillermo Loustau De Linares, Andrew Peck |
Hog 2023.1: a collaborative management tool to handle Git-based HDL repository. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.02437, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Anik Mallik, Sanjoy Kundu, Md. Ashikur Rahman |
An FPGA-Based Semi-Automated Traffic Control System Using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.04716, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Shailja Thakur, Jason Blocklove, Hammond Pearce, Benjamin Tan 0001, Siddharth Garg, Ramesh Karri |
AutoChip: Automating HDL Generation Using LLM Feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.04887, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Xiaodan Xing, Javier Del Ser, Yinzhe Wu 0001, Yang Li 0010, Jun Xia, Lei Xu, David N. Firmin, Peter Gatehouse, Guang Yang 0006 |
HDL: Hybrid Deep Learning for the Synthesis of Myocardial Velocity Maps in Digital Twins for Cardiac Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Biomed. Health Informatics ![In: IEEE J. Biomed. Health Informatics 27(10), pp. 5134-5142, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Davi A. Mendes, Gabriel Reves, M. A. Pastrana, Pedro H. L. S. P. Domingues, Helon V. H. Ayala, Alan Conci Kubrusly, Daniel M. Muñoz, Carlos H. Llanos |
A Comparative Analysis of HDL and HLS for Accelerating Machine Learning based Strain Estimation with Ultrasonic Guided Waves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBESC ![In: XIII Brazilian Symposium on Computing Systems Engineering, SBESC 2023, Porto Alegre, Brazil, November 21-24, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-9410-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Jianjun Xu, Jiayu He, Jingyan Zhang, Deheng Yang, Jiang Wu, Xiaoguang Mao |
Validating the Redundancy Assumption for HDL from Code Clone's Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2023 International Symposium on Physical Design, ISPD 2023, Virtual Event, USA, March 26-29, 2023, pp. 247-255, 2023, ACM, 978-1-4503-9978-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Frans Skarman, Lucas Klemmer, Oscar Gustafsson, Daniel Große |
Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on Specification & Design Languages, FDL 2023, Turin, Italy, September 13-15, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-0737-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Lekshmi S. Ajay, Sreenidhi Prabha Rajeev |
Comparative Analysis of Data Compression using Canonical Huffman and Golomb Rice Encoding in Verilog HDL and Implementation in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Pawel Szczepankowski, Wojciech Sleszynski, Tomasz Bajdecki |
A Direct Modulation for Matrix Converters Based on the One-Cycle Atomic Operation Developed in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 69(4), pp. 3303-3312, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Carter Kelly, Benjamin Wilkinson, Amr H. Abd-Elrahman, Orlando Cordero, H. Andrew Lassiter |
Accuracy Assessment of Low-Cost Lidar Scanners: An Analysis of the Velodyne HDL-32E and Livox Mid-40's Temporal Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 14(17), pp. 4220, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Onur Kilinççeker, Ercument Turk, Fevzi Belli, Moharram Challenger |
Model-based ideal testing of hardware description language (HDL) programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Syst. Model. ![In: Softw. Syst. Model. 21(3), pp. 1209-1240, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Bayley King, Rashmi Jha, Temesguen Kebede, David Kapp |
Securing 3rd-Party HDL IP: a Feasibility Study Using Evolutionary Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Hardw. Syst. Secur. ![In: J. Hardw. Syst. Secur. 6(1-2), pp. 17-31, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Xiaodan Xing, Javier Del Ser, Yinzhe Wu 0001, Yang Li 0010, Jun Xia, Lei Xu, David N. Firmin, Peter Gatehouse, Guang Yang 0006 |
HDL: Hybrid Deep Learning for the Synthesis of Myocardial Velocity Maps in Digital Twins for Cardiac Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2203.05564, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Charles Gouert, Nektarios Georgios Tsoutsos |
Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 825, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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19 | Manoj Srinivas Botla, Jai Bala Srujan Melam, Raja Stuthi Paul Pedapati, Srijanee Mookherji, Vanga Odelu, Rajendra Prasath |
Comparative Study of HDL algorithms for Intrusion Detection System in Internet of Vehicles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1700, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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19 | Safi Ullah, Muazzam Ali Khan, Jawad Ahmad 0001, Sajjad Shaukat Jamal, Zil E. Huma, Muhammad Tahir Hassan, Nikolaos Pitropakis, Arshad, William J. Buchanan |
HDL-IDS: A Hybrid Deep Learning Architecture for Intrusion Detection in the Internet of Vehicles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(4), pp. 1340, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan |
Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 20th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2022, Shanghai, China, October 13-14, 2022, pp. 1-8, 2022, IEEE, 979-8-3503-3190-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | K. N. Raja Praveen, Gadug Sudhamsu |
Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3I ![In: 5th International Conference on Contemporary Computing and Informatics, IC3I 2022, Uttar Pradesh, India, December 14-16, 2022, pp. 712-715, 2022, IEEE, 979-8-3503-9826-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | K. N. Raja Praveen, Gadug Sudhamsu |
Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3I ![In: 5th International Conference on Contemporary Computing and Informatics, IC3I 2022, Uttar Pradesh, India, December 14-16, 2022, pp. 712-715, 2022, IEEE, 979-8-3503-9826-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Frans Skarman, Oscar Gustafsson |
Spade: An HDL Inspired by Modern Software Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022, pp. 454-455, 2022, IEEE, 978-1-6654-7390-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Hye-Hyun Lee, Yeon-Seob Song, Kang-Yoon Lee |
Modeling of nano-scale PLL using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTC ![In: 13th International Conference on Information and Communication Technology Convergence, ICTC 2022, Jeju Island, Korea, Republic of, October 19-21, 2022, pp. 2101-2104, 2022, IEEE, 978-1-6654-9939-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Jakob Wenzel 0002, Christian Hochberger |
Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: IEEE International Workshop on Rapid System Prototyping, RSP 2022, Shanghai, China, October 13, 2022, pp. 43-49, 2022, IEEE, 979-8-3503-9851-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan |
Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTAS ![In: 28th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2022, Milano, Italy, May 4-6, 2022, pp. 305-308, 2022, IEEE, 978-1-6654-9998-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuya Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue |
An HDL Simulator with Direct Register Access for Improving Code Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaJCIS ![In: 17th Asia Joint Conference on Information Security, AsiaJCIS 2022, Baoding, China, July 15-16, 2022, pp. 49-55, 2022, IEEE, 978-1-6654-7392-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Saman Fröhlich |
A Fully Fledged HDL Design Flow for In-Memory Computing with Approximation Support ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
RDF |
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19 | Enrico Reggiani, Emanuele Del Sozzo, Davide Conficconi, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio |
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 14(3), pp. 15:1-15:33, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima |
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 77, pp. 180-192, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Talal Bonny |
Chaotic or Hyper-chaotic Oscillator? Numerical Solution, Circuit Design, MATLAB HDL-Coder Implementation, VHDL Code, Security Analysis, and FPGA Realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(3), pp. 1061-1088, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Daniel Gutierrez-Galan, Juan Pedro Dominguez-Morales, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno |
OpenNAS: Open Source Neuromorphic Auditory Sensor HDL code generator for FPGA implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 436, pp. 35-38, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Samed Al, Murat Dener |
STL-HDL: A new hybrid network intrusion detection system for imbalanced dataset on big data environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Secur. ![In: Comput. Secur. 110, pp. 102435, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Friedrich Bauer, Felix Braun, Daniel Hauer, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima Taherinejad, Philipp-Sebastian Vogt |
MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, pp. 399, 2021, IEEE, 978-1-6654-3759-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Seema Singh Saharan, Pankaj Nagar, Kate Townsend Creasy, Eveline O. Stock, James Feng, Mary J. Malloy, John P. Kane |
Application of Machine Learning Ensemble Super Learner for analysis of the cytokines transported by high density lipoproteins (HDL) of smokers and nonsmokers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCI ![In: International Conference on Computational Science and Computational Intelligence, CSCI 2021, Las Vegas, NV, USA, December 15-17, 2021, pp. 370-375, 2021, IEEE, 978-1-6654-5841-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Young-Hoon Kim, Hyungsik Ju, Ik-Jae Chun, Chan-Bok Jeong, Moon-Sik Lee |
Design of Low-latency Synthesizable PUCCH Demodulation Unit Using Simulink HDL Coder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTC ![In: International Conference on Information and Communication Technology Convergence, ICTC 2021, Jeju Island, Korea, Republic of, October 20-22, 2021, pp. 1387-1389, 2021, IEEE, 978-1-6654-2383-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su |
Implement 32-bit RISC-V Architecture Processor using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2021, Hualien City, Taiwan, November 16-19, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-1951-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Ryan Kabrick, John D. Leidel, David Donofrio |
Toward HDL Extensions for Rapid AI/ML Accelerator Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPEC ![In: 2021 IEEE High Performance Extreme Computing Conference, HPEC 2021, Waltham, MA, USA, September 20-24, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2369-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi |
Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2021, Montpellier, France, June 28-30, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-3654-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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19 | Michael Christensen 0001 |
Programming Language Techniques for Improving ISA and HDL Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
RDF |
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19 | Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann |
Verilog HDL and its ancestors and descendants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Program. Lang. ![In: Proc. ACM Program. Lang. 4(HOPL), pp. 87:1-87:90, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Makoto Kato, Naoya Onizawa, Takahiro Hanyu |
Design Automation of Invertible Logic Circuit from a Standard HDL Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FLAP ![In: FLAP 8(5), pp. 1311-1333, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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19 | Roberto Millon, Emmanuel Frati, Enzo Rucci |
A Comparative Study between HLS and HDL on SoC for Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2012.08320, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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19 | Junya Miura, Hiromu Miyazaki, Kenji Kise |
A portable and Linux capable RISC-V computer system in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.03576, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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19 | Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001 |
Efficient Fault Injection based on Dynamic HDL Slicing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.00787, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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19 | Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001 |
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2001.09982, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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19 | Joël Cathébras, Roselyne Chotin |
A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAIFI ![In: Arithmetic of Finite Fields - 8th International Workshop, WAIFI 2020, Rennes, France, July 6-8, 2020, Revised Selected and Invited Papers, pp. 75-91, 2020, Springer, 978-3-030-68868-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Ryoki Kamesaka, Yukinobu Hoshino |
Design of the convolution layer using HDL and evaluation of delay time using a camera signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FUZZ-IEEE ![In: 29th IEEE International Conference on Fuzzy Systems, FUZZ-IEEE 2020, Glasgow, UK, July 19-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-6932-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Mattia Stighezza, Valentina Bianchi, Ilaria De Munari |
HDL Code Generation from SIMULINK Environment for Li-Ion Cells State of Charge and Parameter Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2020, pp. 136-143, 2020, Springer, 978-3-030-66728-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Guo-Ming Sung, Chun-Ting Lee, Chao-Rong Chen |
IoT-Based Home Care System with a FPGA Development Board by Using RS-485 Interface and Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: 2020 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2020, Toronto, ON, Canada, October 11-14, 2020, pp. 3370-3374, 2020, IEEE, 978-1-7281-8526-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Roberta Avanzato, Gabriele Nicotra |
An efficient HDL IP-core Generator for OFDM modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYSTEM ![In: Proceedings of the 5th Symposium for Young Scientists in Technology, Engineering and Mathematics (SYSTEM 2020), Online, May 20, 2020., pp. 44-51, 2020, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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19 | Charles Gouert, Nektarios Georgios Tsoutsos |
Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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19 | Lucas Lui Motta, Byron Alejandro Acuña Acurio, Nathália Figueiredo Tinoco Aniceto, Luís Geraldo P. Meloni |
Design and implementation of a digital down/up conversion directly from/to RF channels in HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 68, pp. 30-37, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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19 | Ya Li, Peng Jin, Fangjie Hou, Yujie Zhou |
Association Between TG-to-HDL-C Ratio and In-Stent Stenosis Under Optical Coherence Tomography Guidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Medical Syst. ![In: J. Medical Syst. 43(1), pp. 4:1-4:6, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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19 | S. Navid Shahrouzi, Darshika G. Perera |
HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACRIM ![In: IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2019, Victoria, BC, Canada, August 21-23, 2019, pp. 1-9, 2019, IEEE, 978-1-7281-2794-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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19 | Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001 |
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-2769-9. The full citation details ...](Pics/full.jpeg) |
2019 |
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