Search results for "IDCT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Heming Sun, Dajiang Zhou, Peilin Liu, Satoshi Goto	A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2014	DBLP DOI BibTeX RDF
22	Hai Huang, Liyi Xiao, Jiaming Liu	CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST.	Circuits Syst. Signal Process.	2014	DBLP DOI BibTeX RDF
22	Ruhan A. Conceição, J. Claudio de Souza, Ricardo Jeske, Marcelo Schiavon Porto, Bruno Zatt, Luciano Volcan Agostini	Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders.	ISCAS	2014	DBLP DOI BibTeX RDF
22	Ziyou Yao, Weifeng He, Liang Hong, Guanghui He, Zhigang Mao	Area and throughput efficient IDCT/IDST architecture for HEVC standard.	ISCAS	2014	DBLP DOI BibTeX RDF
22	Shan-Chun Kuo, Hong-Yuan Jheng, Fan-Chieh Cheng, Shanq-Jang Ruan	Energy-Efficient IDCT Design for DS-CDMA Watermarking Systems.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2013	DBLP DOI BibTeX RDF
22	Ku He, Andreas Gerstlauer, Michael Orshansky	Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems.	IEEE Trans. Circuits Syst. Video Technol.	2013	DBLP DOI BibTeX RDF
22	Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao	A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
22	Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao	A cost effective 2-D adaptive block size IDCT architecture for HEVC standard.	MWSCAS	2013	DBLP DOI BibTeX RDF
22	Guoyong Li, Leibo Liu, Shouyi Yin, Changkui Mao, Shaojun Wei	Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding.	EMC/HumanCom	2013	DBLP DOI BibTeX RDF
22	Ruhan A. Conceição, J. Claudio de Souza, Ricardo Jeske, Marcelo Schiavon Porto, Júlio C. B. de Mattos, Luciano Volcan Agostini	Hardware design for the 32×32 IDCT of the HEVC video coding standard.	SBCCI	2013	DBLP DOI BibTeX RDF
22	Jia Zhu, Zhenyu Liu 0001, Dongsheng Wang 0002	Fully pipelined DCT/IDCT/Hadamard unified transform architecture for HEVC Codec.	ISCAS	2013	DBLP DOI BibTeX RDF
22	Tianlong Ma, Cong Liu 0014, Yibo Fan, Xiaoyang Zeng	A fast 8×8 IDCT algorithm for HEVC.	ASICON	2013	DBLP DOI BibTeX RDF
22	Thomas Tziortzios	Σχεδίαση προσαρμοστικών και δυναμικά αναδιατάξιμων αρχιτεκτονικών αντιστρόφου μετασχηματισμού συνημιτόνου 8X8 2-D IDCT, για χαμηλή κατανάλωση ισχύος		2013	RDF
22	Jaehee You	Unified Constant Geometry Fault Tolerant DCT/IDCT for Image Codec System on a Display Panel.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
22	Qingkui Chen, Haifeng Wang, Songlin Zhuang, Bocheng Liu	Parallel Algorithm of IDCT with GPUs and CUDA for Large-scale Video Quality of 3G.	J. Comput.	2012	DBLP BibTeX RDF
22	Zahaib Akhtar, Mehar Ali, Nadeem A. Khan, Jahangir Ikram	Complexity scalable IDCT based approaches for power-efficient video decoding.	ICASSP	2012	DBLP DOI BibTeX RDF
22	Biao Wang 0001, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink	An Optimized Parallel IDCT on Graphics Processing Units.	Euro-Par Workshops	2012	DBLP DOI BibTeX RDF
22	Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng	A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards.	ICME	2012	DBLP DOI BibTeX RDF
22	Ardimas Andi Purwita, Trio Adiono	A Four Quadrants Parallel-Recursive 2-D DCT/IDCT VLSI Architecture.	ICETET	2012	DBLP DOI BibTeX RDF
22	Thomas Tziortzios, Stavros Dokouzyannis	A novel architecture for fast 2D IDCT decoders, with reduced number of multiplications.	IEEE Trans. Consumer Electron.	2011	DBLP DOI BibTeX RDF
22	Ku He, Andreas Gerstlauer, Michael Orshansky	Controlled timing-error acceptance for low energy IDCT design.	DATE	2011	DBLP DOI BibTeX RDF
22	Rachmad Vidya Wicaksana Putra, Rella Mareta, Nurfitri Anbarsanti, Trio Adiono	The efficient mCBE algorithm and quantization numbers for multiplierless and low complexity DCT/IDCT Image Compression Architecture.	ICEEI	2011	DBLP DOI BibTeX RDF
22	Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Almada Güntzel	An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms.	SBCCI	2011	DBLP DOI BibTeX RDF
22	Chang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin	High reliability built-in self-detection and self-correction design for DCT/IDCT application.	SoCC	2011	DBLP DOI BibTeX RDF
22	Wenqi Bao, Jiang Jiang, Qing Sun 0002, Yuzhuo Fu	A reconfigurable macro-pipelined DCT/IDCT accelerator.	ASICON	2011	DBLP DOI BibTeX RDF
22	Kiho Choi, Sunyoung Lee, Euee S. Jang	Zero coefficient-aware IDCT algorithm for fast video decoding.	IEEE Trans. Consumer Electron.	2010	DBLP DOI BibTeX RDF
22	Yeong-Kang Lai, Yu-Fan Lai	A reconfigurable IDCT architecture for universal video decoders.	IEEE Trans. Consumer Electron.	2010	DBLP DOI BibTeX RDF
22	Taizo Suzuki, Masaaki Ikehara	Integer DCT Based on Direct-Lifting of DCT-IDCT for Lossless-to-Lossy Image Coding.	IEEE Trans. Image Process.	2010	DBLP DOI BibTeX RDF
22	Taizo Suzuki, Masaaki Ikehara	Realization of lossless-to-lossy image coding compatible with JPEG standard by direct-lifting of DCT-IDCT.	ICIP	2010	DBLP DOI BibTeX RDF
22	Pingping Zhu, Jianguo Liu 0004, Shengkui Dai	Fixed-point IDCT without multiplications based on B.G. Lee's algorithm.	Digit. Signal Process.	2009	DBLP DOI BibTeX RDF
22	Pingping Zhu, Jianguo Liu 0004, Shengkui K. Dai, Guoyou Wang	Scaled AAN for Fixed-Point Multiplier-Free IDCT.	EURASIP J. Adv. Signal Process.	2009	DBLP DOI BibTeX RDF
22	Meng-Lin Hsia, Chih-Feng Tseng, Meng-Hsuan Chan, Oscal T.-C. Chen	Low-complexity frame-size down-scaling integrated with IDCT.	SiPS	2009	DBLP DOI BibTeX RDF
22	Huang-Chun Lin, Yu-Hsuan Lee, Tsung-Han Tsai 0001	The cycle-efficient idct algorithm for H.264/SVC with DSP platform.	ICME	2009	DBLP DOI BibTeX RDF
22	Jin Li 0006, Moncef Gabbouj, Jarmo Takala, Hexin Chen	Merged inverse quantization and IDCT for optimized decoder implementation.	EUSIPCO	2009	DBLP BibTeX RDF
22	Ihab Amer, Wael M. Badawy, Vassil S. Dimitrov, Graham A. Jullien	On the refinement of the DCT/IDCT scaling factor sensitivity.	ICME	2008	DBLP DOI BibTeX RDF
22	Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad	An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
22	Michaela Amoo, Clay Gloster	FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT.	ERSA	2007	DBLP BibTeX RDF
22	Lijie Liu, Trac D. Tran	An 8×8 IEEE-Compliant Lifting-Based Multiplierless IDCT Structure and Algorithm.	ICASSP (1)	2007	DBLP DOI BibTeX RDF
22	Peter Lee	An estimation of mismatch error in IDCT decoders implemented with hybrid-LNS arithmetic.	EUSIPCO	2007	DBLP BibTeX RDF
22	Archana Chidanandan, Magdy A. Bayoumi	Area-Efficient NEDA Architecture for The 1-D DCT/IDCT.	ICASSP (3)	2006	DBLP DOI BibTeX RDF
22	Ahmed Ben Atitallah, Patrice Kadionik, Fahmi Ghozzi, Patrice Nouel, Nouri Masmoudi, Philippe Marchegay	Optimization and Implementation on Fpga of the DCT/IDCT Algorithm.	ICASSP (3)	2006	DBLP DOI BibTeX RDF
22	Seung-Kyun Oh, HyunWook Park	Analysis of IDCT and motion-compensation mismatches between spatial-domain and transform-domain motion-compensated coders.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
22	Doru-Florin Chiper, M. N. Shanmukha Swamy, M. Omair Ahmad, Thanos Stouraitis	Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
22	Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang	Condensed recursive structures for computing multidimensional DCT/IDCT with arbitrary length.	IEEE Trans. Circuits Syst. I Regul. Pap.	2005	DBLP DOI BibTeX RDF
22	Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang	Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
22	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh	A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.	ICME	2004	DBLP BibTeX RDF
22	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen	A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.	ISCAS (2)	2004	DBLP BibTeX RDF
22	Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen	A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT.	ISCAS (2)	2004	DBLP BibTeX RDF
22	Dae Won Kim, Jun Rim Choi	Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder.	Integr.	2003	DBLP DOI BibTeX RDF
22	Yew-San Lee, Keng-Khai Ong, Chen-Yi Lee	Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission.	IEEE Trans. Circuits Syst. Video Technol.	2003	DBLP DOI BibTeX RDF
22	Lorenzo Cappellari, Truong Q. Nguyen	Deblocking of video sequences with lapped embedded IDCT.	ICASSP (3)	2003	DBLP DOI BibTeX RDF
22	Kar-Lik Wong, Nigel P. Topham	High performance IDCT realization using complex arithmetic.	ICASSP (2)	2003	DBLP DOI BibTeX RDF
22	Daewon Kim, Daekyu Shin	Energy-based adaptive DCT/IDCT for video coding.	ICME	2003	DBLP DOI BibTeX RDF
22	Luca Fanucci, Sergio Saponara	Data Driven Power Saving for DCT/IDCT VLSI Macrocell.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
22	Daniele Bagni, Antonio Borneo, Luca Celetto	Efficient IDCT implementations on VLIW processors.	EUSIPCO	2002	DBLP BibTeX RDF
22	Wendi Pan, Antonio Ortega, Ibrahim N. Hajj-Ahmad, Roberto Sannino	Proxy-based approaches for IDCT acceleration.	VCIP	2001	DBLP BibTeX RDF
22	Russell E. Henning, Chaitali Chakrabarti	An approach for enabling DCT/IDCT energy reduction scalability in MPEG-2 video codecs.	ICASSP	2001	DBLP DOI BibTeX RDF
22	Ricardo Pezzuol Jacobi, José Porfírio A. de Carvalho	IDCT Design for JPEG Decompression in an Electronic Ballot Box.	SBCCI	2001	DBLP BibTeX RDF
22	Jen-Shiun Chiang, Yi-Fang Chiu, Teng-Hung Chang	A high throughput 2-dimensional DCT/IDCT architecture for real-time image and video system.	ICECS	2001	DBLP DOI BibTeX RDF
22	Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers	An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.	FCCM	2001	DBLP DOI BibTeX RDF
22	Jari Nikara, Jarmo Takala, David Akopian, Jukka Saarinen	Pipeline architecture for DCT/IDCT.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. Shanmukha Swamy	An on-line CORDIC based 2-D IDCT implementation using distributed arithmetic.	ISSPA	2001	DBLP DOI BibTeX RDF
22	Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen	A simple processor core design for DCT/IDCT.	IEEE Trans. Circuits Syst. Video Technol.	2000	DBLP DOI BibTeX RDF
22	Lowell L. Winger	Source adaptive software 2D iDCT with SIMD.	ICASSP	2000	DBLP DOI BibTeX RDF
22	Kuo-Hsing Cheng, Chih-Sheng Huang, Chun-Pin Lin	The design and implementation of DCT/IDCT chip with novel architecture.	ISCAS	2000	DBLP DOI BibTeX RDF
22	Thucydides Xanthopoulos, Anantha P. Chandrakasan	A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
22	Byung Cheol Song, Myung Jun Kim, Sung Kyu Jang, Jong Beom Ra	Modified IDCT kernel for down-conversion of MPEG-2 compressed video.	IEEE Trans. Consumer Electron.	1999	DBLP DOI BibTeX RDF
22	Thou-Ho Chen	A cost-effective 8×8 2-D IDCT core processor with folded architecture.	IEEE Trans. Consumer Electron.	1999	DBLP DOI BibTeX RDF
22	Shen-Fu Hsiao, Wei-Ren Shiue, Jian-Ming Tseng	A cost-efficient and fully-pipelinable architecture for DCT/IDCT.	IEEE Trans. Consumer Electron.	1999	DBLP DOI BibTeX RDF
22	Myung Jun Kim, Byung Cheol Song, Sung Kyu Jang, Jong Beom Ra	An Efficient Video Down Conversion Algorithm Using Modified IDCT Basis Functions.	ICIP (2)	1999	DBLP DOI BibTeX RDF
22	Seehyun Kim, Wonyong Sung	Fixed-point error analysis and word length optimization of 8×8 IDCT architectures.	IEEE Trans. Circuits Syst. Video Technol.	1998	DBLP DOI BibTeX RDF
22	Eri Murata, Masao Ikekawa, Ichiro Kuroda	Fast 2D IDCT implementation with multimedia instructions for a software MPEG2 decoder.	ICASSP	1998	DBLP DOI BibTeX RDF
22	Roberto Rambaldi, Alessandro Uguzzoni, Roberto Guerrieri	A 35 μW 1.1 V gate array 8×8 IDCT processor for video-telephony.	ICASSP	1998	DBLP DOI BibTeX RDF
22	Rizos Sakellariou, Christine Eisenbeis, Peter M. W. Knijnenburg	Efficient implementation of the row-column 8×8 IDCT on VLIW architectures.	EUSIPCO	1998	DBLP BibTeX RDF
22	Yung-Pin Lee, Thou-Ho Chen, Liang-Gee Chen, Mei-Juan Chen, Chung-Wei Ku	A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method.	IEEE Trans. Circuits Syst. Video Technol.	1997	DBLP DOI BibTeX RDF
22	Minhua Zhou, Jan L. P. de Lameillieure	IDCT output range before clipping in MPEG video coding.	Signal Process. Image Commun.	1997	DBLP DOI BibTeX RDF
22	Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan	Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT.	DAC	1997	DBLP DOI BibTeX RDF
22	Vishnu Srinivasan, K. J. Ray Liu	VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications.	IEEE Trans. Circuits Syst. Video Technol.	1996	DBLP DOI BibTeX RDF
22	David Akopian, Jaakko Astola	Pipeline processor for fast architecture oriented regular DCT-IDCT algorithm.	ICASSP	1996	DBLP DOI BibTeX RDF
22	Shih-Chang Hsia, Bin-Da Liu, Jar-Ferr Yang, Bor-Long Bai	VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor.	IEEE Trans. Circuits Syst. Video Technol.	1995	DBLP DOI BibTeX RDF
22	Avanindra Madisetti, Alan N. Willson Jr.	A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications.	IEEE Trans. Circuits Syst. Video Technol.	1995	DBLP DOI BibTeX RDF
22	Yuk-Hee Chan, Wan-Chi Siu	General approach for the realization of DCT/IDCT using convolutions.	Signal Process.	1994	DBLP DOI BibTeX RDF
22	Vishnu Srinivasan, K. J. Ray Liu	Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip.	ICIP (3)	1994	DBLP DOI BibTeX RDF
22	An-Yeu Wu, K. J. Ray Liu	A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion.	ISCAS	1994	DBLP DOI BibTeX RDF
22	Chan S. Kim, Sang W. Song, Man Y. Kim, Young T. Han, Sang A. Kang, Bang W. Lee	200 Mega Pixel Rate IDCT Processor for HDTVC Applications.	ISCAS	1993	DBLP BibTeX RDF
22	Peter A. Ruetz, Po Tong	A 160 Mpixel/s IDCT processor for HDTV.	IEEE Micro	1992	DBLP DOI BibTeX RDF
22	Darren Slawecki, Weiping Li	DCT/IDCT processor design for high data rate image coding.	IEEE Trans. Circuits Syst. Video Technol.	1992	DBLP DOI BibTeX RDF
22	Ja-Ling Wu, Shyh-Huei Hsu, Wei-Jou Duh	A novel two-stage algorithm for DCT and IDCT.	IEEE Trans. Signal Process.	1992	DBLP DOI BibTeX RDF
22	Silvio Cucchi, Marco Fratti	A novel architecture for VLSI implementation of the 2-D DCT/IDCT.	ICASSP	1992	DBLP DOI BibTeX RDF
22	J. R. Parkhurst, K. Wayne Current, Anil K. Jain 0002, J. E. Grishaw	A unified DCT/IDCT architecture for VLSI implementation.	ICASSP	1988	DBLP DOI BibTeX RDF
14	Vasant Patil, Rajeev Kumar	A Fast Inverse Motion Compensation Algorithm for DCT-Domain Video Transcoder.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
14	Sherman Braganza, Miriam Leeser	An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware.	FCCM	2008	DBLP DOI BibTeX RDF
14	Sherman Braganza, Miriam Leeser	An efficient implementation of a phase unwrapping kernel on reconfigurable hardware.	ASAP	2008	DBLP DOI BibTeX RDF
14	Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev	Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.	HiPEAC	2008	DBLP DOI BibTeX RDF
14	Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev	Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.	ARC	2007	DBLP DOI BibTeX RDF
14	Yung-Chi Chang, Wei-Min Chao, Chih-Wei Hsu, Liang-Gee Chen	Platform-Based MPEG-4 SOC Design for Video Communications.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	platform-based architecture, video encoder, MPEG-4 video
14	Vasant Patil, Rajeev Kumar, Jayanta Mukherjee 0001, S. S. Prasad	A Fast Arbitrary Down-Sizing Algorithm for Video Transcoding.	ICIP	2006	DBLP DOI BibTeX RDF
14	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	Compiler-driven FPGA-area allocation for reconfigurable computing.	DATE	2006	DBLP DOI BibTeX RDF
14	Jinwei Wang, Guangjie Liu, Yuewei Dai, Zhiquan Wang, Shiguo Lian	Robustness Analysis of Watermarking Schemes Based on Two Novel Transforms.	ICICIC (3)	2006	DBLP DOI BibTeX RDF
14	Heiner Giefers, Achim Rettberg	Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	high-level synthesis, low power design, voltage scaling, bit-serial architecture