Search results for "Synopsys"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Amir K. Daneshbeh, M. Anwarul Hasan	A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m).	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
14	Johannes Grad, James E. Stine	A Standard Cell Library for Student Projects.	MSE	2003	DBLP DOI BibTeX RDF
14	Deming Chen, Jason Cong, Yiping Fan	Low-power high-level synthesis for FPGA architectures.	ISLPED	2003	DBLP DOI BibTeX RDF	FPGA power reduction, RT-level power estimation, data path optimization
14	Kaijie Wu 0001, Ramesh Karri	Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis.	ITC	2003	DBLP DOI BibTeX RDF
14	Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii	Clock-tree power optimization based on RTL clock-gating.	DAC	2003	DBLP DOI BibTeX RDF	clock-tree synthsis, low-power design
14	Ramesh Karri, Kaijie Wu 0001	Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
14		Formal Verification: Current Use and Future Perspectives.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
14	Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo 0002, Agatino Pennisi, Gaetano Palumbo	Low Power Strategy for a TFT Controller.	DSD	2002	DBLP DOI BibTeX RDF
14	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
14	Miodrag Vujkovic, Carl Sechen	Optimized power-delay curve generation for standard cell ICs.	ICCAD	2002	DBLP DOI BibTeX RDF	ASCII
14	Eren Kursun, Ankur Srivastava 0001, Seda Ogrenci Memik, Majid Sarrafzadeh	Early evaluation techniques for low power binding.	ISLPED	2002	DBLP DOI BibTeX RDF	metric evaluation, scheduling, low power design, resource binding
14	Yannick Saouter, Claude Berrou	Fast soft-output Viterbi decoding for duo-binary turbo codes.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
14	Gaetano Palumbo, Francesco Pappalardo 0002, S. Sannella	Evaluation on power reduction applying gated clock approaches.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
14	Ashok K. Murugavel, N. Ranganathan	A Real Delay Switching Activity Simulator Based on Petri Net Modeling.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
14	Tomás Bautista, Antonio Núñez	Quantitative study of the impact of design and synthesis options on processor core performance.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
14	Praveen K. Murthy, Shuvra S. Bhattacharyya	Shared buffer implementations of signal processing systems usinglifetime analysis techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
14	Henry Kuo, Ingrid Verbauwhede	Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm.	CHES	2001	DBLP DOI BibTeX RDF
14	Praveen K. Murthy, Shuvra S. Bhattacharyya	Shared Memory Implementations of Synchronous Dataflow Specifications.	DATE	2000	DBLP DOI BibTeX RDF
14	Dinesh Ramanathan, Rajesh K. Gupta 0001, Raymond Roth	Interfacing Hardware and Software Using C++ Class Libraries.	ICCD	2000	DBLP DOI BibTeX RDF
14	M. Kivioja, Jouni Isoaho, L. Vänskä	Design and Implementation of Viterbi Decoder with FPGAs.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
14	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Synthesis of Embedded Software from Synchronous Dataflow Specifications.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
14	Valentin Puente, José A. Gregorio, Cruz Izu, Ramón Beivide	Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications.	Euro-Par	1999	DBLP DOI BibTeX RDF
14	Katriina Heikkinen, Petri Vuorimaa	Computation of Two Texture Features in Hardware.	ICIAP	1999	DBLP DOI BibTeX RDF
14	Apostolos A. Kountouris, Christophe Wolinski	High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency Graphs.	EUROMICRO	1999	DBLP DOI BibTeX RDF
14	Tomás Bautista, Antonio Núñez	Design of Efficient SPARC Cores for Embedded Systems.	EUROMICRO	1999	DBLP DOI BibTeX RDF
14	Alexander Schwarz, Bärbel Mertsching, M. Brucke, Wolfgang Nebel, Jürgen Tchorz, Birger Kollmeier	Implementing a Quantitative Model for the "Effective" Signal Processing in the Auditory System on a Dedicated Digital VLSI Hardware.	EUROMICRO	1999	DBLP DOI BibTeX RDF
14	Srivatsan Srinivasan, Lizy Kurian John	On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors.	ICCD	1999	DBLP DOI BibTeX RDF	hardware resource allocation, superscalar processor, pseudorandom sequences, reorder buffer
14	Hyunman Chang, Myung Hoon Sunwoo	A low complexity Reed-Solomon architecture using the Euclid's algorithm.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
14	C. E. Rabel, Mohamad Sawan	PARC: a new pyramidal FPGA architecture based on a RISC processor.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
14	C.-C. Wang, C. J. Huang, G.-C. Lin	A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
14	K. C. Chang 0001, C. A. Lomasney	Obsolete integrated circuit replacement methodology using advanced electronic design automation technology.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
14	Nilanjan Mukherjee, Ramesh Karri	Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	data-path architectures, response compactor, concurrency, built-in self test, high-level synthesis, on-line test, pattern generator, test function
14	E. Lago, Carlos Jesús Jiménez-Fernández, Diego R. López, Santiago Sánchez-Solano, Angel Barriga	XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers.	DATE	1998	DBLP DOI BibTeX RDF
14	Goran Doncev, Miriam Leeser, Shantanu Tarafdar	High Level Synthesis for Designing Custom Computing Hardware.	FCCM	1998	DBLP DOI BibTeX RDF
14	Ramesh Karri, Nilanjan Mukherjee	Versatile BIST: an integrated approach to on-line/off-line BIST.	ITC	1998	DBLP DOI BibTeX RDF
14	John F. Croix, D. F. Wong 0001	A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis.	DAC	1997	DBLP DOI BibTeX RDF
14	Mariana-Eugenia Petre, Guido Masera	A Parametrical Architecture for Reed-Solomon Decoders.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
14	Olav Schettler, Susanne Heymann	Towards support for design description languages in EDA framework.	ICCAD	1994	DBLP BibTeX RDF