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Found 1144 publication records. Showing 1144 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta 0001, Rolf Drechsler |
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rupali Hongekar, Ankita Gupta, Jayakrishna Guddeti, Meghashyam Ashwathnarayan |
Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System Modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat |
Power Analysis Attack on Locking SIB based IJTAG Achitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Kefalas, George Theodoridis |
An FPGA implementation of the VESA Display Stream Compression decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Vasileiadis, Alexandros Mavropoulis, Panagiotis Loukas, Pascal Normand, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis |
Substrate Effect on Low-frequency Noise of synaptic RRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Renjie Chen, Aaron Stillmaker, Bevan M. Baas |
Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán |
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Georgiou, Panayiotis Kolios |
Accurate real-time UAV flight-mode classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas |
Efficient Dynamic Logic Magnitude Comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas |
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Carlos Fernandez, Ioannis Vourkas |
Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Chun-Jen Tsai, Yi-De Lee |
Embedded TCP/IP Controller for a RISC-V SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Vasileios Leon, Elissaios-Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios I. Reisis, Dimitrios Soudris |
Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Nahla A. El-Araby, David Frismuth, Nilson Neves Filho, Axel Jantsch |
Run Time Power and Accuracy Management with Approximate Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Jorge Marqués-García, Alberto Arcusa-Puente, Antonio D. Martínez-Pérez, Francisco Aznar |
Modeling frequency response of gm-boosted inductorless Common-Gate LNA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou |
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Johannes W. Farias, Diego V. Cirilo do Nascimento, Tiago Barros, Samuel Xavier de Souza |
Speculative guardband: exploiting critical-delay variations across cached instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Panagiotis Gkoutis, Georgios Konidas, Grigorios Kalivas |
30 GHz Front-End with Adaptively Biased PA and Current Steering LNA for Phased Array Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Jonas Gava, Ricardo Reis 0001, Luciano Ost |
Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Pedro Aquino Silva, Mateus Grellert, Cristina Meinhardt |
Approximation Workflow for Energy-Efficient Comparators in Decision Tree Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt |
Routability-Driven Detailed Placement Using Reinforcement Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Samuele Germiniani, Graziano Pravadelli |
Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Anastasios Michailidis, Thomas Noulis, Kostas Siozios |
Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Theo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit |
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Kyriaki Tsantikidou, Nicolas Sklavos 0001 |
Flexible Security and Privacy, System Architecture for IoT, in Healthcare. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Muhammad Awais 0009, Marco Platzner |
Automated Framework for Fast Synthesis of Approximate Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh |
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang |
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Nathan Laubeuf |
Analog Compute in Memory and Breaking Digital Number Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rupesh Raj Karn, Ibrahim Abe M. Elfadel |
Confidential Inference in Decision Trees: FPGA Design and Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | |
30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![IEEE, 978-1-6654-9005-4 The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Elissaios-Alexios Papatheofanous, Ph. Tziolos, V. Kalekis, Tzouma Amrou, George E. Konstantoulakis, Georgios Venitourakis, Dionysios I. Reisis |
SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Salvatore Levantino |
Frequency Synthesizers for 5G Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Antonis M. Paschalis, Panagiotis Chatziantoniou, Dimitris Theodoropoulos, Antonis Tsigkanos, Nektarios Kranitis |
High-Performance Hardware Accelerators for Next Generation On-Board Data Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Anu Asokan |
A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Elif Bilge Kavun |
A Power Reduction Technique Based on Linear Transformations for Block Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Vinicius Zanandrea, Cristina Meinhardt |
Exploring Approximate Computing Approaches to Design Power-efficient Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Jose Cayo, Ioannis Vourkas, Antonio Rubio 0001 |
A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Christopher Chuvalas, Ranga Vemuri |
FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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1 | Nikolaos Chatzivangelis, Dimitris Valiantzas, Christos P. Sotiriou, Iordanis Lilitsis |
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Can Aknesil, Elena Dubrova |
Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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1 | Konstantina Koliogeorgi, Dimitris Mylonakis, Sotirios Xydis, Dimitrios Soudris |
High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Jonathan Merk, Changhai Lin, Matthias Kamuf |
Assessing IMD of a Direct-to-RF Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-2, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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1 | Akashdeep Saha, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty |
Design and Analysis of Logic Locking Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Parya Zolfaghari, Sébastien Le Beux |
A Reconfigurable Nanophotonic Architecture based on Phase Change Material. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Durba Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra |
Formal Analysis of Physically Unclonable Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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1 | Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin |
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Siva Satyendra Sahoo, Akash Kumar 0001 |
Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler |
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Vikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu |
Algebraic Techniques for Rectification of Finite Field Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Akshay Balaji, Sneh Saurabh |
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari |
Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Qazi Arbab Ahmed |
Hardware Trojans in Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Lilian Bossuet, El Mehdi Benhani |
Security Assessment of Heterogeneous SoC-FPGA: On the Practicality of Cache Timing Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Konstantina Miteloudi, Lukasz Chmielewski, Lejla Batina, Nele Mentens |
Evaluating the ROCKY Countermeasure for Side-Channel Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do |
Efficient Implementation of Activation Functions for LSTM accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Dominik Sisejkovic, Rainer Leupers |
Trustworthy Hardware Design with Logic Locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | S. Skandha Deepsita, Kuchipudi Divya, Sk. Noor Mahammad |
Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker |
Aspect-Oriented Design Automation with Model Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon |
A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Zhaoyang Cao, Tan-Tan Zhang, Yuan Gao 0011, Wang Ling Goh |
Design of Fully Differential Energy-Efficient Inverter-Based Low-Noise Amplifier for Ultrasound Imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Stavros Nousias, Erion-Vasilis M. Pikoulis, Christos Mavrokefalidis, Aris S. Lalos, Konstantinos Moustakas |
Accelerating 3D scene analysis for autonomous driving on embedded AI computing platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii |
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Prasanna Ravi, Anupam Chattopadhyay, Shivam Bhasin |
Practical Side-Channel and Fault Attacks on Lattice-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Nikos Petrellis, Panagiotis Christakos, Stavros Zogas, Panagiotis Mousouliotis, Georgios Keramidas, Nikolaos S. Voros, Christos P. Antonopoulos |
Challenges Towards Hardware Acceleration of the Deformable Shape Tracking Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier |
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Ming Ming Wong, Lu Chen, Anh Tuan Do |
A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon |
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Sarah Azimi, Corrado De Sio, Luca Sterpone |
On the Evaluation of SEEs on Open-Source Embedded Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Abhiroop Bhattacharjee, Shubham Rai, Ansh Rupani, Michael Raitza, Akash Kumar 0001 |
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet |
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Siva Satyendra Sahoo, Akash Kumar 0001 |
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Alexander El-Kady, Apostolos P. Fournaris, Thanasis Tsakoulis, Evangelos Haleplidis, Vassilis Paliouras |
High-Level Synthesis design approach for Number-Theoretic Transform Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Luca Valente, Davide Rossi, Luca Benini |
Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | |
29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021 ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![IEEE, 978-1-6654-2614-5 The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Johanna Sepúlveda, Dominik Winkler, Daniel Mauricio Sepúlveda, Mario Cupelli, Radek Olexa |
Post-Quantum Cryptography in MPSoC Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Hussam Amrouch, Nan Du, Anteneh Gebregiorgis, Said Hamdioui, Ilia Polian |
Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Pierre Walder, Jean-Michel Portal |
A Self-referenced and regulated sensing solution for PCM with OTS selector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Emmanuel Stapf, Patrick Jauernig, Ferdinand Brasser, Ahmad-Reza Sadeghi |
In Hardware We Trust? From TPM to Enclave Computing on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Steven Colleman, Thomas Verelst, Linyan Mei, Tinne Tuytelaars, Marian Verhelst |
Processor Architecture Optimization for Spatially Dynamic Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Jianming Zhao, Yuan Gao 0011 |
A 13.56 MHz Active Rectifier with PMOS AC-DC Interface for Wireless Powered Medical Implants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Anubhab Baksi |
Classical and Physical Security of Symmetric Key Cryptographic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Moreno Bragaglio, Nicola Donatelli, Samuele Germiniani, Graziano Pravadelli |
System-level bug explanation through program slicing and instruction clusterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Vitor Hugo F. Maciel, Germano Girondi, Elias de Almeida Ramos, Ricardo Reis 0001 |
Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Hongwei Li, Xuemei Fan, Qiang Li, Hao Liu 0013 |
An Efficient Light-weight Configurable Approximate Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers |
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Thiago Santos Copetti, Tobias Gemmeke, Letícia Maria Veiras Bolzani |
Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Naina Gupta 0001, Anupam Chattopadhyay |
In Quest for Fast and Secure SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | S. Moraitis, D. Seitanidis, George Theodoridis, Odysseas G. Koufopavlou |
Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 46-51, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Samiran Ganguly, Nikhil Shukla, Avik W. Ghosh |
Ultra-Compact, Scalable, Energy-Efficient $VO_{2}$ Insulator-Metal-Transition Oxide Based Spiking Neurons for Liquid State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 147-152, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Eberlein, Harald Pretl |
Subthreshold-Hybrid Solutions for Thermal Sensor and Reference Circuits in Advanced CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 186-191, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Andrew B. Kahng |
Open-Source EDA: If We Build It, Who Will Come? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Valentino Peluso, Enrico Macii, Andrea Calimera |
Optimization Tools for ConvNets on the Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 204-205, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Yongnan Chen, Yanhan Zeng, Junkai Chen, Hong-Zhou Tan |
PT controlled buck converter with adaptive PCCM using charge monitoring and NMOS current sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 176-180, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza |
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 94-99, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury |
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 123-128, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Chhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand 0002, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu |
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 76-81, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
1 | Xuan Hu, Naimul Hassan, Wesley H. Brigner, Maverick Chauwin, Joseph S. Friedman |
Device Modeling and Circuit Design for Scalable Beyond-CMOS Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 210-211, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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1 | Haochang Zhi, Yanhan Zeng, Wei Zhou, Hongzhou Tan |
Fast-transient, light-load efficient DC-DC converter using an auxiliary D-LDO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 181-185, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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1 | David Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin |
A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 52-57, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
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