Search results for "compactor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain.	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
15	Jin Ding, David Moloney, Xiaojun Wang 0001	Aliasing-Free Space and Time Compactions with Limited Overhead.	ISQED	2000	DBLP DOI BibTeX RDF
15	Ondrej Novák	Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata.	EDCC	1999	DBLP DOI BibTeX RDF	linear cyclic codes, hardware test pattern generators, weighted random testing, Cellular automata, BIST, linear feedback shift registers, pseudoexhaustive testing
15	Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal	GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.	VLSI Design	1999	DBLP DOI BibTeX RDF
15	Janusz Rajski, Jerzy Tyszer	Modular logic built-in self-test for IP cores.	ITC	1998	DBLP DOI BibTeX RDF
15	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
15	Slawomir Pilarski, André Ivanov, Tiko Kameda	On minimizing aliasing in scan-based compaction.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, scan path, test response compaction
15	Keiho Akiyama, Kewal K. Saluja	A method of reducing aliasing in a built-in self-test environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
15	Kurt Mehlhorn, Stefan Näher	A faster compaction algorithm with automatic jog insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	Pei-Yung Hsiao, Wu-Shiung Feng	Using a multiple storage quad tree on a hierarchical VLSI compaction scheme.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin	'Zone-refining' techniques for IC layout compaction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	David Marple, Michiel Smulders, Henk Hegen	Tailor: a layout system based on trapezoidal corner stitching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	Knut M. Just, Edgar Auer, Werner L. Schiele, Alexander Schwaferts	PALACE: A Kayout Generator for SCVS Logic Blocks.	DAC	1990	DBLP DOI BibTeX RDF
15	Hyunchul Shin, Chi-Yuan Lo	An Efficient Two-Dimensional Layout Compaction Algorithm.	DAC	1989	DBLP DOI BibTeX RDF
15	Jin-Fuw Lee	A new framework of design rules for compaction of VLSI layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
15	Charles H. Ng	A "gridless" Variable-Width Channel Router for Marco Cell Design.	DAC	1987	DBLP DOI BibTeX RDF
15	Lars S. Nyland, Stephen W. Daniel, C. Durward Rogers	Improving Virtual-Grid Compaction Through Grouping.	DAC	1987	DBLP DOI BibTeX RDF
15	Dwight D. Hill, John P. Fishburn, Mary Diane Palmer Leland	Effective use of virtual grid compaction in macro-module generators.	DAC	1985	DBLP DOI BibTeX RDF
15	Stef van Vlierberghe, Jeff Rijmenants, Walter Heyns	Symbolic hierarchical artwork generation system.	DAC	1985	DBLP DOI BibTeX RDF