Search results for "defect-tolerance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Jennifer Tang, Da Wang, Yury Polyanskiy, Gregory W. Wornell	Defect Tolerance: Fundamental Limits and Examples.	IEEE Trans. Inf. Theory	2018	DBLP DOI BibTeX RDF
18	Onur Tunali, Mustafa Altun	Logic synthesis and defect tolerance for memristive crossbar arrays.	DATE	2018	DBLP DOI BibTeX RDF
18	Jennifer Tang, Da Wang, Yury Polyanskiy, Gregory W. Wornell	Defect tolerance: fundamental limits and examples.	CoRR	2016	DBLP BibTeX RDF
18	Stephen Sunter, Alessandro Valerio, Riccardo Miglierina	Measuring defect tolerance within mixed-signal ICs.	ETS	2016	DBLP DOI BibTeX RDF
18	Jennifer Tang, Da Wang, Yury Polyanskiy, Gregory W. Wornell	Defect tolerance: Fundamental limits and examples.	ISIT	2016	DBLP DOI BibTeX RDF
18	Tianjian Li, Li Jiang 0002, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty	Defect tolerance for CNFET-based SRAMs.	ITC	2016	DBLP DOI BibTeX RDF
18	Stephen Sunter, Alessandro Valerio, Riccardo Miglierina	Automated measurement of defect tolerance in mixed-signal ICs.	ITC	2016	DBLP DOI BibTeX RDF
18	Mariem Slimani, Arwa Ben Dhia, Lirida A. B. Naviner	A novel analytical method for defect tolerance assessment.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
18	Onur Tunali, Mustafa Alton	Defect tolerance in diode, FET, and four-terminal switch based nano-crossbar arrays.	NANOARCH	2015	DBLP DOI BibTeX RDF
18	Hsunwei Hsiung, Sandeep K. Gupta 0001	A multi-layered methodology for defect-tolerance of datapath modules in processors.	VTS	2015	DBLP DOI BibTeX RDF
18	Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri	Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA.	ReConFig	2014	DBLP DOI BibTeX RDF
18	Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri	Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy.	FPL	2014	DBLP DOI BibTeX RDF
18	Shuo Wang, Jianwei Dai, Lei Wang 0003	Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory.	ACM J. Emerg. Technol. Comput. Syst.	2013	DBLP DOI BibTeX RDF
18	Hsiu-Chuan Shih, Cheng-Wen Wu	An enhanced double-TSV scheme for defect tolerance in 3D-IC.	DATE	2013	DBLP DOI BibTeX RDF
18	Jason Cong, Bingjun Xiao	Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance.	DAC	2013	DBLP DOI BibTeX RDF
18	Bo Yuan 0006, Bin Li 0025	Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures.	J. Comput. Sci. Technol.	2012	DBLP DOI BibTeX RDF
18	Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger	Exploiting microarchitectural redundancy for defect tolerance.	ICCD	2012	DBLP DOI BibTeX RDF
18	Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba	Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly.	DFT	2012	DBLP DOI BibTeX RDF
18	Haejun Seo, Yoonseok Heo, Taewon Cho	Three-Dimensional Stacked Memory System for Defect Tolerance.	FGIT	2012	DBLP DOI BibTeX RDF
18	Da Cheng, Sandeep Gupta 0001	A novel software-based defect-tolerance approach for application-specific embedded systems.	ICCD	2011	DBLP DOI BibTeX RDF
18	Glenn H. Chapman, Bonnie L. Gray, Vijay K. Jain	Creating Defect Tolerance in Microfluidic Capacitive/Photonic Biosensors.	DFT	2011	DBLP DOI BibTeX RDF
18	Erik MacLean, Vijay K. Jain	A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance.	DFT	2011	DBLP DOI BibTeX RDF
18	Vijay K. Jain, Glenn H. Chapman	Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid.	DFT	2011	DBLP DOI BibTeX RDF
18	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	On using address scrambling to implement defect tolerance in SRAMs.	ITC	2011	DBLP DOI BibTeX RDF
18	Jianwei Dai, Lei Wang 0003, Fabrizio Lombardi	An information-theoretic analysis of quantum-dot cellular automata for defect tolerance.	ACM J. Emerg. Technol. Comput. Syst.	2010	DBLP DOI BibTeX RDF
18	Mehdi Baradaran Tahoori	Variation and defect tolerance for diode-based nano crossbars.	Nano Commun. Networks	2010	DBLP DOI BibTeX RDF
18	Jianwei Dai, Lei Wang 0003, Faquir C. Jain	Analysis of Defect Tolerance in Molecular Crossbar Electronics.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
18	Sanghyun Ahn, Zachary D. Patitz, Noh-Jin Park, Hyoung Joong Kim, Nohpill Park	A Floorprint-Based Defect Tolerance for Nano-Scale Application-Specific IC.	IEEE Trans. Instrum. Meas.	2009	DBLP DOI BibTeX RDF
18	Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi	Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism.	NANOARCH	2009	DBLP DOI BibTeX RDF
18	Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara	Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory.	AHS	2009	DBLP DOI BibTeX RDF
18	Kypros Constantinides	Online Low-Cost Defect Tolerance Solutions for Microprocessor Designs.		2009	RDF
18	Asbjørn Djupdal, Pauline C. Haddow	Defect Tolerance Inspired by Artificial Evolution.	ISVLSI	2008	DBLP DOI BibTeX RDF
18	Weiguo Tang, Lei Wang 0003	A DSP nanosystem with defect tolerance.	NANOARCH	2008	DBLP DOI BibTeX RDF
18	Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier	Defect tolerance in QCA-based PLAs.	NANOARCH	2008	DBLP DOI BibTeX RDF
18	Michael T. Niemier, Michael Crocker, Xiaobo Sharon Hu	Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA.	DFT	2008	DBLP DOI BibTeX RDF
18	Mo Liu 0005, Craig S. Lent	Reliability and Defect Tolerance in Metallic Quantum-dot Cellular Automata.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	single electronics, nanoelectronics, QCA, quantum-dot cellular automata, molecular electronics
18	Ahmad A. Al-Yamani, S. Ramsundar, Dhiraj K. Pradhan	A Defect Tolerance Scheme for Nanotechnology Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2007	DBLP DOI BibTeX RDF
18	Warren Robinett, Philip Kuekes, R. Stanley Williams	Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2007	DBLP DOI BibTeX RDF
18	Snorre Aunet, Hans Kristian Otnes Berge	Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits.	IWANN	2007	DBLP DOI BibTeX RDF
18	Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai	Utilization of SECDED for soft error and variation-induced defect tolerance in caches.	DATE	2007	DBLP DOI BibTeX RDF
18	Susmit Biswas, Gang Wang 0015, Tzvetan S. Metodi, Ryan Kastner, Frederic T. Chong	Combining static and dynamic defect-tolerance techniques for nanoscale memory systems.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Jianwei Dai, Lei Wang 0003, Faquir C. Jain	Analysis of defect tolerance in molecular electronics using information-theoretic measures.	NANOARCH	2007	DBLP DOI BibTeX RDF
18	Krishnendu Chakrabarty	Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.	DFT	2006	DBLP BibTeX RDF
18	Michael Nicolaidis, Lorena Anghel, Nadir Achouri	Memory Defect Tolerance Architectures for Nanotechnologies.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	word repair, nanotechnologies, BISR, memory repair, high defect densities
18	Zohair Hyder, John Wawrzynek	Defect Tolerance in Multiple-FPGA Systems.	FPL	2005	DBLP DOI BibTeX RDF
18	Mehdi Baradaran Tahoori	A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.	ICCAD	2005	DBLP DOI BibTeX RDF
18	Anthony J. Yu, Guy G. Lemieux	FPGA Defect Tolerance: Impact of Granularity.	FPT	2005	DBLP BibTeX RDF
18	Mohammad Tehranipoor	Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.	DFT	2005	DBLP DOI BibTeX RDF
18	Zhanglei Wang, Krishnendu Chakrabarty	Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics.	ITC	2005	DBLP DOI BibTeX RDF
18	Ethan Schuchman, T. N. Vijaykumar	Rescue: A Microarchitecture for Testability and Defect Tolerance.	ISCA	2005	DBLP DOI BibTeX RDF
18	Mahim Mishra	Scalable Defect Tolerance Beyond the SIA Roadmap.	FPL	2004	DBLP DOI BibTeX RDF
18	Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger	Exploiting Microarchitectural Redundancy For Defect Tolerance.	ICCD	2003	DBLP DOI BibTeX RDF
18	Nobuhiro Tomabechi, Teruki Ito	Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers.	ICECS	2001	DBLP DOI BibTeX RDF
18	Israel Koren, Zahava Koren	Defect tolerance in VLSI circuits: techniques and yield analysis.	Proc. IEEE	1998	DBLP DOI BibTeX RDF
18	Howard Falk	Prolog To Defect Tolerance In Vlsi Circuits: Techniques And Yield Analysis.	Proc. IEEE	1998	DBLP DOI BibTeX RDF
18	Fausto Distante, Mariagiovanna Sami, Renato Stefanelli	Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance.	DFT	1997	DBLP DOI BibTeX RDF
18	W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider	The Teramac Custom Computer: Extending the Limits with Defect Tolerance.	DFT	1996	DBLP DOI BibTeX RDF
18	Adit D. Singh	ADTS: an array defect-tolerance scheme for wafer scale gate arrays.	DFT	1995	DBLP DOI BibTeX RDF
18	David Wessels, Jon C. Muzio	Analyzing and improving delay defect tolerance in pipelined combinational circuits.	DFT	1995	DBLP DOI BibTeX RDF
18	Jean-Luc Patry	Intégration sur tranche d'une architecture massivement parallèle tolérant les défauts de fin de fabrication. (Wafer scale integration of a massively parallel architecture for defect tolerance).		1992	RDF
18	Fausto Distante, Mariagiovanna Sami, Renato Stefanelli, Giancarlo Storti-Gajan	Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution.	Proc. IEEE	1991	DBLP DOI BibTeX RDF
17	George R. Roelke, Rusty O. Baldwin, Barry E. Mullins, Yong C. Kim	A Cache Architecture for Extremely Unreliable Nanotechnologies.	IEEE Trans. Reliab.	2007	DBLP DOI BibTeX RDF
17	Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim	Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects.	DFT	2006	DBLP DOI BibTeX RDF
17	Yuri Khramov	The Cost of Code Quality.	AGILE	2006	DBLP DOI BibTeX RDF
17	Nader Mir-Fakhraei	ATM switching architectures for wafer-scale integration.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
15	Mehdi Baradaran Tahoori, Subhasish Mitra	Defect and Fault Tolerance of Reconfigurable Molecular Computing.	FCCM	2004	DBLP DOI BibTeX RDF
15	Abderrahim Doumar, Hideo Ito	Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	Olivier Temam	The rebirth of neural networks.	ISCA	2010	DBLP DOI BibTeX RDF	neural networks
11	Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Necromancer: enhancing system throughput by animating dead cores.	ISCA	2010	DBLP DOI BibTeX RDF	execution abstraction, heterogeneous core coupling, manufacturing defects
11	Mustafa Altun, Marc D. Riedel, Claudia Neuhauser	Nanoscale digital computation through percolation.	DAC	2009	DBLP DOI BibTeX RDF	nanoscale digital computation, logic synthesis, percolation
11	Grant Martin	Panel: Best ways to use billions of devices on a chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli	Programmable logic circuits based on ambipolar CNFET.	DAC	2008	DBLP DOI BibTeX RDF	CNFET, FPGA, PLA, carbon nanotube
11	Seetharam Narasimhan, Somnath Paul, Swarup Bhunia	Collective computing based on swarm intelligence.	DAC	2008	DBLP DOI BibTeX RDF	collective intelligence, adaptive computing, multi-processor
11	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Tao Xu 0002, Krishnendu Chakrabarty	Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips.	ETS	2007	DBLP DOI BibTeX RDF
11	Massoud Masoumi, Farshid Raissi, Mahmoud Ahmadian	NanoCMOS-Molecular Realization of Rijndael.	CHES	2006	DBLP DOI BibTeX RDF	VLSI realization, CMOL, Rijndael
11	Mariam Momenzadeh, Mehdi Baradaran Tahoori, Jing Huang 0001, Fabrizio Lombardi	Quantum Cellular Automata: New Defects and Faults for New Devices.	IPDPS	2004	DBLP DOI BibTeX RDF
11	Seth Copen Goldstein, Mihai Budiu	NanoFabrics: spatial computing using molecular electronics.	ISCA	2001	DBLP DOI BibTeX RDF
11	Israel Koren	Should Yield be a Design Objective?	ISQED	2000	DBLP DOI BibTeX RDF	routing, floorplanning, yield, compaction, critical area
11	Markus Rudack, Dirk Niggemeyer	Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM.	DFT	1999	DBLP DOI BibTeX RDF
11	Sy-Yen Kuo, S.-C. Liang	Design and analysis of defect tolerant hierarchical sorting networks.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
11	Jonathon David Mellott, Jermy C. Smith, Fred J. Taylor	The Gauss machine: A Galois-enhanced quadratic residue number system systolic array.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF