Search results for "gate-delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Shubhankar Basu, Priyanka Thakore, Ranga Vemuri	Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.	ISQED	2007	DBLP DOI BibTeX RDF
18	Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin, Amir H. Ajami	Modeling and Propagation of Noisy Waveforms in Static Timing Analysis.	DATE	2005	DBLP DOI BibTeX RDF
18	Hiroshi Saito, Alex Kondratyev, Takashi Nanya	Design of Asynchronous Controllers with Delay Insensitive Interface.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	delay insensitive interface, gate-level transformation, behavioral transformation, asynchronous circuits, hazards
18	Norio Kuji, Takako Ishihara	EB-Testing-Pad Method and Its Evaluation by Actual Devices.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability
18	Cho W. Moon, Paul R. Stephan, Robert K. Brayton	Specification, synthesis, and verification of hazard-free asynchronous circuits.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
18	Eric M. Schwarz, Michael J. Flynn	Cost-efficient high-radix division.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
16	Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor	Test-Pattern Grading and Pattern Selection for Small-Delay Defects.	VTS	2008	DBLP DOI BibTeX RDF	Small-delay defects, pattern grading, pattern selection, ATPG
16	Yu Cao, Lawrence T. Clark	Mapping statistical process variations toward circuit performance variability: an analytical modeling approach.	DAC	2005	DBLP DOI BibTeX RDF	delay, process variations, variability
16	Kazuhito Ito, Daisuke Suzuki	A high-level synthesis method for simultaneous placement and scheduling considering data communication delay.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
16	Soha Hassoun	Critical path analysis using a dynamically bounded delay model.	DAC	2000	DBLP DOI BibTeX RDF
16	Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara	A high resolution digital CMOS time-to-digital converter based on nested delay locked loops.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
16	Yuji Kukimoto, Robert K. Brayton	Hierarchical Functional Timing Analysis.	DAC	1998	DBLP DOI BibTeX RDF
16	David Wessels, Jon C. Muzio	The dangers of simplistic delay models.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	critical paths, Delay models, path sensitization, circuit delays
16	Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Synthesis for testability techniques for asynchronous circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
16	Andrzej Krasniewski, Leszek B. Wronski	Coverage of Delay Faults: When 13% and 99% Mean the Same.	EDCC	1994	DBLP DOI BibTeX RDF
16	Kye S. Hedlund	Electrical optimization of PLAs.	DAC	1985	DBLP DOI BibTeX RDF
16	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
15	Vishal Khandelwal, Ankur Srivastava 0001	A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
15	Vishal Khandelwal, Ankur Srivastava 0001	A general framework for accurate statistical timing analysis considering correlations.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, statistical timing
15	Sachin S. Sapatnekar, Rahul B. Deokar	Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
14	Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis	Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
14	Walter Schneider	Statistical gate-delay modeling with copulas.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14	Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee	Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.	VTS	2021	DBLP DOI BibTeX RDF
14	Peng Cao 0002, Zhiyuan Liu 0011, Jingjing Guo, Jiangping Wu	An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation.	IEEE Access	2019	DBLP DOI BibTeX RDF
14	Paolo Paletti, Mina Asghari Heidarlou, Karla González-Serrano, Cristobal Alessandri, Alan C. Seabaugh	Steep Subthreshold Swing Originating from Gate Delay.	DRC	2019	DBLP DOI BibTeX RDF
14	Taizhi Liu, Chang-Chih Chen, Linda Milor	Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors.	IEEE Trans. Emerg. Top. Comput.	2018	DBLP DOI BibTeX RDF
14	Asad Ali Nawaz, Jubaid Abdul Qayyum, Ahmet Cagri Ulusoy, John D. Cressler, Wibo D. Van Noort	A new figure-of-merit for CML gate delay estimation.	WiSNet	2018	DBLP DOI BibTeX RDF
14	Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet	On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept.	NEWCAS	2017	DBLP DOI BibTeX RDF
14	Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.	IPSJ Trans. Syst. LSI Des. Methodol.	2016	DBLP DOI BibTeX RDF
14	Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda	An effective ATPG flow for Gate Delay Faults.	DTIS	2015	DBLP DOI BibTeX RDF
14	Bishnu Prasad Das, Hidetoshi Onodera	On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
14	Steven Bielby, Gordon W. Roberts	Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques.	CCECE	2014	DBLP DOI BibTeX RDF
14	Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations.	Integr.	2013	DBLP DOI BibTeX RDF
14	Donkyu Baek, Insup Shin, Youngsoo Shin	Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
14	Prasanjeet Das, Sandeep K. Gupta 0001	Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits.	ICCD	2013	DBLP DOI BibTeX RDF
14	Suchismita Roy, P. P. Chakrabarti 0001, Pallab Dasgupta	SAT based timing analysis for fixed and rise/fall gate delay models.	Integr.	2012	DBLP DOI BibTeX RDF
14	Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
14	Donkyu Baek, Insup Shin, Youngsoo Shin	Gate delay modeling for static timing analysis of body-biased circuits.	ICICDT	2012	DBLP DOI BibTeX RDF
14	Ali Arabi M. Shahi, Payman Zarkesh-Ha	Prediction of gate delay variation for CNFET under CNT density variation.	DFT	2012	DBLP DOI BibTeX RDF
14	Chin-Hsin Lin, Marek Syrzycki	Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution.	Circuits Syst.	2011	DBLP DOI BibTeX RDF
14	Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto	Gate Delay Estimation in STA under Dynamic Power Supply Noise.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
14	Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas	Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
14	Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto	Gate delay estimation in STA under dynamic power supply noise.	ASP-DAC	2010	DBLP DOI BibTeX RDF
14	Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita	A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.	ISSCC	2010	DBLP DOI BibTeX RDF
14	Mingzhi Gao, Zuochang Ye, Yao Peng 0003, Yan Wang 0023, Zhiping Yu	A comprehensive model for gate delay under process variation and different driving and loading conditions.	ISQED	2010	DBLP DOI BibTeX RDF
14	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Statistical Gate Delay Model for Multiple Input Switching.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
14	Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan	Within-die gate delay variability measurement using re-configurable ring oscillator.	CICC	2008	DBLP DOI BibTeX RDF
14	Sangwoo Han, Yooseong Kim, Woosick Choi, Inho Shin, Youngdoo Choi	A second-order gate delay modeling method with an efficient sensitivity analysis.	APCCAS	2008	DBLP DOI BibTeX RDF
14	Y. Satish Kumar, Jun Li 0066, Claudio Talarico, Janet Meiling Wang	A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching	CoRR	2007	DBLP BibTeX RDF
14	Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan	Robust analytical gate delay modeling for low voltage circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
14	Shahdad Irajpour, Sandeep K. Gupta 0001, Melvin A. Breuer	Multiple tests for each gate delay fault: higher coverage and lower test application cost.	ITC	2005	DBLP DOI BibTeX RDF
14	Soroush Abbaspour, Massoud Pedram	Gate delay calculation considering the crosstalk capacitances.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	A statistical gate delay model for intra-chip and inter-chip variabilities.	ASP-DAC	2003	DBLP DOI BibTeX RDF
14	George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis	A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model.	VLSI Design	2001	DBLP DOI BibTeX RDF
14	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	A New Gate Delay Model for Simultaneous Switching and Its Applications.	DAC	2001	DBLP DOI BibTeX RDF
14	Kaoru Kusafuka, Hidehisa Shimizu, Shinichi Kimura	Driving method for gate-delay compensation of TFT/LCD.	IBM J. Res. Dev.	1998	DBLP DOI BibTeX RDF
14	Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo Takamatsu	Tests for small gate delay faults in combinational circuits and a test generation method.	Syst. Comput. Jpn.	1997	DBLP DOI BibTeX RDF
14	Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi	CMOS Gate Delay Models for General RLC Loading.	ICCD	1997	DBLP DOI BibTeX RDF
14	P. Cavallera, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits.	ED&TC	1996	DBLP DOI BibTeX RDF
14	Noriyoshi Itazaki, Kozo Kinoshita, Hisao Naitoh	Test pattern generation for crosstalk faults considering the gate delay.	Syst. Comput. Jpn.	1995	DBLP DOI BibTeX RDF
14	G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus	Gate delay fault test generation for non-scan circuits.	ED&TC	1995	DBLP DOI BibTeX RDF
14	Arno Kunzmann, Frank Böhland	Gate-Delay Fault Test with Conventional Scan-Design.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
14	Franco Fummi, Donatella Sciuto, Micaela Serra	Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method.	DFT	1994	DBLP BibTeX RDF
14	Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage	A Gate-Delay Model for high-Speed CMOS Circuits.	DAC	1994	DBLP DOI BibTeX RDF
14	Pranav Ashar, Srinivas Devadas, Kurt Keutzer	Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.	Formal Methods Syst. Des.	1993	DBLP DOI BibTeX RDF
14	Udo Mahlstedt	DELTEST: Deterministic Test Generation for Gate-Delay Faults.	ITC	1993	DBLP DOI BibTeX RDF
14	Daniel Brand, Vijay S. Iyengar	Identification of Single Gate Delay Fault Redundancies.	ICCD	1992	DBLP DOI BibTeX RDF
14	Weiwei Mao, Michael D. Ciletti	Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.	ITC	1992	DBLP DOI BibTeX RDF
14	Pranav Ashar, Srinivas Devadas, Kurt Keutzer	Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.	ITC	1991	DBLP DOI BibTeX RDF
14	Veronika Eisele, Bernhard Hoppe, Oliver Kiehl	Transmission gate delay models for circuit optimization.	EURO-DAC	1990	DBLP DOI BibTeX RDF
14	Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li	Static timing analysis for flexible TFT circuits.	DAC	2010	DBLP DOI BibTeX RDF	flexible electronics, static timing analysis
14	Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava	Computation of Waveform Sensitivity Using Geometric Transforms for SSTA.	ISQED	2008	DBLP DOI BibTeX RDF	Timing Library, Accuracy, SSTA
14	Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu	Wire Retiming Problem With Net Topology Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	An analytical model for negative bias temperature instability.	ICCAD	2006	DBLP DOI BibTeX RDF
14	Zhaojun Wo, Israel Koren	Effective analytical delay model for transistor sizing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
14	Arun Krishnamachary, Jacob A. Abraham	Test generation for resistive opens in CMOS.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	resistive opens, delay testing, defect detection
14	Srinivas Devadas, Kurt Keutzer	Synthesis of robust delay-fault-testable circuits: practice.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
13	Haining Fan, M. Anwar Hasan	A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	subquadratic space complexity multiplier, shifted polynomial basis, Finite field, coordinate transformation, Toeplitz matrix
13	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent waveform propagation for static timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
13	Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera	Equivalent Waveform Propagation for Static Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
13	Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao	A high-resolution and fast-conversion time-to-digital converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
13	Matthias Ringe, Thomas Lindenkreuz, Erich Barke	Static Timing Analysis Taking Crosstalk into Account.	DATE	2000	DBLP DOI BibTeX RDF
13	Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev	What is the cost of delay insensitivity?	ICCAD	1999	DBLP DOI BibTeX RDF
13	Weiyu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test generation in VLSI circuits for crosstalk noise.	ITC	1998	DBLP DOI BibTeX RDF
11	Takashi Enami, Masanori Hashimoto, Takashi Sato	Decoupling capacitance allocation for timing with statistical noise model and timing analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.	DATE	2004	DBLP DOI BibTeX RDF
11	Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas	Low power ATPG for path delay faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults, PODEM
11	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Variable Observation Times.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	statistical delay fault coverage, delay test observation times, delay fault testing
11	Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das	Delay Fault Coverage Enhancement Using Multiple Test Observation Times.	VLSI Design	1997	DBLP DOI BibTeX RDF
11	Wayne Wei-Ming Dai	Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract).	DAC	1997	DBLP DOI BibTeX RDF
11	William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Valid clock frequencies and their computation in wavepipelined circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
11	Abhijit Chatterjee, Jacob A. Abraham	RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults.	ICCAD	1994	DBLP DOI BibTeX RDF
11	Ankan K. Pramanick, Sudhakar M. Reddy	On the fault coverage of delay fault detecting tests.	EURO-DAC	1990	DBLP DOI BibTeX RDF
11	Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska	Timing analysis considering IR drop waveforms in power gating designs.	ICCD	2008	DBLP DOI BibTeX RDF
11	Malcolm Taylor, Chi-En Daniel Yin, Min Wu, Gang Qu 0001	A Hardware-Assisted Data Hiding Based Approach in Building High-Performance Trusted Computing Systems.	HOST	2008	DBLP DOI BibTeX RDF
11	Shubhankar Basu, Ranga Vemuri	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.	ISVLSI	2007	DBLP DOI BibTeX RDF
11	Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang	IDDT ATPG Based on Ambiguous Delay Assignments.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	IDDT testing, delay Assignments, stuck-open fault
11	Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.	A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, MAC, multiplier
11	Hyunsik Im	Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model).	ISLPED	2002	DBLP DOI BibTeX RDF	?-power model, MOSFET modeling, Saturation current
11	Scott Woods, Giorgio Casinovi	Gate-level simulation of digital circuits using multi-valued Boolean algebras.	ICCAD	1995	DBLP DOI BibTeX RDF	Gate-level logic simulation, mixed-mode simulation, boolean equations solution, multi-valued logic