Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Shubhankar Basu, Priyanka Thakore, Ranga Vemuri |
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 814-820, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin, Amir H. Ajami |
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 776-777, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Hiroshi Saito, Alex Kondratyev, Takashi Nanya |
Design of Asynchronous Controllers with Delay Insensitive Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 93-98, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay insensitive interface, gate-level transformation, behavioral transformation, asynchronous circuits, hazards |
18 | Norio Kuji, Takako Ishihara |
EB-Testing-Pad Method and Its Evaluation by Actual Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 179-184, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability |
18 | Cho W. Moon, Paul R. Stephan, Robert K. Brayton |
Specification, synthesis, and verification of hazard-free asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 85-100, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Eric M. Schwarz, Michael J. Flynn |
Cost-efficient high-radix division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(4), pp. 293-305, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor |
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 233-239, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Small-delay defects, pattern grading, pattern selection, ATPG |
16 | Yu Cao, Lawrence T. Clark |
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 658-663, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay, process variations, variability |
16 | Kazuhito Ito, Daisuke Suzuki |
A high-level synthesis method for simultaneous placement and scheduling considering data communication delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 149-154, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Soha Hassoun |
Critical path analysis using a dynamically bounded delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 260-265, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara |
A high resolution digital CMOS time-to-digital converter based on nested delay locked loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 537-540, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Yuji Kukimoto, Robert K. Brayton |
Hierarchical Functional Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 580-585, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | David Wessels, Jon C. Muzio |
The dangers of simplistic delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 61-69, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
critical paths, Delay models, path sensitization, circuit delays |
16 | Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Synthesis for testability techniques for asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1569-1577, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Andrzej Krasniewski, Leszek B. Wronski |
Coverage of Delay Faults: When 13% and 99% Mean the Same. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-1, First European Dependable Computing Conference, Berlin, Germany, October 4-6, 1994, Proceedings, pp. 178-195, 1994, Springer, 3-540-58426-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Kye S. Hedlund |
Electrical optimization of PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 681-687, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 49-54, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
15 | Vishal Khandelwal, Ankur Srivastava 0001 |
A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(2), pp. 206-215, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Vishal Khandelwal, Ankur Srivastava 0001 |
A general framework for accurate statistical timing analysis considering correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 89-94, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
correlation, variability, statistical timing |
15 | Sachin S. Sapatnekar, Rahul B. Deokar |
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10), pp. 1237-1248, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis |
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(5), pp. 962-972, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Walter Schneider |
Statistical gate-delay modeling with copulas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 107, pp. 104938, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 39th IEEE VLSI Test Symposium, VTS 2021, San Diego, CA, USA, April 25-28, 2021, pp. 1-7, 2021, IEEE, 978-1-6654-1949-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Peng Cao 0002, Zhiyuan Liu 0011, Jingjing Guo, Jiangping Wu |
An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 171515-171524, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Paolo Paletti, Mina Asghari Heidarlou, Karla González-Serrano, Cristobal Alessandri, Alan C. Seabaugh |
Steep Subthreshold Swing Originating from Gate Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2019, Ann Arbor, MI, USA, June 23-26, 2019, pp. 53-54, 2019, IEEE, 978-1-7281-2111-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
14 | Taizhi Liu, Chang-Chih Chen, Linda Milor |
Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 6(2), pp. 219-232, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Asad Ali Nawaz, Jubaid Abdul Qayyum, Ahmet Cagri Ulusoy, John D. Cressler, Wibo D. Van Noort |
A new figure-of-merit for CML gate delay estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WiSNet ![In: IEEE Topical Conference on Wireless Sensors and Sensor Networks, WiSNet 2018, Anaheim, CA, USA, January 14-17, 2018, pp. 73-76, 2018, IEEE, 978-1-5386-1286-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
14 | Assia El-Hadbi, Abdelkarim Cherkaoui, Oussama Elissati, Jean Simatic, Laurent Fesquet |
On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, June 25-28, 2017, pp. 305-308, 2017, IEEE, 978-1-5090-4991-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 9, pp. 13-20, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
14 | Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda |
An effective ATPG flow for Gate Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-6, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Bishnu Prasad Das, Hidetoshi Onodera |
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 61-II(3), pp. 183-187, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Steven Bielby, Gordon W. Roberts |
Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014, Toronto, ON, Canada, May 4-7, 2014, pp. 1-5, 2014, IEEE, 978-1-4799-3099-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Kenichi Shinkai, Masanori Hashimoto, Takao Onoye |
A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 46(4), pp. 345-358, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Donkyu Baek, Insup Shin, Youngsoo Shin |
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(8), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Prasanjeet Das, Sandeep K. Gupta 0001 |
Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 227-234, 2013, IEEE Computer Society, 978-1-4799-2987-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
14 | Suchismita Roy, P. P. Chakrabarti 0001, Pallab Dasgupta |
SAT based timing analysis for fixed and rise/fall gate delay models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 45(4), pp. 357-364, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai |
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(12), pp. 918-921, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Donkyu Baek, Insup Shin, Youngsoo Shin |
Gate delay modeling for static timing analysis of body-biased circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: IEEE International Conference on IC Design & Technology, ICICDT 2012, Austin, TX, USA, May 30 - June 1, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-0146-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Ali Arabi M. Shahi, Payman Zarkesh-Ha |
Prediction of gate delay variation for CNFET under CNT density variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, pp. 140-145, 2012, IEEE Computer Society, 978-1-4673-3043-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
14 | Chin-Hsin Lin, Marek Syrzycki |
Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. ![In: Circuits Syst. 2(4), pp. 365-371, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto |
Gate Delay Estimation in STA under Dynamic Power Supply Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12), pp. 2447-2455, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas |
Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 50(9-11), pp. 1223-1229, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto |
Gate delay estimation in STA under dynamic power supply noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 775-780, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita |
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, pp. 476-477, 2010, IEEE, 978-1-4244-6033-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Mingzhi Gao, Zuochang Ye, Yao Peng 0003, Yan Wang 0023, Zhiping Yu |
A comprehensive model for gate delay under process variation and different driving and loading conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 406-412, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
14 | Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera |
Statistical Gate Delay Model for Multiple Input Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12), pp. 3070-3078, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan |
Within-die gate delay variability measurement using re-configurable ring oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008, pp. 133-136, 2008, IEEE, 978-1-4244-2018-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Sangwoo Han, Yooseong Kim, Woosick Choi, Inho Shin, Youngdoo Choi |
A second-order gate delay modeling method with an efficient sensitivity analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1008-1011, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Y. Satish Kumar, Jun Li 0066, Claudio Talarico, Janet Meiling Wang |
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/0710.4634, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
14 | Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan |
Robust analytical gate delay modeling for low voltage circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 61-66, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Shahdad Irajpour, Sandeep K. Gupta 0001, Melvin A. Breuer |
Multiple tests for each gate delay fault: higher coverage and lower test application cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 9, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Soroush Abbaspour, Massoud Pedram |
Gate delay calculation considering the crosstalk capacitances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 852-857, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
A statistical gate delay model for intra-chip and inter-chip variabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 31-36, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis |
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 12(1), pp. 69-79, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
A New Gate Delay Model for Simultaneous Switching and Its Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 289-294, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Kaoru Kusafuka, Hidehisa Shimizu, Shinichi Kimura |
Driving method for gate-delay compensation of TFT/LCD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 42(3), pp. 459-466, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
14 | Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo Takamatsu |
Tests for small gate delay faults in combinational circuits and a test generation method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 28(6), pp. 68-76, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
14 | Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi |
CMOS Gate Delay Models for General RLC Loading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 224-229, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
14 | P. Cavallera, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996, pp. 79-87, 1996, IEEE Computer Society, 0-8186-7423-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Noriyoshi Itazaki, Kozo Kinoshita, Hisao Naitoh |
Test pattern generation for crosstalk faults considering the gate delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 26(7), pp. 24-33, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
14 | G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus |
Gate delay fault test generation for non-scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995, pp. 308-313, 1995, IEEE Computer Society, 0-8186-7039-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
14 | Arno Kunzmann, Frank Böhland |
Gate-Delay Fault Test with Conventional Scan-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 524-528, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
14 | Franco Fummi, Donatella Sciuto, Micaela Serra |
Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 17-19, 1994, Montréal, Quebec, Canada, Proceedings, pp. 254-262, 1994, IEEE Computer Society, 0-8186-6307-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
14 | Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage |
A Gate-Delay Model for high-Speed CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 576-580, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
14 | Pranav Ashar, Srinivas Devadas, Kurt Keutzer |
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 2(1), pp. 93-112, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
14 | Udo Mahlstedt |
DELTEST: Deterministic Test Generation for Gate-Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 972-980, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
14 | Daniel Brand, Vijay S. Iyengar |
Identification of Single Gate Delay Fault Redundancies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 24-28, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
14 | Weiwei Mao, Michael D. Ciletti |
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992, pp. 588-597, 1992, IEEE Computer Society, 0-7803-0760-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
14 | Pranav Ashar, Srinivas Devadas, Kurt Keutzer |
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991, pp. 887-896, 1991, IEEE Computer Society, 0-8186-9156-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
14 | Veronika Eisele, Bernhard Hoppe, Oliver Kiehl |
Transmission gate delay models for circuit optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 558-562, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
14 | Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li |
Static timing analysis for flexible TFT circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 799-802, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
flexible electronics, static timing analysis |
14 | Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava |
Computation of Waveform Sensitivity Using Geometric Transforms for SSTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 373-378, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Timing Library, Accuracy, SSTA |
14 | Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu |
Wire Retiming Problem With Net Topology Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1648-1660, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
An analytical model for negative bias temperature instability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 493-496, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Zhaojun Wo, Israel Koren |
Effective analytical delay model for transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 387-392, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Arun Krishnamachary, Jacob A. Abraham |
Test generation for resistive opens in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 65-70, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
resistive opens, delay testing, defect detection |
14 | Srinivas Devadas, Kurt Keutzer |
Synthesis of robust delay-fault-testable circuits: practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3), pp. 277-300, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
13 | Haining Fan, M. Anwar Hasan |
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 224-233, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
subquadratic space complexity multiplier, shifted polynomial basis, Finite field, coordinate transformation, Toeplitz matrix |
13 | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
Equivalent waveform propagation for static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 498-508, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
Equivalent Waveform Propagation for Static Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 169-175, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao |
A high-resolution and fast-conversion time-to-digital converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 37-40, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Matthias Ringe, Thomas Lindenkreuz, Erich Barke |
Static Timing Analysis Taking Crosstalk into Account. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 451-455, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev |
What is the cost of delay insensitivity? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 316-323, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Weiyu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
Test generation in VLSI circuits for crosstalk noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 641-650, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Takashi Enami, Masanori Hashimoto, Takashi Sato |
Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 420-425, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel |
A New Self-Checking Sum-Bit Duplicated Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1360-1361, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas |
Low power ATPG for path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 389-392, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults, PODEM |
11 | Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das |
Delay Fault Coverage Enhancement Using Variable Observation Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 131-146, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
statistical delay fault coverage, delay test observation times, delay fault testing |
11 | Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das |
Delay Fault Coverage Enhancement Using Multiple Test Observation Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 106-110, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Wayne Wei-Ming Dai |
Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 717-719, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Valid clock frequencies and their computation in wavepipelined circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), pp. 791-807, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
11 | Abhijit Chatterjee, Jacob A. Abraham |
RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 340-343, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
11 | Ankan K. Pramanick, Sudhakar M. Reddy |
On the fault coverage of delay fault detecting tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 334-338, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
11 | Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Timing analysis considering IR drop waveforms in power gating designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 532-537, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Malcolm Taylor, Chi-En Daniel Yin, Min Wu, Gang Qu 0001 |
A Hardware-Assisted Data Hiding Based Approach in Building High-Performance Trusted Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings, pp. 93-96, 2008, IEEE Computer Society, 978-1-4244-2401-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Shubhankar Basu, Ranga Vemuri |
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 291-298, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang |
IDDT ATPG Based on Ambiguous Delay Assignments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 400-405, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
IDDT testing, delay Assignments, stuck-open fault |
11 | Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr. |
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 77-89, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, MAC, multiplier |
11 | Hyunsik Im |
Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 13-18, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
?-power model, MOSFET modeling, Saturation current |
11 | Scott Woods, Giorgio Casinovi |
Gate-level simulation of digital circuits using multi-valued Boolean algebras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 413-419, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Gate-level logic simulation, mixed-mode simulation, boolean equations solution, multi-valued logic |