Search results for "gate-sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	John Lillis, Premal Buch	Table-Lookup Methods for Improved Performance-Driven Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	Bogdan G. Arsintescu, Edoardo Charbon, Enrico Malavasi, Umakanta Choudhury, William H. Kao	General AC Constraint Transformation for Analog ICs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	David S. Kung 0001	A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer Insertion for Noise and Delay Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	Hai Zhou 0001, D. F. Wong 0001	Global Routing with Crosstalk Constraints.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	Arun N. Lokanathan, Jay B. Brockman	Process Multi-Circuit Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
24	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Timing-Aware Power-Noise Reduction in Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang	Statistical circuit optimization considering device andinterconnect process variations.	SLIP	2007	DBLP DOI BibTeX RDF	gate and wire sizing, statistical optimization
24	Xiaoji Ye, Yaping Zhan, Peng Li 0001	Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.	DAC	2007	DBLP DOI BibTeX RDF
24	Youngmoon Choi, Earl E. Swartzlander Jr.	Parallel Prefix Adder Design with Matrix Representation.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
24	Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz	Cell replication and redundancy elimination during placement for cycle time optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
20	Hiran Tennakoon, Carl Sechen	Nonconvex Gate Delay Modeling and Delay Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
20	Ravi Varadarajan	Convergence of placement technology in physical synthesis: is placement really a point tool?	ISPD	2003	DBLP DOI BibTeX RDF
20	Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu 0001, Longxing Shi	Learning-driven Physically-aware Large-scale Circuit Gate Sizing.	CoRR	2024	DBLP DOI BibTeX RDF
20	Dimitrios Mangiras, David G. Chinnery, Giorgos Dimitrakopoulos	Task-Based Parallel Programming for Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
20	Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan	Geometric Programming Approach to Glitch Minimization via Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
20	Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin 0001, Uday Mallappa	DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
20	Junyu Jiang	Optimized Gate Sizing for Improved Performance and Power Efficiency in Adder Circuits.	ICITEE	2023	DBLP DOI BibTeX RDF
20	Phuoc Pham, Jaeyong Chung	AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing.	DAC	2023	DBLP DOI BibTeX RDF
20	David G. Chinnery, Ankur Sharma 0001	Integrating LR Gate Sizing in an Industrial Place-and-Route Flow.	ISPD	2022	DBLP DOI BibTeX RDF
20	Xinyi Zhou 0010, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang 0034, Jianye Hao, Guangyong Chen, Pheng-Ann Heng	Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration.	ICCAD	2022	DBLP DOI BibTeX RDF
20	Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren	Generative self-supervised learning for gate sizing: invited.	DAC	2022	DBLP DOI BibTeX RDF
20	Aiman H. El-Maleh, Ghashmi H. Bin Talib	Time redundancy and gate sizing soft error-tolerant based adder design.	Integr.	2021	DBLP DOI BibTeX RDF
20	Seyed Milad Ebrahimipour, Behnam Ghavami, Mohsen Raji	A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
20	Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim	RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning.	DAC	2021	DBLP DOI BibTeX RDF
20	Dimitrios Mangiras, Giorgos Dimitrakopoulos	Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment.	MOCAST	2021	DBLP DOI BibTeX RDF
20	Ankur Sharma 0001, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu	Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
20	Juliano C. Zanelli, Carolina Metzler, Ricardo Augusto da Luz Reis	Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits.	LASCAS	2020	DBLP DOI BibTeX RDF
20	Mohsen Raji, M. Amin Sabet, Behnam Ghavami	Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme.	IEEE Access	2019	DBLP DOI BibTeX RDF
20	Behnam Ghavami, Mohsen Raji, Ramin Rasaizadi, Mashaallah Mashinchi	Process variation-aware gate sizing with fuzzy geometric programming.	Comput. Electr. Eng.	2019	DBLP DOI BibTeX RDF
20	Andres F. Gomez, Víctor H. Champac	An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
20	Henrique Placido, Ricardo Reis 0001	Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm.	ISVLSI	2019	DBLP DOI BibTeX RDF
20	Ankur Sharma 0001, David G. Chinnery, Chris Chu	Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach.	ISPD	2019	DBLP DOI BibTeX RDF
20	Patanjali SLPSK, Prasanna Karthik Vairam, Chester Rebeiro, V. Kamakoti 0001	Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection.	ICCAD	2019	DBLP DOI BibTeX RDF
20	Siad Daboul, Nicolai Hähnle, Stephan Held, Ulrike Schorr	Provably Fast and Near-Optimum Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
20	Zahira Perez, Hector Villacorta, Víctor H. Champac	An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
20	Xuebing Cao, Liyi Xiao, Linzhe Li, Jie Li 0030, Jiaqiang Li, Jinxiang Wang 0001	Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm.	IOLTS	2018	DBLP DOI BibTeX RDF
20	Andres F. Gomez, Roberto Gómez 0001, Víctor H. Champac	A metric-guided gate-sizing methodology for aging guardband reduction.	LATS	2018	DBLP DOI BibTeX RDF
20	M. Amin Sabet, Behnam Ghavami, Mohsen Raji	A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing.	IEEE Trans. Reliab.	2017	DBLP DOI BibTeX RDF
20	Mohsen Raji, Behnam Ghavami	Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
20	Ankur Sharma 0001, David G. Chinnery, Shrirang Dhamdhere, Chris Chu	Rapid gate sizing with fewer iterations of Lagrangian Relaxation.	ICCAD	2017	DBLP DOI BibTeX RDF
20	Vijay Sundararajan	Gate Sizing.	Encyclopedia of Algorithms	2016	DBLP DOI BibTeX RDF
20	Subhendu Roy, Derong Liu 0002, Jagmohan Singh, Junhyung Um, David Z. Pan	OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
20	Sangmin Kim, Seokhyeong Kang, Youngsoo Shin	Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
20	Ramprasath S 0001, Vinita Vasudevan	Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
20	Gang Wu 0002, Chris C. N. Chu	Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits.	DATE	2016	DBLP BibTeX RDF
20	Jeong-Won Kim, Deok Keun Oh, Juho Kim	Performance optimization in FinFET-based circuit using TILOS-like gate sizing.	ISIC	2016	DBLP DOI BibTeX RDF
20	Tony Casagrande, Nagarajan Ranganathan	GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games.	DATE	2015	DBLP BibTeX RDF
20	Gang Wu 0002, Ankur Sharma 0001, Chris C. N. Chu	Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation.	ASYNC	2015	DBLP DOI BibTeX RDF
20	Tiago Reimann, Cliff C. N. Sze, Ricardo Reis 0001	Gate sizing and threshold voltage assignment for high performance microprocessor designs.	ASP-DAC	2015	DBLP DOI BibTeX RDF
20	Ankur Sharma 0001, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu	Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading.	ICCAD	2015	DBLP DOI BibTeX RDF
20	Jiani Xie, C. Y. Roger Chen	Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
20	Srinath R. Naidu	Geometric Programming Formulation for Gate Sizing with Pipelining Constraints.	VLSID	2015	DBLP DOI BibTeX RDF
20	Subhendu Roy, Derong Liu 0002, Junhyung Um, David Z. Pan	OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions.	DAC	2015	DBLP DOI BibTeX RDF
20	Amin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick	Optimal gate sizing using a self-tuning multi-objective framework.	Integr.	2014	DBLP DOI BibTeX RDF
20	Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis 0001	Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
20	Ing-Chao Lin, Shun-Ming Syu, Tsung-Yi Ho	NBTI tolerance and leakage reduction using gate sizing.	ACM J. Emerg. Technol. Comput. Syst.	2014	DBLP DOI BibTeX RDF
20	Vinicius S. Livramento, Chrystian Guth, José Luís Almada Güntzel, Marcelo O. Johann	A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation.	ACM Trans. Design Autom. Electr. Syst.	2014	DBLP DOI BibTeX RDF
20	Azam Beg	Automating the CMOS Gate Sizing for Reduced Power/Energy.	FIT	2014	DBLP DOI BibTeX RDF
20	Andrew B. Kahng, Hyein Lee 0001	Minimum implant area-aware gate sizing and placement.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
20	Subhendu Roy, David Z. Pan	Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown.	VLSID	2014	DBLP DOI BibTeX RDF
20	Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis 0001	Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.	ISVLSI	2013	DBLP DOI BibTeX RDF
20	Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak	Gate Sizing Under Uncertainty.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
20	Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann	Fast and efficient lagrangian relaxation-based discrete gate sizing.	DATE	2013	DBLP DOI BibTeX RDF
20	Andrew B. Kahng, Seokhyeong Kang, Hyein Lee 0001, Igor L. Markov, Pankit Thapar	High-performance gate sizing with a signoff timer.	ICCAD	2013	DBLP DOI BibTeX RDF
20	Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis 0001	Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.	ISCAS	2013	DBLP DOI BibTeX RDF
20	Amin Farshidi, Logan M. Rakai, Laleh Behjat, David T. Westwick	A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
20	Mohsen Jafari, Mohsen Imani, Morteza Fathipour, Nader Sehatbakhsh	Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing.	DTIS	2013	DBLP DOI BibTeX RDF
20	John Lee 0002, Puneet Gupta 0001	Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment.	Found. Trends Electron. Des. Autom.	2012	DBLP DOI BibTeX RDF
20	Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu	Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
20	Bing Shi, Yufu Zhang, Ankur Srivastava 0001	Accelerating Gate Sizing Using Graphics Processing Units.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
20	John Lee 0002, Puneet Gupta 0001	ECO cost measurement and incremental gate sizing for late process changes.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
20	Morteza Nabavi, Maitham Shams	A gate sizing and transistor fingering strategy for subthreshold CMOS circuits.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
20	Vinicius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann	Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization.	ICECS	2012	DBLP DOI BibTeX RDF
20	Andrew B. Kahng, Seokhyeong Kang	Construction of realistic gate sizing benchmarks with known optimal solutions.	ISPD	2012	DBLP DOI BibTeX RDF
20	Gregory Shklover, Ben Emanuel	Simultaneous clock and data gate sizing algorithm with common global objective.	ISPD	2012	DBLP DOI BibTeX RDF
20	Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov	Sensitivity-guided metaheuristics for accurate discrete gate sizing.	ICCAD	2012	DBLP DOI BibTeX RDF
20	Yoni Aizik, Avinoam Kolodny	Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints.	VLSI Design	2011	DBLP DOI BibTeX RDF
20	Sanghamitra Roy, Koushik Chakraborty	Exploiting dynamic micro-architecture usage in gate sizing.	Microprocess. Microsystems	2011	DBLP DOI BibTeX RDF
20	Huan Ren, Shantanu Dutt	Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous Vdd, Vth Assignments, Gate Sizing, and Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
20	Chen Liao, Shiyan Hu	Approximation scheme for restricted discrete gate sizing targeting delay minimization.	J. Comb. Optim.	2011	DBLP DOI BibTeX RDF
20	Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija	A Quick Method for Energy Optimized Gate Sizing of Digital Circuits.	PATMOS	2011	DBLP DOI BibTeX RDF
20	Shuzhe Zhou, Hailong Yao, Qiang Zhou 0001, Yici Cai	Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.	ISVLSI	2011	DBLP DOI BibTeX RDF
20	Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis 0001	Gate Sizing Minimizing Delay and Area.	ISVLSI	2011	DBLP DOI BibTeX RDF
20	Abhishek A. Sinkar, Nam Sung Kim	AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors.	ASP-DAC	2011	DBLP DOI BibTeX RDF
20	Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu	Gate sizing and device technology selection algorithms for high-performance industrial designs.	ICCAD	2011	DBLP DOI BibTeX RDF
20	Junjun Gu, Gang Qu 0001, Lin Yuan, Cheng Zhuo	Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization.	ICCAD	2011	DBLP DOI BibTeX RDF
20	Jason Cong, John Lee 0002, Guojie Luo	A unified optimization framework for simultaneous gate sizing and placement under density constraints.	ISCAS	2011	DBLP DOI BibTeX RDF
20	Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz	A gate sizing method for glitch power reduction.	SoCC	2011	DBLP DOI BibTeX RDF
20	Yifang Liu, Jiang Hu	A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
20	S. Saqib Khursheed, Bashir M. Al-Hashimi, Krishnendu Chakrabarty, Peter Harrod	Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
20	Shantanu Dutt, Huan Ren	Timing yield optimization via discrete gate sizing using globally-informed delay PDFs.	ICCAD	2010	DBLP DOI BibTeX RDF
20	John Lee 0002, Puneet Gupta 0001	Incremental gate sizing for late process changes.	ICCD	2010	DBLP DOI BibTeX RDF
20	Sanghamitra Roy, Koushik Chakraborty	Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization.	ICCD	2010	DBLP DOI BibTeX RDF
20	Jin Sun 0006, Janet Meiling Wang	Robust gate sizing by Uncertainty Second Order Cone.	ISQED	2010	DBLP DOI BibTeX RDF
20	Shiyan Hu, Mahesh Ketkar, Jiang Hu	Gate Sizing for Cell-Library-Based Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
20	Jia Wang 0003, Debasish Das, Hai Zhou 0001	Gate Sizing by Lagrangian Relaxation Revisited.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
20	Stephan Held	Gate sizing for large cell-based designs.	DATE	2009	DBLP DOI BibTeX RDF
20	S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod	Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.	DATE	2009	DBLP DOI BibTeX RDF
20	Vijay Sundararajan	Gate Sizing.	Encyclopedia of Algorithms	2008	DBLP DOI BibTeX RDF