Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Brock J. LaMeres, Sunil P. Khatri |
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Hao Yu 0001, Lei He 0001 |
A provably passive and cost-efficient model for inductive interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam |
A closed-form delay formula for on-chip RLC interconnects in current-mode signaling. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Mikhail Popovich, Eby G. Friedman |
Noise coupling in multi-voltage power distribution systems with decoupling capacitors. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Andrey V. Mezhiba, Eby G. Friedman |
Impedance characteristics of power distribution grids in nanoscale integrated circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Subhash Chander Rustagi, Chun-Geik Tan |
Equivalent circuit models for stacked spiral inductors in deep submicron CMOS technology. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Michael D. Powell, T. N. Vijaykumar |
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. |
ISCA |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White 0001 |
Managing on-chip inductive effects. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Karel Hajek, Z. Sedlacek, B. Sviezeny |
New circuits for realization of the 1st and 2nd order all-pass LC filters with a better technological feasibility. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Repeater insertion in tree structured inductive interconnect. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Yehea I. Ismail, Eby G. Friedman |
Repeater insertion in RLC lines for minimum propagation delay. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto |
QFP wiring problem-introduction and analytical considerations. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Mark A. Johnson, Paul Cote, Krystyna Truszkowska |
Determining the electrical gradients of electromagnetic launchers using the transmission line model. |
SpringSim (3) |
2007 |
DBLP BibTeX RDF |
inductance gradient, railgun, resistance gradient, transmission line |
29 | Yehia Massoud, Arthur Nieuwoudt |
Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits. |
ACM J. Emerg. Technol. Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
nanotube bundle, interconnect, inductance, Carbon nanotube, resistance |
29 | Lakshmi Kalpana Vakati, Janet Meiling Wang |
A new multi-ramp driver model with RLC interconnect load. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance |
29 | José R. Sendra, Javier del Pino, Antonio Hernández, Javier Hernández, Jaime Aguilera, Andrés Garcia-Alonso, Antonio Núñez |
Integrated Inductors Modeling and Tools for Automatic Selection and Layout Generation. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
parasitic effects, Eddy currents, magnetic flux, models, Integrated, inductance, resistance, spiral |
29 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
Lossless Transmission Lines, VLSI, Dynamic, Power, CMOS, Inductance, Short-circuit |
27 | Xiaopeng Ji, Long Ge, Xiaodong Han, Zhiquan Wang |
Wire-Sizing for Interconnect Performance Optimization Considering High Inductance Effects. |
ICNSC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury |
Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury |
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Rafael Escovar, Salvador Ortiz 0002, Roberto Suaya |
Mutual inductance between intentional inductors: closed form expressions. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal |
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
measurement, process variations, extraction, VLSI interconnects |
27 | Denis Deschacht, Alain Lopez |
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Chieki Mizuta, Jiro Iwai, Ken Machida, Tetsuro Kage, Hiroo Masuda |
Large-scale linear circuit simulation with an inversed inductance matrix. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
27 | M. A. Azadpour, T. S. Kalkur |
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Xiaoyan Wang, Pietro Andreani |
Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Yehia Massoud, Jacob White 0001 |
FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Shuzhou Fang, Zeyi Wang, Xianlong Hong |
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Chin Hsia, Ming-Hong Lai, Wu-Shiung Feng |
On-board effective inductance measurement. |
APCCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Chung Kei Thomas Chan, Christofer Toumazou |
Design of a class E power amplifier with non-linear transistor output capacitance and finite DC-feed inductance. |
ISCAS (1) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Renatas Jakushokas, Eby G. Friedman |
Line width optimization for interdigitated power/ground networks. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
interdigitated structure, optimal line width, power/ground network, power network |
21 | Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A fast band matching technique for impedance extraction. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin |
Equivalent rise time for resonance in power/ground noise estimation. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin |
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
signal integrity, mixed-signal circuits, Substrate coupling |
21 | Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson |
Noise Interaction Between Power Distribution Grids and Substrate. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
power supply, Substrate noise |
21 | Saihua Lin, Huazhong Yang, Rong Luo |
A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
21 | J. V. R. Ravindra, Srinivas Bala Mandalika |
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
RC, distributed RLC, interconnect, SPICE, circuit, RL |
21 | Dominic DiClemente, Fei Yuan 0005 |
Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
21 | You Zheng, Carlos E. Saavedra |
A Microwave OTA Using a Feedforward-Regulated Cascode Topology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas |
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling |
21 | Guoqing Chen, Eby G. Friedman |
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Junmou Zhang, Eby G. Friedman |
Crosstalk modeling for coupled RLC interconnects with application to shield insertion. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Mengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang |
An efficient algorithm for 3-D reluctance extraction considering high frequency effect. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Dongmin Park, SeongHwan Cho |
A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman |
On-die decoupling capacitance: frequency domain analysis of activity radius. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Mohamed Abdalla, George V. Eleftheriades, Khoman Phang |
A differential 0.13µm CMOS active inductor for high-frequency phase shifters. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Changhao Yan, Wenjian Yu, Zeyi Wang |
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Rong Jiang 0002, Wenyin Fu, Charlie Chung-Ping Chen |
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail |
Realizable reduction of interconnect circuits including self and mutual inductances. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Brock J. LaMeres, Sunil P. Khatri |
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Lucas Andrew Milner, Gabriel A. Rincón-Mora |
A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
active ripple filters, inductor multipliers, integrated inductors, power management |
21 | Brock J. LaMeres, Sunil P. Khatri |
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Guoqing Chen, Eby G. Friedman |
Low power repeaters driving RLC interconnects with delay and bandwidth constraints. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Hao Yu 0001, Lei He 0001 |
A sparsified vector potential equivalent circuit model for massively coupled interconnects. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Rafael Escovar, Roberto Suaya |
Optimal design of clock trees for multigigahertz applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
Equivalent waveform propagation for static timing analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Dipak Sitaram, Yu Zheng, Kenneth L. Shepard |
Full-chip, three-dimensional shapes-based RLC extraction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001 |
On-chip interconnect modeling by wire duplication. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Gregorio Cappuccino |
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
Equivalent Waveform Propagation for Static Timing Analysis. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Aleksandar Tasic, Wouter A. Serdijn, John R. Long |
Concept of transformer-feedback degeneration of low-noise amplifiers. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Andrey V. Mezhiba, Eby G. Friedman |
Electrical characteristics of multi-layer power distribution grids. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Byunghoo Jung, Anand Gopinath, Ramesh Harjani |
A novel noise optimization design technique for radio frequency low noise amplifiers. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Aleksandar Tasic, Wouter A. Serdijn, John R. Long |
Matching of low-noise amplifiers at high frequencies. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter |
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001 |
On-chip interconnect modeling by wire duplication. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Hui Zheng, Lawrence T. Pileggi |
Robust and passive model order reduction for circuits containing susceptance elements. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Andrey V. Mezhiba, Eby G. Friedman |
Scaling trends of on-chip Power distribution noise. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
technology scaling, power supply noise, power distribution |
21 | Guoan Zhong, Cheng-Kok Koh |
Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos |
Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Edgar F. M. Albuquerque, Manuel M. Silva |
Evaluation of substrate noise in CMOS and low-noise logic cells. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Apisak Worapishet, Suttipong Ninyawee |
Magnetically-coupled tuneable inductor for wide-band variable frequency oscillators. |
ISCAS (3) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Kenneth L. Shepard, Zhong Tian |
Return-limited inductances: a practical approach to on-chipinductance extraction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Mehdi M. Mechaik |
Electrical Characterization of Signal Routability and Performance. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Shiyou Zhao, Kaushik Roy 0001 |
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
switching noise, Ldi/dt noise, maximum switching current, IR voltage drop |
21 | Arani Sinha, Sandeep K. Gupta 0001, Melvin A. Breuer |
Validation and test generation for oscillatory noise in VLSI interconnects. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Michael W. Beattie, Lawrence T. Pileggi |
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
21 | N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone |
Taming Noise in Deep Submicron Digital Integrated Circuits (Panel). |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Andrew B. Kahng, Sudhakar Muddu |
An analytical delay model for RLC interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Taoyun Wang, Joseph R. Mautz, Roger F. Harrington |
The excess capacitance of a microstrip via in a dielectric substrate. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Taehoon Kim, Dongchul Kim, Jung-A Lee, Yungseon Eo |
Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
inductance effect, signal transient, crosstalk, transmission lines |
19 | Azad Naeemi, James D. Meindl |
Carbon nanotube interconnects. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
quantum wires, crosstalk, inductance, repeaters, molecular electronics, system analysis and design, system optimization |
19 | Hong He, Shi-jiu Jin, Dajian Zhang, Hui Meng, Xian-wei Zhu, Lu Tang |
Study of Suppression Techniques for Harmonic Current. |
ISDA (1) |
2006 |
DBLP DOI BibTeX RDF |
harmonic current, suppression techniques, insertion loss, effective magnetic permeability, inductance, inductor |
19 | Aishwarya Dubey |
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
P/G (Power/Ground) pad placement, current sink, package resistance, package inductance, IR drop |
19 | Kevin M. Lepak, Min Xu, Jun Chen 0008, Lei He 0001 |
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
VLSI physical design automation and on-chip inductance, net ordering, noise minimization, signal integrity, shielding |
19 | Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester |
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate |
19 | Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiaodong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi |
A fast simulation approach for inductive effects of VLSI interconnects. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
inductance, circuit simulation, VLSI interconnects |
19 | Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy 0001 |
An adaptive window-based susceptance extraction and its efficient implementation. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
interconnect, inductance, susceptance |
19 | Seung Hoon Choi, Kaushik Roy 0001 |
Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
Crosstalk, Inductance, Capacitance, Noise Analysis, Noise Margin, High Speed Circuit |
19 | Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001 |
Dynamic Noise Analysis with Capacitive and Inductive Coupling. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
capacitiance, dynamic noise margin, crosstalk, inductance, noise analysis, deep submicron, noise model |
19 | Brian W. Amick, Claude R. Gauthier, Dean Liu |
Macro-modeling concepts for the chip electrical interface. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
VLSI power distribution, analog and I/O power delivery, high speed microprocessor design, inductance |
19 | Phillip J. Restle, Albert E. Ruehli, Steven G. Walker |
Multi-GHz interconnect effects in microprocessors. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning |
19 | James D. Z. Ma, Lei He 0001 |
Simultaneous signal and power routing under K model. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design |
19 | Nathan Kalyanasundharam, Nital Patwa |
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance |
19 | Jason Cong, Cheng-Kok Koh |
Interconnect layout optimization under higher-order RLC model. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization |
19 | Cheng-Ping Wang, Chin-Long Wey |
Test Generation Of Analog Switched-Current Circuits. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults |
19 | Kenneth L. Shepard, Vinod Narayanan |
Noise in deep submicron digital design. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
static analysis, noise, crosstalk, inductance, CMOS circuits, noise margins |
16 | Junming Zeng, Jiayang Wu, Kerui Li, Yun Yang 0002, Shu Yuen Ron Hui |
Dynamic Monitoring of Battery Variables and Mutual Inductance for Primary-Side Control of a Wireless Charging System. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|