Search results for "legalization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Tao Lin 0007, Chris Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev	POLAR: placement based on novel rough legalization and refinement.	ICCAD	2013	DBLP DOI BibTeX RDF
23	Ulrich Brenner	VLSI legalization with minimum perturbation by iterative augmentation.	DATE	2012	DBLP DOI BibTeX RDF
23	Tsung-Yi Ho, Sheng-Hung Liu	Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization.	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
23	Tsung-Yi Ho, Sheng-Hung Liu	Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
23	Sheng Chou, Tsung-Yi Ho	OAL: An obstacle-aware legalization in standard cell placement with displacement minimization.	SoCC	2009	DBLP DOI BibTeX RDF
23	Ameya R. Agnihotri, Patrick H. Madden	Legalization and Detailed Placement.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
23	Chia-Yi Chang, Hung-Ming Chen	Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
23	Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez	A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation.	ISPD	1997	DBLP DOI BibTeX RDF
22	Ashutosh Chakraborty, Anurag Kumar 0002, David Z. Pan	RegPlace: a high quality open-source placement framework for structured ASICs.	DAC	2009	DBLP DOI BibTeX RDF	global placement, regular ASIC, FPGA, placement, legalization, structured ASIC
22	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack	Constraint-driven floorplan repair.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	constraints, Floorplanning, legalization
22	Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat	Floorplan repair using dynamic whitespace management.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	VLSI, placement, floorplanning, legalization
22	Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia	Diffusion-based placement migration.	DAC	2005	DBLP DOI BibTeX RDF	placement migration, diffusion, legalization
17	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
17	Bing Shi, Yufu Zhang, Ankur Srivastava 0001	Dynamic thermal management for single and multicore processors under soft thermal constraints.	ISLPED	2010	DBLP DOI BibTeX RDF	multi-core processor, dynamic thermal management
17	Kwangok Jeong, Andrew B. Kahng, Hailong Yao	Revisiting the linear programming framework for leakage power vs. performance optimization.	ISQED	2009	DBLP DOI BibTeX RDF
17	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	Handling complexities in modern large-scale mixed-size placement.	DAC	2009	DBLP DOI BibTeX RDF	incremental placement, mixed-size design, floorplanning
17	Ulrich Brenner, Markus Struzyna, Jens Vygen	BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
17	Herman Schmit, Amit Gupta, Radu Ciobanu	Placement challenges for structured ASICs.	ISPD	2008	DBLP DOI BibTeX RDF	field programmable gate arrays, placement, structured ASICs
17	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
17	M. Thenappan, Arasu T. Senthil, K. M. Sreekanth, Ramesh S. Guzar	An Overlap Removal Algorithm for Macrocell Placement in VLSI Layouts.	ICCTA	2007	DBLP DOI BibTeX RDF
17	Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou 0001, Xianlong Hong, Qiang Zhou 0001	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
17	Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001	Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.	SBCCI	2006	DBLP DOI BibTeX RDF	3d circuits, cell shifting, placement, quadratic placement
17	Lijuan Luo, Qiang Zhou 0001, Yici Cai, Xianlong Hong, Yibo Wang	A novel technique integrating buffer insertion into timing driven placement.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Tao Luo 0002, David Newmark, David Z. Pan	A new LP based incremental timing driven placement for high performance designs.	DAC	2006	DBLP DOI BibTeX RDF
17	Xin Yuan, Kevin W. McCullen, Fook-Luen Heng, Robert F. Walker, Jason Hibbeler, Robert J. Allen, Rani R. Narayan	Technology migration technique for designs with strong RET-driven layout restrictions.	ISPD	2005	DBLP DOI BibTeX RDF	RDR, RET-driven layout, restrictive design rules, technology migration
17	Andrew B. Kahng, Sherief Reda, Qinke Wang	APlace: a general analytic placement framework.	ISPD	2005	DBLP DOI BibTeX RDF	mixed size, congestion, multi-level, analytical placement
17	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris	Unified quadratic programming approach for mixed mode placement.	ISPD	2005	DBLP DOI BibTeX RDF	mixed mode placement, discrete cosine transformation, quadratic programming
17	Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar	Net weighting to reduce repeater counts during placement.	DAC	2005	DBLP DOI BibTeX RDF	interconnect, placement, scaling, buffering, repeater, force-directed placement, net weighting
17	Ameya R. Agnihotri, Mehmet Can Yildiz, Ateen Khatkhate, Ajita Mathur, Satoshi Ono, Patrick H. Madden	Fractional Cut: Improved Recursive Bisection Placement.	ICCAD	2003	DBLP DOI BibTeX RDF
17	Bill Halpin, Naresh Sehgal, C. Y. Roger Chen	Detailed Placement with Net Length Constraints.	IWSOC	2003	DBLP DOI BibTeX RDF
17	Fook-Luen Heng, Lars Liebmann, Jennifer Lund	Application of automated design migration to alternating phase shift mask design.	ISPD	2001	DBLP DOI BibTeX RDF	design migration, phase-shifting mask, resolution enchancement technique