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Found 120 publication records. Showing 120 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen |
An Adaptive Low-Power Control Scheme for On-Chip Network Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 113-118, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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13 | Mohammad Yavari, Omid Shoaei, Ali Afzali-Kusha |
A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 1045-1048, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong |
Design of a 10GHz clock distribution network using coupled standing-wave oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 682-687, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators |
13 | Vjekoslav Svilan, Masataka Matsui, James B. Burr |
Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 268-272, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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12 | Joonsung Bae, Joo-Young Kim 0001, Hoi-Jun Yoo |
A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2861-2864, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo |
Low-power network-on-chip for high-performance SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(2), pp. 148-160, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov |
A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 6138-6141, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Kanishka Lahiri, Anand Raghunathan |
Power analysis of system-level on-chip communication architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 236-241, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
system-on-chip, network-on-chip, low-power design, power analysis, communication architectures |
12 | Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson |
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1), pp. 50-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
12 | Ankireddy Nalamalpu, Wayne P. Burleson |
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 204-211, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
methodology, timing, interconnect, buffering |
12 | L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy |
Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 106-108, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power CMOS logic, low voltage logic circuits, manufacturing variations, mixed-swing CMOS logic |
10 | Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi |
8Gb/s capacitive low power and high speed 4-PWAM transceiver design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 33-38, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
pam, pulse amplitude modulation, pwam. low power, high performance, high speed, receiver, transceiver, capacitive, transmitter, pwm, pulse width modulation |
10 | Mohammad Reza Kakoee, Igor Loi, Luca Benini |
A new physical routing approach for robust bundled signaling on NoC links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 3-8, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing |
10 | George Michelogiannakis, James D. Balfour, William J. Dally |
Elastic-buffer flow control for on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 151-162, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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10 | Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi |
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 3-14, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models |
10 | Martin Saint-Laurent, Baker Mohammad, Paul Bassett |
A 65-nm pulsed latch with a single clocked transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 347-350, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking |
10 | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada |
On-chip 8GHz non-periodic high-swing noise detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 670-671, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Srinivasa R. Sridhara, Naresh R. Shanbhag |
Coding for system-on-chip networks: a unified framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 655-667, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Ivo Bolsens |
Challenges and Opportunities for FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 391-392, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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10 | Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi |
Energy efficient signaling in DSM CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 411-414, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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