Search results for "low-swing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen	An Adaptive Low-Power Control Scheme for On-Chip Network Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
13	Mohammad Yavari, Omid Shoaei, Ali Afzali-Kusha	A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25µm CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
13	Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong	Design of a 10GHz clock distribution network using coupled standing-wave oscillators.	DAC	2003	DBLP DOI BibTeX RDF	distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators
13	Vjekoslav Svilan, Masataka Matsui, James B. Burr	Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS.	ISLPED	2000	DBLP DOI BibTeX RDF
12	Joonsung Bae, Joo-Young Kim 0001, Hoi-Jun Yoo	A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects.	ISCAS	2008	DBLP DOI BibTeX RDF
12	Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	Low-power network-on-chip for high-performance SoC design.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov	A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
12	Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson	Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
12	Ankireddy Nalamalpu, Wayne P. Burleson	Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.	ISPD	2001	DBLP DOI BibTeX RDF	methodology, timing, interconnect, buffering
12	L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy	Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	low power CMOS logic, low voltage logic circuits, manufacturing variations, mixed-swing CMOS logic
10	Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi	8Gb/s capacitive low power and high speed 4-PWAM transceiver design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	pam, pulse amplitude modulation, pwam. low power, high performance, high speed, receiver, transceiver, capacitive, transmitter, pwm, pulse width modulation
10	Mohammad Reza Kakoee, Igor Loi, Luca Benini	A new physical routing approach for robust bundled signaling on NoC links.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing
10	George Michelogiannakis, James D. Balfour, William J. Dally	Elastic-buffer flow control for on-chip networks.	HPCA	2009	DBLP DOI BibTeX RDF
10	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
10	Martin Saint-Laurent, Baker Mohammad, Paul Bassett	A 65-nm pulsed latch with a single clocked transistor.	ISLPED	2007	DBLP DOI BibTeX RDF	low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
10	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	On-chip 8GHz non-periodic high-swing noise detector.	DATE	2006	DBLP DOI BibTeX RDF
10	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for system-on-chip networks: a unified framework.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Ivo Bolsens	Challenges and Opportunities for FPGA Platforms.	FPL	2002	DBLP DOI BibTeX RDF
10	Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi	Energy efficient signaling in DSM CMOS technology.	ISCAS (5)	2001	DBLP DOI BibTeX RDF