Search results for "netlist"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Erwei Wang, James J. Davis 0001, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference.	CoRR	2021	DBLP BibTeX RDF
21	Katie Liszewski, Tim McDonley, Josh Delozier, Andrew Elliott, Dylan Jones, Matthew Sutter, Adam G. Kimura	Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
21	Mahamuda Sultana, Ayan Chaudhuri, Diganta Sengupta, Debashis De, Atal Chaudhuri	Design of synchronous decimal counter using reversible Toffoli-Fredkin Netlist.	Innov. Syst. Softw. Eng.	2021	DBLP DOI BibTeX RDF
21	Hao Chen 0059, Mingjie Liu, Biying Xu, Keren Zhu 0001, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun 0001, David Z. Pan	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.	IEEE Des. Test	2021	DBLP DOI BibTeX RDF
21	Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang	Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator.	DATE	2021	DBLP DOI BibTeX RDF
21	Ali Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener	Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration.	ARC	2021	DBLP DOI BibTeX RDF
21	Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito	R-GCN Based Function Inference for Gate-level Netlist.	IPSJ Trans. Syst. LSI Des. Methodol.	2020	DBLP DOI BibTeX RDF
21	Grace Li Zhang, Bing Li 0005, Meng Li 0004, Bei Yu 0001, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann	TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
21	Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat	Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
21	Grace Li Zhang, Bing Li 0005, Meng Li 0004, Bei Yu 0001, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann	TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).	CoRR	2020	DBLP BibTeX RDF
21	Ahmet Turan Erozan, Michael Hefenbrock, Michael Beigl, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori	Reverse Engineering of Printed Electronics Circuits: From Imaging to Netlist Extraction.	IEEE Trans. Inf. Forensics Secur.	2020	DBLP DOI BibTeX RDF
21	Nils Albartus, Max Hoffmann 0001, Sebastian Temme, Leonid Azriel, Christof Paar	DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2020	DBLP DOI BibTeX RDF
21	Nils Albartus, Max Hoffmann 0001, Sebastian Temme, Leonid Azriel, Christof Paar	DANA - Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
21	Emmanouil Kalligeros, Nikolaos Karousos, Irene G. Karybali	Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist.	DATE	2020	DBLP DOI BibTeX RDF
21	Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.	DATE	2020	DBLP DOI BibTeX RDF
21	Yipei Yang, Jing Ye 0001, Yuan Cao 0003, Jiliang Zhang 0002, Xiaowei Li 0001, Huawei Li 0001, Yu Hu 0001	Survey: Hardware Trojan Detection for Netlist.	ATS	2020	DBLP DOI BibTeX RDF
21	Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David G. Chinnery, Giorgos Dimitrakopoulos	Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation.	ISPD	2020	DBLP DOI BibTeX RDF
21	Dallin Skouson, Andrew M. Keller, Michael J. Wirthlin	Netlist Analysis and Transformations Using SpyDrNet.	SciPy	2020	DBLP DOI BibTeX RDF
21	Shotaro Yamada, Shuichi Ichikawa	Netlist-based Measures for Hardware Obfuscation: A Preliminary Study.	CANDAR (Workshops)	2020	DBLP DOI BibTeX RDF
21	Rongliang Fu, Zhimin Zhang 0004, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun	Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
21	Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, David Z. Pan	ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist.	HOST	2020	DBLP DOI BibTeX RDF
21	Georgios Zervakis 0001, Konstantina Koliogeorgi, Dimitrios Anagnostos, Nikolaos Zompakis, Kostas Siozios	VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
21	Sebastian Wallat, Nils Albartus, Steffen Becker 0003, Max Hoffmann 0001, Maik Ender, Marc Fyrbiak, Adrian Drees, Sebastian Maaßen, Christof Paar	Highway to HAL: Open-Sourcing the First Extendable Gate-Level Netlist Reverse Engineering Framework.	CoRR	2019	DBLP BibTeX RDF
21	Abhrajit Sengupta, Ozgur Sinanoglu	CAS-Unlock: Unlocking CAS-Lock without Access to a Reverse-Engineered Netlist.	IACR Cryptol. ePrint Arch.	2019	DBLP BibTeX RDF
21	Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis	Netlist Optimization by Gate Merging.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
21	Chee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, Fawnizu Azmadi Hussin	Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection.	ATS	2019	DBLP DOI BibTeX RDF
21	Yonghwi Kwon 0002, Inhak Han, Youngsoo Shin	Clock Gating Synthesis of Netlist with Cyclic Logic Paths.	ICCAD	2019	DBLP DOI BibTeX RDF
21	Sebastian Wallat, Nils Albartus, Steffen Becker 0003, Max Hoffmann 0001, Maik Ender, Marc Fyrbiak, Adrian Drees, Sebastian Maaßen, Christof Paar	Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework.	CF	2019	DBLP DOI BibTeX RDF
21	Travis Meade, Kaveh Shamsi, Thao Le 0001, Jia Di, Shaojie Zhang, Yier Jin	The Old Frontier of Reverse Engineering: Netlist Partitioning.	J. Hardw. Syst. Secur.	2018	DBLP DOI BibTeX RDF
21	Yusuke Kimura, Amir Masoud Gharehbaghi, Masahiro Fujita	C Description Reconstruction Method from a Revised Netlist for ECO Support.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
21	Thorben Casper, David Duque, Sebastian Schöps, Herbert De Gersem	Automated Netlist Generation for 3D Electrothermal and Electromagnetic Field Problems.	CoRR	2018	DBLP BibTeX RDF
21	Grace Li Zhang, Bing Li 0005, Ulf Schlichtmann	Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.	ISVLSI	2018	DBLP DOI BibTeX RDF
21	Yonghwi Kwon 0002, Jinwook Jung, Inhak Han, Youngsoo Shin	Transient Clock Power Estimation of Pre-CTS Netlist.	ISCAS	2018	DBLP DOI BibTeX RDF
21	Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat	A machine learning framework to identify detailed routing short violations from a placed netlist.	DAC	2018	DBLP DOI BibTeX RDF
21	Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003	Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning.	Integr.	2017	DBLP DOI BibTeX RDF
21	Travis Meade, Shaojie Zhang, Yier Jin	IP protection through gate-level netlist security enhancement.	Integr.	2017	DBLP DOI BibTeX RDF
21	Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003	Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning.	CoRR	2017	DBLP BibTeX RDF
21	Hassan Salmani	COTD: Reference-Free Hardware Trojan Detection and Recovery Based on Controllability and Observability in Gate-Level Netlist.	IEEE Trans. Inf. Forensics Secur.	2017	DBLP DOI BibTeX RDF
21	Xin Xie, Yangyang Sun, Hongda Chen 0004, Yong Ding 0003	Hardware Trojans classification based on controllability and observability in gate-level netlist.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
21	Thao Le 0001, Jia Di	Golden reference matching for gate-level netlist functionality identification.	MWSCAS	2017	DBLP DOI BibTeX RDF
21	Christoph Jäschke, Ulla Herter, Claudia Wolkober, Carsten Schmitt, Christian G. Zoellin	Static netlist verification for IBM high-frequency processors using a tree-grammar.	DATE	2017	DBLP DOI BibTeX RDF
21	Sharareh Zamanzadeh, Ali Jahanian 0001	ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow.	ISC Int. J. Inf. Secur.	2016	DBLP DOI BibTeX RDF
21	Sharareh Zamanzadeh, Ali Jahanian 0001	Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
21	Khouloud Bouaziz, Sonda Chtourou, Zied Marrakchi, Abdulfattah Mohammad Obeid, Mohamed Abid	Rebuilding synthesized design hierarchy based on instances path names of flattened netlist.	IDT	2016	DBLP DOI BibTeX RDF
21	Jaya Dofe, Yuejun Zhang, Qiaoyan Yu	DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation.	ISVLSI	2016	DBLP DOI BibTeX RDF
21	Travis Meade, Shaojie Zhang, Yier Jin	Netlist reverse engineering for high-level functionality reconstruction.	ASP-DAC	2016	DBLP DOI BibTeX RDF
21	Travis Meade, Yier Jin, Mark M. Tehranipoor, Shaojie Zhang	Gate-level netlist reverse engineering for hardware security: Control logic register identification.	ISCAS	2016	DBLP DOI BibTeX RDF
21	Konstantinos Maragos 0001, Kostas Siozios, Dimitrios Soudris	An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs.	IEEE Embed. Syst. Lett.	2015	DBLP DOI BibTeX RDF
21	Christian Fibich, Peter Rössler, Stefan Tauner, Herbert Taucher, Martin Matschnig	A netlist-level fault-injection tool for FPGAs.	Elektrotech. Informationstechnik	2015	DBLP DOI BibTeX RDF
21	Giovanni Beltrame	Triple Modular Redundancy verification via heuristic netlist analysis.	PeerJ Comput. Sci.	2015	DBLP DOI BibTeX RDF
21	Dan Niu, Yasuaki Inoue, Zhou Jin 0001, Xiao Wu	A netlist implementation of the Newton fixed-point homotopy method for MOS transistor circuits.	MWSCAS	2015	DBLP DOI BibTeX RDF
21	Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey	Virtual logic netlist: Enabling efficient RTL analysis.	ISQED	2015	DBLP DOI BibTeX RDF
21	Edward Tashjian, Azadeh Davoodi	On using control signals for word-level identification in a gate-level netlist.	DAC	2015	DBLP DOI BibTeX RDF
21	Jiazhao Xu, Mark Williams, Hari Mony, Jason Baumgartner	Scalable reachability analysis via automated dynamic netlist-based hint generation.	Formal Methods Syst. Des.	2014	DBLP DOI BibTeX RDF
21	Bernhard Schmidt, Daniel Ziener, Jürgen Teich	An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
21	Bernhard Schmidt, Daniel Ziener, Jürgen Teich	Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.	IPDPS Workshops	2014	DBLP DOI BibTeX RDF
21	Tamir Heyman, Dan Smith, Yogesh Mahajan, Lance Leong, Husam Abu-Haimed	Dominant Controllability Check Using QBF-Solver and Netlist Optimizer.	SAT	2014	DBLP DOI BibTeX RDF
21	Emna Amouri, Habib Mehrez, Zied Marrakchi	Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA.	Int. J. Reconfigurable Comput.	2013	DBLP DOI BibTeX RDF
21	Rizwan A. Ashraf, Ronald F. DeMara	Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms.	IEEE Trans. Computers	2013	DBLP DOI BibTeX RDF
21	Sharareh Zamanzadeh, Ali Jahanian 0001	Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
21	Nabil Kerkiz, Amr Elchouemi	Netlist partitioning method suitable for adaptive computing systems.	ICECS	2013	DBLP DOI BibTeX RDF
21	Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez	Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist.	ARC	2013	DBLP DOI BibTeX RDF
21	Karim Baratli, Ahmed Lakhssassi, Yves Blaquière, Yvon Savaria	A netlist pruning tool for an electronic system prototyping platform.	NEWCAS	2013	DBLP DOI BibTeX RDF
21	Sandeep Singh Gill, Rajeevan Chandel, Ashwani Kumar Chandel	Netlist bipartitioning using particle swarm optimisation technique.	Int. J. Artif. Intell. Soft Comput.	2012	DBLP DOI BibTeX RDF
21	Jason Xin Zheng, Miodrag Potkonjak	Securing netlist-level FPGA design through exploiting process variation and degradation.	FPGA	2012	DBLP DOI BibTeX RDF
21	Yiqiong Shi, Bah-Hwee Gwee, Ye Ren, Thet Khaing Phone, Chan Wai Ting	Extracting functional modules from flattened gate-level netlist.	ISCIT	2012	DBLP DOI BibTeX RDF
21	Jiazhao Xu, Mark Williams, Hari Mony, Jason Baumgartner	Enhanced reachability analysis via automated dynamic netlist-based hint generation.	FMCAD	2012	DBLP BibTeX RDF
21	Shuenn-Yuh Lee, Chih-Yuan Chen, Jia-Hua Hong, Rong-Guey Chang, Mark Po-Hung Lin	Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
21	Mohamed Badreddine, Yves Blaquière, Mounir Boukadoum	Machine-learning framework for automatic netlist creation.	ISCAS	2011	DBLP DOI BibTeX RDF
21	Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche	An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities.	IOLTS	2011	DBLP DOI BibTeX RDF
21	Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani	Quantum physical synthesis: Improving physical design by netlist modifications.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
21	Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche	Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation.	ICECS	2010	DBLP DOI BibTeX RDF
21	Yiqiong Shi, Chan Wai Ting, Bah-Hwee Gwee, Ye Ren	A highly efficient method for extracting FSMs from flattened gate-level netlist.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Suprio Das, Shamik Sural, Amit Patra	Resistance Estimation for Lateral Power Arrays Through Accurate Netlist Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez	Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA.	ICECS	2009	DBLP DOI BibTeX RDF
21	Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna	Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist.	EWDTS	2008	DBLP DOI BibTeX RDF
21	Moritz Schmid, Daniel Ziener, Jürgen Teich	Netlist-level IP protection by watermarking for LUT-based FPGAs.	FPT	2008	DBLP DOI BibTeX RDF
21	Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu	How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
21	Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji	Evolutionary algorithms for VLSI multi-objective netlist partitioning.	Eng. Appl. Artif. Intell.	2006	DBLP DOI BibTeX RDF
21	Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski	Generic netlist representation for system and PE level design exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	GNR, NISC, modeling, synthesis, system design, architecture description language, application-specific processor
21	David J. Walkey, Tom J. Smy, Dritan Celo, Tom W. MacElwee, Michael C. Maliepaard	Compact, netlist-based representation of thermal transient coupling using controlled sources.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
21	Shawki Areibi, Anthony Vannelli	Tabu Search: Implementation & Complexity Analysis for Netlist Partitioning.	Int. J. Comput. Their Appl.	2003	DBLP BibTeX RDF
21	Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji	Enhancing performance of iterative heuristics for VLSI netlist partitioning.	ICECS	2003	DBLP DOI BibTeX RDF
21	Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy	Synthesis of Scan Chains for Netlist Descriptions at RT-Level.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	scan synthesis, design for testability (DFT), register transfer level (RTL)
21	Shawki Areibi, Anthony Vannelli	Tabu Search: A Meta Heuristic for Netlist Partitioning.	VLSI Design	2000	DBLP DOI BibTeX RDF
21	Helena Krupnova, Gabriele Saucier	Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs.	DATE	1999	DBLP DOI BibTeX RDF
21	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning.	ALENEX	1999	DBLP DOI BibTeX RDF
21	Kwang-Su Seong, Chong-Min Kyung	CBLO: a clustering based linear ordering for netlist partitioning.	ASP-DAC	1997	DBLP DOI BibTeX RDF
21	Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes	Timing driven placement in interaction with netlist transformations.	ISPD	1997	DBLP DOI BibTeX RDF
21	Wray L. Buntine, Lixin Su, A. Richard Newton, Andrew Mayer	Adaptive methods for netlist partitioning.	ICCAD	1997	DBLP DOI BibTeX RDF	Fidducia-Matheysses algorithm, partitioning, stochastic optimization, placement and routing
21	Charles J. Alpert, Andrew B. Kahng	Recent directions in netlist partitioning: a survey.	Integr.	1995	DBLP DOI BibTeX RDF
21	Ulrike Ober, Manfred Glesner	Multiway netlist partitioning onto FPGA-based board architecture.	EURO-DAC	1995	DBLP DOI BibTeX RDF
21	Roman Kuznar, Franc Brglez, Baldomir Zajc	Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect.	DAC	1994	DBLP DOI BibTeX RDF
21	B. Naveen, K. S. Raghunathan	An Automatic Netlist-to-Schematic Generator.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
21	Charles J. Alpert, Andrew B. Kahng	Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning.	DAC	1993	DBLP DOI BibTeX RDF
21	Subindrao Singh Johal	Design interfaces for high-level synthesis : library modelling, netlist generation and visualisation.		1993	RDF
21	B. Naveen, A. Savargaonkar, K. S. Raghunathan	N2S: An Automatic Netlist to Schematic generator.	VLSI Design	1992	DBLP DOI BibTeX RDF
21	David A. Zein, Oliver P. Engel, Gary S. Ditlow	HLSIM - A New Hierarchical Logic Simulator and Netlist Converter.	DAC	1992	DBLP BibTeX RDF
21	Georg Peltz	An Interpreter for General Netlist Design Rule Checking.	DAC	1992	DBLP BibTeX RDF
21	Pradeep Batra, David Cooke	Hcompare: A Hierarchical Netlist Comparison Program.	DAC	1992	DBLP BibTeX RDF