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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1997 occurrences of 975 keywords
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Results
Found 1754 publication records. Showing 1754 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
35 | Smita Bakshi, Daniel Gajski |
A Scheduling and Pipelining Algorithm for Hardware/Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 10th International Symposium on System Synthesis, ISSS '97, Antwerp, Belgium, September 17-19, 1997., pp. 113-, 1997, ACM / IEEE Computer Society, 0-8186-7949-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
throughput-constrained, scheduling, pipelining, high-performance, Hardware/software codesign |
35 | Peter Pfahler, Georg Piepenbrock |
A Comparison of Modulo Scheduling Techniques for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 18-32, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors |
35 | Fermín Sánchez |
Time-Constrained Loop Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 592, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
timing and resource contraints, register optimization, scheduling, loop pipelining |
35 | Bogong Su, Stanley Habib, Wei Zhao, Jian Wang 0046, Youfeng Wu |
A study of pointer aliasing for software pipelining using run-time disambiguation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 112-117, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
compensation code, pointer aliasing, rerollability, run-time disambiguation, software pipelining |
35 | B. Ramakrishna Rau |
Iterative modulo scheduling: an algorithm for software pipelining loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 63-74, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
software pipelining, instruction scheduling, modulo scheduling, loop scheduling |
35 | Hongbo Rong, Alban Douillet, Guang R. Gao |
Register allocation for software pipelined multi-dimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, Chicago, IL, USA, June 12-15, 2005, pp. 154-167, 2005, ACM, 1-59593-056-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining |
35 | Pradeep Kumar Mishra |
Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 328-342, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Jacobian coordinates, pipelining, Elliptic curve cryptosystems, scalar multiplication |
35 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu |
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 977-994, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing |
35 | Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger |
An ASIC Implementation of the AES SBoxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2002, The Cryptographer's Track at the RSA Conference, 2002, San Jose, CA, USA, February 18-22, 2002, Proceedings, pp. 67-78, 2002, Springer, 3-540-43224-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic |
35 | G. X. Tyson, M. Smelyanskyi, Edward S. Davidson |
Evaluating the Use of Register Queues in Software Pipelined Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(8), pp. 769-783, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW |
33 | Ramaswamy Govindarajan, Guang R. Gao, Palash Desai |
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(3), pp. 207-229, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
buffer minimization, Digital Signal Processing (DSP) computation, Multi-Rate Software Pipelining, Regular Stream Flow Graphs, software pipelining, dataflow graphs |
30 | Hirochika Asai |
Deep Pipelining: Efficient Pipelining of Network Function Chains with Coroutines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NetSoft ![In: 5th IEEE Conference on Network Softwarization, NetSoft 2019, Paris, France, June 24-28, 2019, pp. 324-332, 2019, IEEE, 978-1-5386-9376-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
30 | Priyankar Talukdar |
On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
30 | Manish Garg |
High performance pipelining method for static circuits using heterogeneous pipelining elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 185-188, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Yoshiyuki Yamashita, Masato Tsuru |
Implementing Fast Packet Filters by Software Pipelining on x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 420-435, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo |
Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 358-365, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee |
A software pipelining algorithm in high-level synthesis for FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 297-302, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu |
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(2), pp. 127-135, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
data transition detection, CLA, pipeline, power-aware, ANT |
30 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
High-throughput interconnect wave-pipelining for global communication in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 258, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August |
Parallel-stage decoupled software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 114-123, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism |
30 | Timothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms |
Correct-by-construction microarchitectural pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 434-441, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Jie Shao, Ning Ye, Xiao-Yan Zhang |
An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (4) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 4: Embedded Programming / Database Technology / Neural Networks and Applications / Other Applications, December 12-14, 2008, Wuhan, China, pp. 50-53, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Jingye Xu, Abinash Roy, Masud H. Chowdhury |
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1218-1223, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Colin J. Ihrig, Justin Stander, Alex K. Jones |
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Ming Su, Lili Zhou, C.-J. Richard Shi |
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 636-643, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | A. Neslin Ismailoglu, Murat Askar |
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3259-3262, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Jingye Xu, Abinash Roy, Masud H. Chowdhury |
Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3716-3719, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu |
Exploiting Software Pipelining for Network-on-Chip architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 295-302, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Kishan Chand Gupta, Pradeep Kumar Mishra, Pinakpani Pal |
A General Methodology for Pipelining the Point Multiplication Operation in Curve Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACNS ![In: Applied Cryptography and Network Security, 4th International Conference, ACNS 2006, Singapore, June 6-9, 2006, Proceedings, pp. 405-420, 2006, 3-540-34703-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Alban Douillet, Hongbo Rong, Guang R. Gao |
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 311-322, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Dongwuk Kyoung, Keechul Jung |
Fully-Pipelining Hardware Implementation of Neural Network for Text-Based Images Retrieval. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part III, pp. 1350-1356, 2006, Springer, 3-540-34482-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Jinhui Xu 0002, Guiming Wu, Yong Dou, Yazhuo Dong |
Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 567-573, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Ke Zhou 0001, Zhongying Niu |
Decease I/O Mean Response Time Using Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (1) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 1, pp. 332-337, 2006, IEEE Computer Society, 0-7695-2581-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu |
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 319-330, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Jahangir Hasan, T. N. Vijaykumar |
Dynamic pipelining: making IP-lookup truly scalable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2005 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications, Philadelphia, Pennsylvania, USA, August 22-26, 2005, pp. 205-216, 2005, ACM, 1-59593-009-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scalable, pipelined, IP-lookup, longest prefix matching, tries |
30 | Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen |
Pipelining technique for energy-aware datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1218-1221, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | João M. P. Cardoso |
Self-loop Pipelining and Reconfigurable Dataflow Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 234-243, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Steven J. E. Wilton, Su-Shin Ang, Wayne Luk |
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 719-728, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | V. Seth, Min Zhao 0001, Jiang Hu |
Exploiting level sensitive latches in wire pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 283-290, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Mario R. Casu, Luca Macchiarulo |
On-Chip Transparent Wire Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 160-167, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1395-1415, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Greg Snider |
Performance-constrained pipelining of software loops onto reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 177-186, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Matthias Korch, Thomas Rauber, Gudula Rünger |
Pipelining for Locality Improvement in RK Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 724-734, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Raya Leviathan, Amir Pnueli |
Validating software pipelining optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 280-287, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimization, verification, compilers, pipeline processors, translation validation |
30 | Shing Tenqchen, Ji-Horn Chang, Wu-Shiung Feng, Bor-Sheng Jeng |
Pipelining Extended Givens Rotation RLS Adaptive Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 466-473, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Nilesh N. Dalvi, Sumit K. Sanghai, Prasan Roy, S. Sudarshan 0001 |
Pipelining in Multi-Query Optimization. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODS ![In: Proceedings of the Twentieth ACM SIGACT-SIGMOD-SIGART Symposium on Principles of Database Systems, May 21-23, 2001, Santa Barbara, California, USA, 2001, ACM, 1-58113-361-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Michael T. Niemier, Peter M. Kogge |
Exploring and exploiting wire-level pipelining in emerging technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 166-177, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | E. Christopher Lewis, Lawrence Snyder |
Pipelining Wavefront Computations: Experiences and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 261-268, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Cagdas Akturan, Margarida F. Jacome |
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 34-40, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Martin Weichert |
Pipelining the Molecule Soup: A Plumber's Approach to Gamma. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COORDINATION ![In: Coordination Languages and Models, Third International Conference, COORDINATION '99, Amsterdam, The Netherlands, April 26-28, 1999, Proceedings, pp. 69-84, 1999, Springer, 3-540-65836-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Jason Cong, Chang Wu |
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 644-649, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Josep Llosa, Mateo Valero, Eduard Ayguadé |
Heuristics for Register-Constrained Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 250-261, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | John C. Ruttenberg, Guang R. Gao, Woody Lichtenstein, Artour Stoutchinin |
Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), Philadephia, Pennsylvania, USA, May 21-24, 1996, pp. 1-11, 1996, ACM, 0-89791-795-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 640-651, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
30 | Qi Ning, Guang R. Gao |
A Novel Framework of Register Allocation for Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Twentieth Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Charleston, South Carolina, USA, January 1993, pp. 29-42, 1993, ACM Press, 0-89791-560-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong |
An Efficient Scheme for Fine-Grain Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: CONPAR 90 - VAPP IV, Joint International Conference on Vector and Parallel Processing, Zurich, Switzerland, September 10-13, 1990, Proceedings, pp. 709-720, 1990, Springer, 3-540-53065-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
30 | Bogong Su, Shiyuan Ding, Jian Wang 0046, Jinshi Xia |
GURPR - a method for global software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 88-96, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
30 | Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur |
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 163-168, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani |
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 473-478, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Eric L. Hill, Mikko H. Lipasti |
Stall cycle redistribution in a transparent fetch pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 31-36, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pipeline gating, microarchitecture, dynamic power, instruction fetch |
30 | Marco Macchetti, Luigi Dadda |
Quasi-Pipelined Hash Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 222-229, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 |
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 640-645, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
piecewise-linear, performance, pipeline, interconnect, floorplanning |
30 | Jos Sulistyo, Dong Sam Ha |
5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 117-120, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Glenn Reinman, Brad Calder, Todd M. Austin |
Optimizations Enabled by a Decoupled Front-End Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 338-355, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fetch architectures, branch prediction, Decoupled architectures, instruction prefetching |
30 | Ahmed F. Shalash, Keshab K. Parhi |
Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(3), pp. 199-213, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
LMS design, power efficient folding, wireline communications, traveling sales person, relaxed LMS, low power design, greedy algorithm, algorithm transformation |
30 | Jan Hoogerbrugge, Lex Augusteijn |
Pipelined Java Virtual Machine Interpreters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 9th International Conference, CC 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 35-49, 2000, Springer, 3-540-67263-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Chen Ding, Steve Carr 0001, Philip H. Sweany |
Modulo Scheduling with Cache Reuse Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 1079-1083, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Tang-Hsun Tu, Chih-wen Hsueh |
Batch-Pipelining for H.264 Decoding on Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCC ![In: 2010 Data Compression Conference (DCC 2010), 24-26 March 2010, Snowbird, UT, USA, pp. 553, 2010, IEEE Computer Society, 978-0-7695-3994-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Optimization, Multimedia, Pipelining, Multicore, H.264 |
28 | Matthias Függer, Andreas Dielacher, Ulrich Schmid 0001 |
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Eighth European Dependable Computing Conference, EDCC-8 2010, Valencia, Spain, 28-30 April 2010, pp. 230-239, 2010, IEEE Computer Society, 978-0-7695-4007-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
modeling approaches, VLSI, pipelining, clock synchronization, Fault-tolerant distributed algorithms |
28 | Yong Dou, Guiming Wu, Jinhui Xu 0002, Xingming Zhou |
A coarse-grained reconfigurable computing architecture with loop self-pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(4), pp. 575-587, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable computing, data driven, loop pipelining, register promotion |
28 | Andreas Dielacher, Matthias Függer, Ulrich Schmid 0001 |
Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the 28th Annual ACM Symposium on Principles of Distributed Computing, PODC 2009, Calgary, Alberta, Canada, August 10-12, 2009, pp. 276-277, 2009, ACM, 978-1-60558-396-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modeling approaches, VLSI, pipelining, clock synchronization, fault-tolerant distributed algorithms |
28 | Christopher T. Johnston, Donald G. Bailey, Paul J. Lyons |
Towards a visual notation for pipelining in a visual programming language for programming FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHINZ ![In: Proceedings of the 7th ACM SIGCHI New Zealand Chapter's International Conference on Computer-Human Interaction: Design Centered HCI, 2006, Christchurch, New Zealand, July 6-7, 2006, pp. 1-9, 2006, ACM, 1-59593-473-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, visual programming language |
28 | Seongmoo Heo, Krste Asanovic |
Power-optimal pipelining in deep submicron technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 218-223, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
power scaling, supply voltage reduction, pipelining |
28 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 904-907, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect pipelining, statistical timing analysis |
28 | Joachim Worringen |
Pipelining and Overlapping for MPI Collective Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 28th Annual IEEE Conference on Local Computer Networks (LCN 2003), The Conference on Leading Edge and Practical Computer Networking, 20-24 October 2003, Bonn/Königswinter, Germany, Proceedings, pp. 548-557, 2003, IEEE Computer Society, 0-7695-2037-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
MPI, pipelining, overlapping, SCI, collective operations |
28 | Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz |
Coarse-Grain Pipelining on Multiple FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 77-, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Coarse-grain Pipelining, FPGA-based Custom Computing Machines, Parallelizing Compiler Analysis Techniques |
28 | Pawel Chodowiec, Po Khuon, Kris Gaj |
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 94-102, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fast architectures, secret-key ciphers, pipelining, AES |
28 | Glenn Altemose, Cindy Norris |
Register pressure responsive software pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), March 11-14, 2001, Las Vegas, NV, USA, pp. 626-631, 2001, ACM, 1-58113-287-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining |
28 | Daehong Kim, Dongwan Shin, Kiyoung Choi |
Low power pipelining of linear systems: a common operand centric approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 225-230, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
common operand, operand sharing, low power, pipelining |
28 | Roberto R. Osorio, Javier D. Bruguera |
New arithmetic coder/decoder architectures based on pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 106-115, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
arithmetic coder/decoder architectures, arithmetic encoding, arithmetic decoding, multilevel images, cycle length, VLSI, pipelining, VLSI architectures |
28 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(11), pp. 1133-1149, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling |
28 | Pierre-Yves Calland, Alain Darte, Yves Robert |
A New Guaranteed Heuristic for the Software Pipelining Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 10th international conference on Supercomputing, ICS 1996, Philadelphia, PA, USA, May 25-28, 1996, pp. 261-269, 1996, ACM, 0-89791-803-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit retiming, guaranteed heuristic, software pipelining, list scheduling, cyclic scheduling |
28 | Ming-Syan Chen, Ming-Ling Lo, Philip S. Yu, Honesty C. Young |
Applying Segmented Right-Deep Trees to Pipelining Multiple Hash Joins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 7(4), pp. 656-668, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
bushy trees, right-deep trees, Pipelining, parallel query processing, hash joins |
28 | James D. Allen, David E. Schimmel |
The impact of pipelining on SIMD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 380-387, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
massively parallel SIMD architectures, stall penalties, reduction operations, Scheduling mechanisms, area costs, scheduling, parallel architectures, pipelining, program compilers, pipeline processing, performance improvement, SIMD architectures, instruction delivery |
28 | S. Rao Kosaraju |
Pipelining Computations in a Tree of Processors (Preliminary Version) ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 30th Annual Symposium on Foundations of Computer Science, Research Triangle Park, North Carolina, USA, 30 October - 1 November 1989, pp. 184-189, 1989, IEEE Computer Society, 0-8186-1982-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
tree of processors, lower bound, dictionaries, pipelining computations, sampling technique |
28 | Yih-Chyun Jenq |
Digital Convolution Algorithm for Pipelining Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(12), pp. 966-973, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
digital convolution algorithm, pipelining, multiprocessing, Dedicated processor, tree machine |
28 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 43-52, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
28 | Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang |
Practice of parallelizing network applications on multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 204-213, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
application-level protocol processing, deep content inspection, lock-free data structures, multi-core parallelization, pipelining implementation, tcp/ip protocol processing |
28 | Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001 |
Post-pass periodic register allocation to minimise loop unrolling degree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 141-150, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded code optimisation, periodic register allocation, software pipelining, loop unrolling |
28 | Hugo Venturini, Frédéric Riss, Jean-Claude Fernandez, Miguel Santana |
Non-transparent debugging for software-pipelined loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 23-32, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-transparent debugging, compiler, software-pipelining, debugger |
28 | Christopher Zimmer 0001, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley |
Facilitating compiler optimizations through the dynamic mapping of alternate register structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 165-169, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register queues, compiler optimizations, software pipelining |
28 | Pradeep Kumar Mishra |
Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems (Extended Version). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(8), pp. 1000-1010, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
EC-operations, comb methods, Jacobian coordinates, sidechannel attacks, sidechannel atomicity, pipelining, ECC, Elliptic Curve Cryptosystems, scalar multiplication, binary methods |
28 | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
Microarchitecture-aware floorplanning using a statistical design of experiments approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 579-584, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, wire pipelining |
28 | John Teifel, Rajit Manohar |
Highly pipelined asynchronous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 133-142, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
concurrency, pipelining, asynchronous circuits, programmable logic, correctness by construction |
28 | Vidyasagar Nookala, Sachin S. Sapatnekar |
A method for correcting the functionality of a wire-pipelined circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 570-575, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
synchronous design, wire pipelining |
28 | Qingfeng Zhuge, Bin Xiao 0001, Edwin Hsing-Mean Sha |
Code size reduction technique and implementation for software-pipelined DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(4), pp. 590-613, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scheduling, software pipelining, Retiming, DSP processors |
28 | Masaru Takesue |
Software Queue-Based Algorithms for Pipelined Synchronization on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 6-9 October 2003, Kaohsiung, Taiwan, pp. 115-122, 2003, IEEE Computer Society, 0-7695-2018-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
queue-based locks, algorithms, synchronization, Multiprocessors, pipelining |
28 | J. Living, M. Moniri, S. B. Tennakoon |
Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 269-295, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IIR digital filters, iteration bound, look ahead pipelining, resource minimisation |
28 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
MIRS: Modulo Scheduling with Integrated Register Spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1-3, 2001. Revised Papers, pp. 239-253, 2001, Springer, 3-540-04029-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code |
28 | Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan |
Buffer Assignment Algorithms on Data Driven ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(1), pp. 16-32, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture |
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