Search results for "pipelining"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
35	Smita Bakshi, Daniel Gajski	A Scheduling and Pipelining Algorithm for Hardware/Software Systems.	ISSS	1997	DBLP DOI BibTeX RDF	throughput-constrained, scheduling, pipelining, high-performance, Hardware/software codesign
35	Peter Pfahler, Georg Piepenbrock	A Comparison of Modulo Scheduling Techniques for Software Pipelining.	CC	1996	DBLP DOI BibTeX RDF	Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors
35	Fermín Sánchez	Time-Constrained Loop Pipelining.	ICCAD	1995	DBLP DOI BibTeX RDF	timing and resource contraints, register optimization, scheduling, loop pipelining
35	Bogong Su, Stanley Habib, Wei Zhao, Jian Wang 0046, Youfeng Wu	A study of pointer aliasing for software pipelining using run-time disambiguation.	MICRO	1994	DBLP DOI BibTeX RDF	compensation code, pointer aliasing, rerollability, run-time disambiguation, software pipelining
35	B. Ramakrishna Rau	Iterative modulo scheduling: an algorithm for software pipelining loops.	MICRO	1994	DBLP DOI BibTeX RDF	software pipelining, instruction scheduling, modulo scheduling, loop scheduling
35	Hongbo Rong, Alban Douillet, Guang R. Gao	Register allocation for software pipelined multi-dimensional loops.	PLDI	2005	DBLP DOI BibTeX RDF	register allocation, software pipelining
35	Pradeep Kumar Mishra	Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems.	CHES	2004	DBLP DOI BibTeX RDF	Jacobian coordinates, pipelining, Elliptic curve cryptosystems, scalar multiplication
35	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
35	Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger	An ASIC Implementation of the AES SBoxes.	CT-RSA	2002	DBLP DOI BibTeX RDF	standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic
35	G. X. Tyson, M. Smelyanskyi, Edward S. Davidson	Evaluating the Use of Register Queues in Software Pipelined Loops.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW
33	Ramaswamy Govindarajan, Guang R. Gao, Palash Desai	Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	buffer minimization, Digital Signal Processing (DSP) computation, Multi-Rate Software Pipelining, Regular Stream Flow Graphs, software pipelining, dataflow graphs
30	Hirochika Asai	Deep Pipelining: Efficient Pipelining of Network Function Chains with Coroutines.	NetSoft	2019	DBLP DOI BibTeX RDF
30	Priyankar Talukdar	On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints.	VDAT	2015	DBLP DOI BibTeX RDF
30	Manish Garg	High performance pipelining method for static circuits using heterogeneous pipelining elements.	ESSCIRC	2003	DBLP DOI BibTeX RDF
30	Yoshiyuki Yamashita, Masato Tsuru	Implementing Fast Packet Filters by Software Pipelining on x86 Processors.	APPT	2009	DBLP DOI BibTeX RDF
30	Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE (2)	2009	DBLP DOI BibTeX RDF
30	Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee	A software pipelining algorithm in high-level synthesis for FPGA architectures.	ISQED	2009	DBLP DOI BibTeX RDF
30	Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu	Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	data transition detection, CLA, pipeline, power-aware, ANT
30	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
30	Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August	Parallel-stage decoupled software pipelining.	CGO	2008	DBLP DOI BibTeX RDF	doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism
30	Timothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms	Correct-by-construction microarchitectural pipelining.	ICCAD	2008	DBLP DOI BibTeX RDF
30	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE (4)	2008	DBLP DOI BibTeX RDF
30	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.	DATE	2007	DBLP DOI BibTeX RDF
30	Colin J. Ihrig, Justin Stander, Alex K. Jones	Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions.	IPDPS	2007	DBLP DOI BibTeX RDF
30	Ming Su, Lili Zhou, C.-J. Richard Shi	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.	ICCD	2007	DBLP DOI BibTeX RDF
30	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu	Exploiting Software Pipelining for Network-on-Chip architectures.	ISVLSI	2006	DBLP DOI BibTeX RDF
30	Kishan Chand Gupta, Pradeep Kumar Mishra, Pinakpani Pal	A General Methodology for Pipelining the Point Multiplication Operation in Curve Based Cryptography.	ACNS	2006	DBLP DOI BibTeX RDF
30	Alban Douillet, Hongbo Rong, Guang R. Gao	Multi-dimensional Kernel Generation for Loop Nest Software Pipelining.	Euro-Par	2006	DBLP DOI BibTeX RDF
30	Dongwuk Kyoung, Keechul Jung	Fully-Pipelining Hardware Implementation of Neural Network for Text-Based Images Retrieval.	ISNN (2)	2006	DBLP DOI BibTeX RDF
30	Jinhui Xu 0002, Guiming Wu, Yong Dou, Yazhuo Dong	Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
30	Ke Zhou 0001, Zhongying Niu	Decease I/O Mean Response Time Using Software Pipelining.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF
30	Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu	"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense.	MICRO	2005	DBLP DOI BibTeX RDF
30	Jahangir Hasan, T. N. Vijaykumar	Dynamic pipelining: making IP-lookup truly scalable.	SIGCOMM	2005	DBLP DOI BibTeX RDF	scalable, pipelined, IP-lookup, longest prefix matching, tries
30	Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen	Pipelining technique for energy-aware datapaths.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
30	João M. P. Cardoso	Self-loop Pipelining and Reconfigurable Dataflow Arrays.	SAMOS	2004	DBLP DOI BibTeX RDF
30	Steven J. E. Wilton, Su-Shin Ang, Wayne Luk	The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays.	FPL	2004	DBLP DOI BibTeX RDF
30	V. Seth, Min Zhao 0001, Jiang Hu	Exploiting level sensitive latches in wire pipelining.	ICCAD	2004	DBLP DOI BibTeX RDF
30	Mario R. Casu, Luca Macchiarulo	On-Chip Transparent Wire Pipelining.	ICCD	2004	DBLP DOI BibTeX RDF
30	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
30	Greg Snider	Performance-constrained pipelining of software loops onto reconfigurable hardware.	FPGA	2002	DBLP DOI BibTeX RDF
30	Matthias Korch, Thomas Rauber, Gudula Rünger	Pipelining for Locality Improvement in RK Methods.	Euro-Par	2002	DBLP DOI BibTeX RDF
30	Raya Leviathan, Amir Pnueli	Validating software pipelining optimizations.	CASES	2002	DBLP DOI BibTeX RDF	optimization, verification, compilers, pipeline processors, translation validation
30	Shing Tenqchen, Ji-Horn Chang, Wu-Shiung Feng, Bor-Sheng Jeng	Pipelining Extended Givens Rotation RLS Adaptive Filters.	DELTA	2002	DBLP DOI BibTeX RDF
30	Nilesh N. Dalvi, Sumit K. Sanghai, Prasan Roy, S. Sudarshan 0001	Pipelining in Multi-Query Optimization. (PDF / PS)	PODS	2001	DBLP DOI BibTeX RDF
30	Michael T. Niemier, Peter M. Kogge	Exploring and exploiting wire-level pipelining in emerging technologies.	ISCA	2001	DBLP DOI BibTeX RDF
30	E. Christopher Lewis, Lawrence Snyder	Pipelining Wavefront Computations: Experiences and Performance.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
30	Cagdas Akturan, Margarida F. Jacome	FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors.	ISSS	2000	DBLP DOI BibTeX RDF
30	Martin Weichert	Pipelining the Molecule Soup: A Plumber's Approach to Gamma.	COORDINATION	1999	DBLP DOI BibTeX RDF
30	Jason Cong, Chang Wu	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.	DAC	1997	DBLP DOI BibTeX RDF
30	Josep Llosa, Mateo Valero, Eduard Ayguadé	Heuristics for Register-Constrained Software Pipelining.	MICRO	1996	DBLP DOI BibTeX RDF
30	John C. Ruttenberg, Guang R. Gao, Woody Lichtenstein, Artour Stoutchinin	Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler.	PLDI	1996	DBLP DOI BibTeX RDF
30	Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao	A Framework for Resource-Constrained Rate-Optimal Software Pipelining.	CONPAR	1994	DBLP DOI BibTeX RDF
30	Qi Ning, Guang R. Gao	A Novel Framework of Register Allocation for Software Pipelining.	POPL	1993	DBLP DOI BibTeX RDF
30	Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong	An Efficient Scheme for Fine-Grain Software Pipelining.	CONPAR	1990	DBLP DOI BibTeX RDF
30	Bogong Su, Shiyuan Ding, Jian Wang 0046, Jinshi Xia	GURPR - a method for global software pipelining.	MICRO	1987	DBLP DOI BibTeX RDF
30	Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur	Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani	Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	Eric L. Hill, Mikko H. Lipasti	Stall cycle redistribution in a transparent fetch pipeline.	ISLPED	2006	DBLP DOI BibTeX RDF	pipeline gating, microarchitecture, dynamic power, instruction fetch
30	Marco Macchetti, Luigi Dadda	Quasi-Pipelined Hash Circuits.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
30	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.	DAC	2004	DBLP DOI BibTeX RDF	piecewise-linear, performance, pipeline, interconnect, floorplanning
30	Jos Sulistyo, Dong Sam Ha	5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
30	Glenn Reinman, Brad Calder, Todd M. Austin	Optimizations Enabled by a Decoupled Front-End Architecture.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	fetch architectures, branch prediction, Decoupled architectures, instruction prefetching
30	Ahmed F. Shalash, Keshab K. Parhi	Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	LMS design, power efficient folding, wireline communications, traveling sales person, relaxed LMS, low power design, greedy algorithm, algorithm transformation
30	Jan Hoogerbrugge, Lex Augusteijn	Pipelined Java Virtual Machine Interpreters.	CC	2000	DBLP DOI BibTeX RDF
30	Chen Ding, Steve Carr 0001, Philip H. Sweany	Modulo Scheduling with Cache Reuse Information.	Euro-Par	1997	DBLP DOI BibTeX RDF
28	Tang-Hsun Tu, Chih-wen Hsueh	Batch-Pipelining for H.264 Decoding on Multicore Systems.	DCC	2010	DBLP DOI BibTeX RDF	Optimization, Multimedia, Pipelining, Multicore, H.264
28	Matthias Függer, Andreas Dielacher, Ulrich Schmid 0001	How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining.	EDCC	2010	DBLP DOI BibTeX RDF	modeling approaches, VLSI, pipelining, clock synchronization, Fault-tolerant distributed algorithms
28	Yong Dou, Guiming Wu, Jinhui Xu 0002, Xingming Zhou	A coarse-grained reconfigurable computing architecture with loop self-pipelining.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	reconfigurable computing, data driven, loop pipelining, register promotion
28	Andreas Dielacher, Matthias Függer, Ulrich Schmid 0001	Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining.	PODC	2009	DBLP DOI BibTeX RDF	modeling approaches, VLSI, pipelining, clock synchronization, fault-tolerant distributed algorithms
28	Christopher T. Johnston, Donald G. Bailey, Paul J. Lyons	Towards a visual notation for pipelining in a visual programming language for programming FPGAs.	CHINZ	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, visual programming language
28	Seongmoo Heo, Krste Asanovic	Power-optimal pipelining in deep submicron technology.	ISLPED	2004	DBLP DOI BibTeX RDF	power scaling, supply voltage reduction, pipelining
28	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, statistical timing analysis
28	Joachim Worringen	Pipelining and Overlapping for MPI Collective Operations.	LCN	2003	DBLP DOI BibTeX RDF	MPI, pipelining, overlapping, SCI, collective operations
28	Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz	Coarse-Grain Pipelining on Multiple FPGA Architectures.	FCCM	2002	DBLP DOI BibTeX RDF	Coarse-grain Pipelining, FPGA-based Custom Computing Machines, Parallelizing Compiler Analysis Techniques
28	Pawel Chodowiec, Po Khuon, Kris Gaj	Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining.	FPGA	2001	DBLP DOI BibTeX RDF	fast architectures, secret-key ciphers, pipelining, AES
28	Glenn Altemose, Cindy Norris	Register pressure responsive software pipelining.	SAC	2001	DBLP DOI BibTeX RDF	register allocation, software pipelining
28	Daehong Kim, Dongwan Shin, Kiyoung Choi	Low power pipelining of linear systems: a common operand centric approach.	ISLPED	2001	DBLP DOI BibTeX RDF	common operand, operand sharing, low power, pipelining
28	Roberto R. Osorio, Javier D. Bruguera	New arithmetic coder/decoder architectures based on pipelining.	ASAP	1997	DBLP DOI BibTeX RDF	arithmetic coder/decoder architectures, arithmetic encoding, arithmetic decoding, multilevel images, cycle length, VLSI, pipelining, VLSI architectures
28	Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao	A Framework for Resource-Constrained Rate-Optimal Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	superscalar and VLIW architectures, Instruction-level parallelism, integer linear programming, software pipelining, instruction scheduling
28	Pierre-Yves Calland, Alain Darte, Yves Robert	A New Guaranteed Heuristic for the Software Pipelining Problem.	International Conference on Supercomputing	1996	DBLP DOI BibTeX RDF	circuit retiming, guaranteed heuristic, software pipelining, list scheduling, cyclic scheduling
28	Ming-Syan Chen, Ming-Ling Lo, Philip S. Yu, Honesty C. Young	Applying Segmented Right-Deep Trees to Pipelining Multiple Hash Joins.	IEEE Trans. Knowl. Data Eng.	1995	DBLP DOI BibTeX RDF	bushy trees, right-deep trees, Pipelining, parallel query processing, hash joins
28	James D. Allen, David E. Schimmel	The impact of pipelining on SIMD architectures.	IPPS	1995	DBLP DOI BibTeX RDF	massively parallel SIMD architectures, stall penalties, reduction operations, Scheduling mechanisms, area costs, scheduling, parallel architectures, pipelining, program compilers, pipeline processing, performance improvement, SIMD architectures, instruction delivery
28	S. Rao Kosaraju	Pipelining Computations in a Tree of Processors (Preliminary Version)	FOCS	1989	DBLP DOI BibTeX RDF	tree of processors, lower bound, dictionaries, pipelining computations, sampling technique
28	Yih-Chyun Jenq	Digital Convolution Algorithm for Pipelining Multiprocessor Systems.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	digital convolution algorithm, pipelining, multiprocessing, Dedicated processor, tree machine
28	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
28	Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang	Practice of parallelizing network applications on multi-core architectures.	ICS	2009	DBLP DOI BibTeX RDF	application-level protocol processing, deep content inspection, lock-free data structures, multi-core parallelization, pipelining implementation, tcp/ip protocol processing
28	Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001	Post-pass periodic register allocation to minimise loop unrolling degree.	LCTES	2008	DBLP DOI BibTeX RDF	embedded code optimisation, periodic register allocation, software pipelining, loop unrolling
28	Hugo Venturini, Frédéric Riss, Jean-Claude Fernandez, Miguel Santana	Non-transparent debugging for software-pipelined loops.	CASES	2007	DBLP DOI BibTeX RDF	non-transparent debugging, compiler, software-pipelining, debugger
28	Christopher Zimmer 0001, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley	Facilitating compiler optimizations through the dynamic mapping of alternate register structures.	CASES	2007	DBLP DOI BibTeX RDF	register queues, compiler optimizations, software pipelining
28	Pradeep Kumar Mishra	Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems (Extended Version).	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	EC-operations, comb methods, Jacobian coordinates, sidechannel attacks, sidechannel atomicity, pipelining, ECC, Elliptic Curve Cryptosystems, scalar multiplication, binary methods
28	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
28	John Teifel, Rajit Manohar	Highly pipelined asynchronous FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	concurrency, pipelining, asynchronous circuits, programmable logic, correctness by construction
28	Vidyasagar Nookala, Sachin S. Sapatnekar	A method for correcting the functionality of a wire-pipelined circuit.	DAC	2004	DBLP DOI BibTeX RDF	synchronous design, wire pipelining
28	Qingfeng Zhuge, Bin Xiao 0001, Edwin Hsing-Mean Sha	Code size reduction technique and implementation for software-pipelined DSP applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	scheduling, software pipelining, Retiming, DSP processors
28	Masaru Takesue	Software Queue-Based Algorithms for Pipelined Synchronization on Multiprocessors.	ICPP Workshops	2003	DBLP DOI BibTeX RDF	queue-based locks, algorithms, synchronization, Multiprocessors, pipelining
28	J. Living, M. Moniri, S. B. Tennakoon	Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	IIR digital filters, iteration bound, look ahead pipelining, resource minimisation
28	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	MIRS: Modulo Scheduling with Integrated Register Spilling.	LCPC	2001	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code
28	Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan	Buffer Assignment Algorithms on Data Driven ASICs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture