Search results for "set-associative"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	José Luis Hamkalo, Andrés Djordjalian, Bruno Cernuschi-Frías	A shared-way set associative architecture for on-chip caches.	CATA	2001	DBLP BibTeX RDF
15	Ramon Doallo, Basilio B. Fraguela, Emilio L. Zapata	Set Associative Cache Behavior Optimization.	Euro-Par	1999	DBLP DOI BibTeX RDF
15	John Stuart Harper, Darren J. Kerbyson, Graham R. Nudd	Efficient Analytical Modelling of Multi-Level Set-Associative Caches.	HPCN	1999	DBLP DOI BibTeX RDF
15	Koji Inoue, Tohru Ishihara, Kazuaki J. Murakami	Way-predicting set-associative cache for high performance and low energy consumption.	ISLPED	1999	DBLP DOI BibTeX RDF
15	Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata	Modeling Set Associative Caches Behavior for Irregular Computations.	SIGMETRICS	1998	DBLP DOI BibTeX RDF	probabilistic model, cache performance, sparse matrix, irregular computation
15	Frank Mueller 0001	Generalizing timing predictions to set-associative caches.	RTS	1997	DBLP DOI BibTeX RDF
15	Nathalie Drach, André Seznec, Daniel Windheiser	Direct-mapped versus set-associative pipelined caches.	PACT	1995	DBLP BibTeX RDF
15	Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu	Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches.	ICPP (1)	1993	DBLP DOI BibTeX RDF
15	C. Eric Wu, Yarsun Hsu, Yew-Huey Liu	Stack simulation for set-associative V/R-type caches.	COMPSAC	1992	DBLP DOI BibTeX RDF
15	Yuguang Wu, Gerald J. Popek, Richard R. Muntz	Efficient Evaluation of Arbitrary Set-Associative Caches on Multiprocessors.	SPDP	1992	DBLP DOI BibTeX RDF
15	Wen-Hann Wang, Jim Quinlan, Konrad Lai	Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches.	ISCA	1992	DBLP DOI BibTeX RDF
15	Stephen A. Ward, Robert C. Zak	Set-associative dynamic random access memory.	ICCD	1988	DBLP DOI BibTeX RDF
15	Alan Jay Smith	A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory.	IEEE Trans. Software Eng.	1978	DBLP DOI BibTeX RDF
15	Alan Jay Smith	On the Effectiveness of Set Associative Page Mapping and Its Application to Main Memory Management.	ICSE	1976	DBLP BibTeX RDF
15	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López 0001, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
15	Chuanjun Zhang	Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
15	Jan Staschulat, Rolf Ernst	Scalable precision cache analysis for preemptive scheduling.	LCTES	2005	DBLP DOI BibTeX RDF	scheduling, embedded systems, cache, worst case execution time analysis
15	Mathias Spjuth, Martin Karlsson, Erik Hagersten	Skewed caches from a low-power perspective.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	elbow, skewed caches, low-power, CAT
15	Min-wuk Lee, Byeong-Gyu Nam, Ju-Ho Sohn, Namjun Cho, Hyejung Kim, Kwanho Kim, Hoi-Jun Yoo	A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato	A leakage-energy-reduction technique for highly-associative caches in embedded systems.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF	cache memories, embedded processors, leakage current
15	Pepijn J. de Langen, Ben H. H. Juurlink	Reducing traffic generated by conflict misses in caches.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	caches, embedded processors, power reduction, conflict misses
15	John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk	Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories.	DFT	2004	DBLP DOI BibTeX RDF
15	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A Highly-Configurable Cache Architecture for Embedded Systems.	ISCA	2003	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, low energy, architecture tuning
15	Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta 0001	Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.	ISHPC	2002	DBLP DOI BibTeX RDF
15	Lishing Liu	Partial address directory for cache access.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
15	Seif Haridi, Erik Hagersten	The Cache Coherence Protocol of the Data Diffusion Machine.	PARLE (1)	1989	DBLP DOI BibTeX RDF
14	Yu Liu 0037, Wei Zhang 0002	Exploiting stack distance to estimate worst-case data cache performance.	SAC	2009	DBLP DOI BibTeX RDF	stack distance, cache, timing analysis, worst-case execution time
14	Linda M. Null, Karishma Rao	CAMERA: introducing memory concepts via visualization.	SIGCSE	2005	DBLP DOI BibTeX RDF	computer memory workbenches, education, tutorial
14	Calin Cascaval, David A. Padua	Estimating cache misses and locality using stack distances.	ICS	2003	DBLP DOI BibTeX RDF	stack algorithms, cache modeling, compiler algorithms
14	Adam Wiggins, Simon Winwood, Harvey Tuch, Gernot Heiser	Legba: Fast Hardware Support for Fine-Grained Protection.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
14	Amos Fiat, Manor Mendel, Steven S. Seiden	Online Companion Caching.	ESA	2002	DBLP DOI BibTeX RDF
14	Andrés Djordjalian	Minimally-Skewed-Associative Caches.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
14	Hans Vandierendonck, Koenraad De Bosschere	A Comparison of Locality-Based and Recency-Based Replacement Policies.	ISHPC	2000	DBLP DOI BibTeX RDF
14	François Bodin, André Seznec	Skewed Associativity Enhances Performance Predictability.	ISCA	1995	DBLP DOI BibTeX RDF
14	Jeffrey J. Rothschild	Cache organizations.	ACM Southeast Regional Conference	1979	DBLP DOI BibTeX RDF	Buffer memories, computer architecture, cache memories, paging, memory organization
10	Madhu Mutyam, Narayanan Vijaykrishnan	Working with process variation aware caches.	DATE	2007	DBLP DOI BibTeX RDF
10	Yutao Zhong 0001, Steven G. Dropsho, Xipeng Shen, Ahren Studer, Chen Ding 0001	Miss Rate Prediction Across Program Inputs and Cache Configurations.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	optimization, compilers, Cache memories, modeling techniques, performance analysis and design aids
9	Yutao Zhong 0001, Steve Dropsho, Chen Ding 0001	Miss Rate Prediction across All Program Inputs.	IEEE PACT	2003	DBLP DOI BibTeX RDF
9	Brad Calder, Dirk Grunwald, Joel S. Emer	Predictive Sequential Associative Cache.	HPCA	1996	DBLP DOI BibTeX RDF	predictive sequential associative cache, miss rate, prediction sources, storage management, memory architecture, content-addressable storage, access time, direct-mapped cache, access latency
9	Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill	Inexpensive Implementations of Set-Associativity.	ISCA	1989	DBLP DOI BibTeX RDF
8	Chuanjun Zhang	Reducing cache misses through programmable decoders.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	low power, Cache, dynamic optimization
8	Minghua Tang, Xiaola Lin	A Novel Scheme to Balance the Cache Sharing in High Performance Computing System.	HPCC	2008	DBLP DOI BibTeX RDF
8	Mingming Zhang, Xiaotao Chang, Ge Zhang 0007	Reducing cache energy consumption by tag encoding in embedded processors.	ISLPED	2007	DBLP DOI BibTeX RDF	tag encoding, cache, low power design, embedded processors
8	Fong Pong, Nian-Feng Tzeng	Storage-Efficient Architecture for Routing Tables via Prefix Transformation.	LCN	2007	DBLP DOI BibTeX RDF
8	Chuanjun Zhang	Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches.	ISCA	2006	DBLP DOI BibTeX RDF
8	Tohru Ishihara, Farzan Fallah	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.	DATE	2005	DBLP DOI BibTeX RDF
8	Zhiqiang Ma, Zhenzhou Ji, Mingzeng Hu, Yi Ji	Energy Efficient United L2 Cache Design with Instruction/Data Filter Scheme.	APPT	2005	DBLP DOI BibTeX RDF
8	Ramesh V. Peri, John Fernando, Ravi K. Kolagotla	Addressing mode driven low power data caches for embedded processors.	WMPI	2004	DBLP DOI BibTeX RDF
8	Martin Kämpe, Per Stenström, Michel Dubois 0001	Self-correcting LRU replacement policies.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	LRU algorithms, mistake prediction, shadow directories
8	Alaa R. Alameldeen, David A. Wood 0001	Adaptive Cache Compression for High-Performance Processors.	ISCA	2004	DBLP DOI BibTeX RDF
8	Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau	Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors.	DATE	2003	DBLP DOI BibTeX RDF
8	Toni Juan, Tomás Lang, Juan J. Navarro	The Difference-bit Cache.	ISCA	1996	DBLP DOI BibTeX RDF
8	Edouard Bugnion, Jennifer-Ann M. Anderson, Todd C. Mowry, Mendel Rosenblum, Monica S. Lam	Compiler-Directed Page Coloring for Multiprocessors.	ASPLOS	1996	DBLP DOI BibTeX RDF
8	Scott McFarling	Program Optimization for Instruction Caches.	ASPLOS	1989	DBLP DOI BibTeX RDF	RISC
7	Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem	CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP Lookup.	Networking	2009	DBLP DOI BibTeX RDF	hardware multiple hashing, content-based probing, IP lookup
7	Cuiping Xu, Ge Zhang, Shouqing Hao	Fast Way-Prediction Instruction Cache for Energy Efficiency and High Performance.	NAS	2009	DBLP DOI BibTeX RDF
7	Deze Zeng, Minyi Guo, Song Guo 0001, Mianxiong Dong, Hai Jin 0001	The Design and Evaluation of a Selective Way Based Trace Cache.	APPT	2009	DBLP DOI BibTeX RDF	instruction fetch unit design, selective way, energy efficient, computer architecture, trace cache
7	Jongmin Lee 0002, Soontae Kim	An energy-delay efficient 2-level data cache architecture for embedded system.	ISLPED	2009	DBLP DOI BibTeX RDF	2-level data cache, early cache hit predictor, one-way write
7	Guangyu Sun 0003, Xiaoxia Wu, Yuan Xie 0001	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, performance, 3D, L2 caches
7	Timothy M. Jones 0001, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O'Boyle	Instruction Cache Energy Saving Through Compiler Way-Placement.	DATE	2008	DBLP DOI BibTeX RDF
7	Naizheng Bian, Hao Chen	A Least Grade Page Replacement Algorithm for Web Cache Optimization.	WKDD	2008	DBLP DOI BibTeX RDF
7	Chih-Wen Hsueh, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin	Anticipatory access pipeline design for phased cache.	ISCAS	2008	DBLP DOI BibTeX RDF
7	Riku Saikkonen, Eljas Soisalon-Soininen	Cache-sensitive Memory Layout for Binary Trees.	IFIP TCS	2008	DBLP DOI BibTeX RDF
7	Hyungmin Cho, Bernhard Egger 0002, Jaejin Lee, Heonshik Shin	Dynamic data scratchpad memory management for a memory subsystem with an MMU.	LCTES	2007	DBLP DOI BibTeX RDF	horizontally-partitioned memory, post-pass optimization, compilers, scratchpad memory, demand paging
7	Emre Özer 0001, Stuart Biles	Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
7	Arul Sandeep Gade, Yul Chu	A Case for Dual-Mapping One-Way Caches.	ARCS	2006	DBLP DOI BibTeX RDF
7	Milene Barbosa Carvalho, Luís F. W. Góes, Carlos Augusto Paiva da Silva Martins	Dynamically reconfigurable cache architecture using adaptive block allocation policy.	IPDPS	2006	DBLP DOI BibTeX RDF
7	Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim	Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	embedded system, low-power, multimedia application, cache architecture
7	Fong Pong	Fast and Robust TCP Session Lookup by Digest Hash.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
7	Hui Zeng, Kanad Ghose	Register file caching for energy efficiency.	ISLPED	2006	DBLP DOI BibTeX RDF	register caching, energy-efficiency, register files
7	Allan Hartstein, Viji Srinivasan, Thomas R. Puzak, Philip G. Emma	Cache miss behavior: is it sqrt(2)?	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	performance, memory hierarchy, cache organization
7	Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai	An Automatic Cache Generator Based on Content-Addressable Memory.	APCCAS	2006	DBLP DOI BibTeX RDF
7	Yudong Tan, Vincent John Mooney III	WCRT analysis for a uniprocessor with a unified prioritized cache.	LCTES	2005	DBLP DOI BibTeX RDF	real-time system, timing analysis, cache design
7	Evangelia Athanasaki, Kornilios Kourtis, Nikos Anastopoulos, Nectarios Koziris	Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
7	Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad K. Lai	Scalable Load and Store Processing in Latency Tolerant Processors.	ISCA	2005	DBLP DOI BibTeX RDF
7	G. Edward Suh, Larry Rudolph, Srinivas Devadas	Dynamic Partitioning of Shared Cache Memory.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	CMP and SMT, shared caches, cache partitioning
7	Yudong Tan, Vincent John Mooney III	Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches.	DATE	2004	DBLP DOI BibTeX RDF
7	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A Self-Tuning Cache Architecture for Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
7	Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos	Accurate and Complexity-Effective Spatial Pattern Prediction.	HPCA	2004	DBLP DOI BibTeX RDF
7	Abdur Rakib, Oleg Parshin, Stephan Thesing, Reinhard Wilhelm	Component-Wise Instruction-Cache Behavior Prediction.	ATVA	2004	DBLP DOI BibTeX RDF
7	Pavel Tvrdík, Ivan Simecek	Performance Optimization and Evaluation for Linear Codes.	NAA	2004	DBLP DOI BibTeX RDF
7	Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata	Probabilistic Miss Equations: Evaluating Memory Hierarchy Performance.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	probabilistic miss estimation, Analytical modeling, performance prediction, memory hierarchy, compiler optimizations
7	Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim	An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications.	PDP	2003	DBLP DOI BibTeX RDF
7	Akihito Sakanaka, Toshinori Sato	Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction.	PATMOS	2003	DBLP DOI BibTeX RDF
7	Diego Andrade, Basilio B. Fraguela, Ramon Doallo	Cache Behavior Modeling of Codes with Data-Dependent Conditionals.	SCOPES	2003	DBLP DOI BibTeX RDF
7	Paul Racunas, Yale N. Patt	Partitioned first-level cache design for clustered microarchitectures.	ICS	2003	DBLP DOI BibTeX RDF	partitioned cache, clustered microarchitecture
7	Maria Grigoriadou, Maria Toula, Evangelos Kanidis	Design and Evaluation of a Cache Memory Simulation Program.	ICALT	2003	DBLP DOI BibTeX RDF
7	Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau	Reducing data cache energy consumption via cached load/store queue.	ISLPED	2003	DBLP DOI BibTeX RDF	LSQ, load queue, store queue, low power, cache, memory, low energy, low latency
7	Pavel Tvrdík, Ivan Simecek	Analytical Modeling of Optimized Sparse Linear Code.	PPAM	2003	DBLP DOI BibTeX RDF
7	Brian R. Mestan, Mikko H. Lipasti	Exploiting Partial Operand Knowledge.	ICPP	2003	DBLP DOI BibTeX RDF
7	Jason Stinson, Stefan Rusu	A 1.5GHz third generation itanium® 2 processor.	DAC	2003	DBLP DOI BibTeX RDF	on-die cache, reliability, test, design methodology, processor
7	Jung-Hoon Lee, Shin-Dug Kim, Charles C. Weems	Application-adaptive intelligent cache memory system.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	dynamic block fetching and cache memory, general application, media application, Memory hierarchy, temporal locality, spatial locality
7	Dana S. Henry, Gabriel H. Loh, Rahul Sami	Speculative Clustered Caches for Clustered Processors.	ISHPC	2002	DBLP DOI BibTeX RDF
7	Yul Chu, Mabo Robert Ito	An Efficient Indirect Branch Predictor.	Euro-Par	2001	DBLP DOI BibTeX RDF
7	Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, Shin-Dug Kim	A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure.	LCTES	2000	DBLP DOI BibTeX RDF
7	Jeffrey B. Rothman, Alan Jay Smith	Sector Cache Design and Performance.	MASCOTS	2000	DBLP DOI BibTeX RDF	sector cache, simulation, architecture, workloads, multiprogramming
7	Ernesto Damiani, Valentino Liberali, Andrea Tettamanzi	Dynamic Optimisation of Non-linear Feed Forward Circuits.	ICES	2000	DBLP DOI BibTeX RDF
7	Afzal Malik, Bill Moyer, Dan Cermak	A low power unified cache architecture providing power and performance flexibility (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
7	Afzal Malik, Bill Moyer, Dan Cermak	The M·CORETM M340 Unified Cache Architecture.	ICCD	2000	DBLP DOI BibTeX RDF
7	David H. Albonesi	Selective Cache Ways: On-Demand Cache Resource Allocation.	MICRO	1999	DBLP DOI BibTeX RDF