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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1267 occurrences of 744 keywords
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Results
Found 3383 publication records. Showing 3383 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
47 | Majdi Ben Hadj Ali |
An Object/Segment Oriented Skew-Correction Technique for Document Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 4th International Conference Document Analysis and Recognition (ICDAR '97), 2-Volume Set, August 18-20, 1997, Ulm, Germany, Proceedings, pp. 671-674, 1997, IEEE Computer Society, 0-8186-7898-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Connected components, Skew detection, Skew correction, optical character recognition systems |
45 | Xin-Wei Shih, Yao-Wen Chang |
Fast timing-model independent buffered clock-tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 80-85, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Fabian Kuhn, Thomas Locher, Rotem Oshman |
Gradient clock synchronization in dynamic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2009: Proceedings of the 21st Annual ACM Symposium on Parallelism in Algorithms and Architectures, Calgary, Alberta, Canada, August 11-13, 2009, pp. 270-279, 2009, ACM, 978-1-60558-606-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
distributed algorithms, clock synchronization, dynamic networks |
45 | Hongyu Chen, Chung-Kuan Cheng |
A multi-level transmission line network approach for multi-giga hertz clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 103-106, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri |
A novel clock distribution and dynamic de-skewing methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 626-631, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Amith R. Mamidala, Jiuxing Liu, Dhabaleswar K. Panda 0001 |
Efficient Barrier and Allreduce on Infiniband clusters using multicast and adaptive algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2004 IEEE International Conference on Cluster Computing (CLUSTER 2004), September 20-23 2004, San Diego, California, USA, pp. 135-144, 2004, IEEE Computer Society, 0-7803-8694-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Carl Ebeling, Brian Lockyear |
On the performance of level-clocked circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 342-357, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits |
42 | Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye |
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 197-202, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
on-chip sensors, self-compensation, clock distribution, manufacturing variability |
42 | Vinayak Honkote, Baris Taskin |
Zero clock skew synchronization with rotary clocking technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 588-593, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi |
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 794-798, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Atanu Chattopadhyay, Zeljko Zilic |
Built-in Clock Skew System for On-line Debug and Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 248-251, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Abinash Roy, Masud H. Chowdhury |
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2426-2429, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu |
Type-matching clock tree for zero skew clock gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 714-719, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
physical design, gated clock, clock network synthesis |
42 | Lichun Zhang, Yue Lu, Guoyue Chen, Patrick S. P. Wang |
Image Skew Detection for Formulas without Fraction Bars Using Connected Components Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Seventh International Conference on Computer and Information Technology (CIT 2007), October 16-19, 2007, University of Aizu, Fukushima, Japan, pp. 680-679, 2007, IEEE Computer Society, 978-0-7695-2983-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Sherif A. Tawfik, Volkan Kursun |
Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 645-648, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Pingli Huang, Yun Chiu |
A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1241-1244, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Sherif A. Tawfik, Volkan Kursun |
Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 73-78, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Shih-Hsu Huang, Yow-Tyng Nieh |
Synthesis of nonzero clock skew circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 961-976, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Anand Rajaram, Jiang Hu, Rabi N. Mahapatra |
Reducing clock skew variability via crosslinks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 1176-1182, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Ganesh Venkataraman, Jiang Hu, Frank Liu 0001, Cliff C. N. Sze |
Integrated placement and skew optimization for rotary clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 756-761, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee |
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 812-815, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Dihua Xi, Mohamed Kamel, Seong-Whan Lee |
Skew Estimation and Correction for Form Documents Using Wavelet Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIAR ![In: Image Analysis and Recognition, Second International Conference, ICIAR 2005, Toronto, Canada, September 28-30, 2005, Proceedings, pp. 182-190, 2005, Springer, 3-540-29069-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Adnan Amin, Sue Wu |
Robust Skew Detection in mixed Text/Graphics Documents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Eighth International Conference on Document Analysis and Recognition (ICDAR 2005), 29 August - 1 September 2005, Seoul, Korea, pp. 247-251, 2005, IEEE Computer Society, 0-7695-2420-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida |
Skew measurements in clock distribution circuits using an analytic signal method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7), pp. 997-1009, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Shih-Hsu Huang, Yow-Tyng Nieh |
Clock Period Minimization of Non-Zero Clock Skew Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 809-812, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Sei Hyung Jang |
A new synchronous mirror delay with an auto-skew-generation circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 397-400, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Mohamed Nekili, Yvon Savaria, Guy Bois |
Minimizing process-induced skew using delay tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 426-429, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | Mostafa Bamha, Gaétan Hains |
A Skew-insensitive Algorithm for Join and Multi-join Operations on Shared Nothing Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA ![In: Database and Expert Systems Applications, 11th International Conference, DEXA 2000, London, UK, September 4-8, 2000, Proceedings, pp. 644-653, 2000, Springer, 3-540-67978-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | Xiaohong Jiang 0001, Susumu Horiguchi |
Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 96-104, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas |
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 168-171, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | Ivan S. Kourtev, Eby G. Friedman |
Clock skew scheduling for improved reliability via quadratic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 239-243, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Andrew V. Goldberg, Alexander V. Karzanov |
Maximum Skew-Symmetric Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA '95, Third Annual European Symposium, Corfu, Greece, September 25-27, 1995, Proceedings, pp. 155-170, 1995, Springer, 3-540-60313-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
42 | Jae Chung, Chung-Kuan Cheng |
Skew sensitivity minimization of buffered clock tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 280-283, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
42 | Shen Lin, C. K. Wong |
Process-variation-tolerant clock skew minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 284-288, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
42 | Ren-Song Tsay |
An exact zero-skew clock routing algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2), pp. 242-249, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
42 | Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Yazawa, Teruo Tanaka, Yasuhiro Inagami, Yoshiko Tamaki |
Scalable Parallel Memory Architecture with a Skew Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 7th international conference on Supercomputing, ICS 1993, Tokyo, Japan, July 20-22, 1993, pp. 157-166, 1993, ACM, 0-89791-600-X. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
ILLIAC IV |
40 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu |
A single layer zero skew clock routing in X architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(8), pp. 1466-1475, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
single layer, X architecture, zero skew, clock routing |
40 | Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman |
Power efficient tree-based crosslinks for skew reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 285-290, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
crosslink, non-tree clock distribution network, power, mesh, skew, clock tree |
40 | Yi Wang, Wai-Shing Luk, Xuan Zeng 0001, Jun Tao 0001, Changhao Yan, Jiarong Tong, Wei Cai 0003, Jia Ni |
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 223-226, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-Gaussian, process variations, yield, clock skew scheduling |
40 | Min Ni, Seda Ogrenci Memik |
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 610-613, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-Vth, leakage power optimization, gate sizing, clock skew scheduling |
40 | Charbel J. Akl, Magdy A. Bayoumi |
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 696-701, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
transition skew coding, global on-chip interconnects, bus encoding technique, encoding latencies, decoding latencies, 90 nm |
40 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic thermal clock skew compensation using tunable delay buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 162-167, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
temperature aware design methodology, tunable delay buffers, clock skew, clock tree |
40 | David Camarero, Jean-François Naviner, Patrick Loumeau |
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 228-232, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
digital calibration, parallel ADC, sample-time errors, time-interleaved, adaptive filters, clock skew |
40 | Yu-lung Lo, Yu-chen Huang |
Effective Skew Handling for Parallel Sorting in Multiprocessor Database Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 9th International Conference on Parallel and Distributed Systems, ICPADS 2002, Taiwan, ROC, December 17-20, 2002, pp. 151-156, 2002, IEEE Computer Society, 0-7695-1760-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Load Balancing, Parallel Sort, Data Skew |
40 | Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Power Supply Noise Suppression via Clock Skew Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 355-360, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Skew Scheduling, Power noise, Clock |
40 | Baris Taskin, Ivan S. Kourtev |
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 111-118, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimization, linear programming, clock skew, cycle stealing |
40 | Amit Kumar Das 0001, Bhabatosh Chanda |
A fast algorithm for skew detection of document images using morphology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Document Anal. Recognit. ![In: Int. J. Document Anal. Recognit. 4(2), pp. 109-114, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
OCR, Mathematical morphology, Text segmentation, Document processing, Skew detection |
40 | Oleg Okun, Matti Pietikäinen, Jaakko J. Sauvola |
Document skew estimation without angle range restriction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Document Anal. Recognit. ![In: Int. J. Document Anal. Recognit. 2(2-3), pp. 132-144, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Skew estimation, Image processing, Document image analysis |
40 | Junichi Kanai, Andrew D. Bagdanov |
Projection profile based skew estimation algorithm for JBIG compressed images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Document Anal. Recognit. ![In: Int. J. Document Anal. Recognit. 1(1), pp. 43-51, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Skew estimation, JBIG compression -Document image analysis, Performance evaluation |
40 | B. B. Chaudhuri 0001, U. Pal 0001 |
Skew Angle Detection of Digitized Indian Script Documents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 19(2), pp. 182-186, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
document structure analysis, digital library, optical character recognition (OCR), Document processing, skew detection |
40 | Nadine Rondel, Gilles Burel |
Cooperation of multi-layer perceptrons for the estimation of skew angle in text document images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume II, pp. 1141-1144, 1995, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
skew angle estimation, text document images, sensor array processing technique, three-layer perceptron, maximum likelihood-like optimization, simulated radar data, noisy handwritten texts, optical character recognition, optical character recognition, neural net, multilayer perceptrons |
39 | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Bounded-skew clock and Steiner routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(3), pp. 341-388, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
(inter)connection, boundary merging and embedding, bounded-skew, interior merging and embedding, merging region, merging segment, pathlength delay, VLSI, low power, synchronization, Steiner tree, clock tree, Elmore delay, zero-skew |
38 | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown |
Process-induced skew reduction in nominal zero-skew clock trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 84-89, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Zena M. Ariola, Stefan Blom |
Skew and omega-Skew Confluence and Abstract Böhm Semantics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Processes, Terms and Cycles ![In: Processes, Terms and Cycles: Steps on the Road to Infinity, Essays Dedicated to Jan Willem Klop, on the Occasion of His 60th Birthday, pp. 368-403, 2005, Springer, 3-540-30911-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Lei Wang 0003 |
An energy-efficient skew compensation technique for high-speed skew-sensitive signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1658-1661, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou |
Experimental Evaluation of Resonant Clock Distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 135-140, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Darius Buntinas, Dhabaleswar K. Panda 0001, Ron Brightwell |
Application-Bypas Broadcast in MPICH over GM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 3rd IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2003), 12-15 May 2003, Tokyo, Japan, pp. 2-9, 2003, IEEE Computer Society, 0-7695-1919-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Adam Wagner, Darius Buntinas, Dhabaleswar K. Panda 0001, Ron Brightwell |
Application-Bypass Reduction for Large-Scale Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2003 IEEE International Conference on Cluster Computing (CLUSTER 2003), 1-4 December 2003, Kowloon, Hong Kong, China, pp. 404-411, 2003, IEEE Computer Society, 0-7695-2066-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt |
Statistical analysis of timing rules for high-speed synchronous VLSI systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 477-482, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Ahmed El-Amawy, Priyalal Kulasinghe |
Properties of Generalized Branch and Combine Clock Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(5), pp. 541-546, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
36 | Christoph Lenzen 0001, Thomas Locher, Roger Wattenhofer |
Tight bounds for clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the 28th Annual ACM Symposium on Principles of Distributed Computing, PODC 2009, Calgary, Alberta, Canada, August 10-12, 2009, pp. 46-55, 2009, ACM, 978-1-60558-396-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
gradient property, optimal skew bounds, clock synchronization |
36 | Wei-Chung Chao, Wai-Kei Mak |
Low-power gated and buffered clock network construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 20:1-20:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, buffer, clock gating, Clock tree, zero-skew |
36 | Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen |
IR Drop Reduction via a Flip-Flop Resynthesis Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 78-83, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Peak Current Reduction, IR Drop, Clock Skew Scheduling |
36 | Duc Thanh Nguyen |
A rotation method for binary document images using DDA algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on Document Engineering ![In: Proceedings of the 2008 ACM Symposium on Document Engineering, Sao Paulo, Brazil, September 16-19, 2008, pp. 267-270, 2008, ACM, 978-1-60558-081-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
DDA, rotation algorithm, skew correction |
36 | Sherif A. Tawfik, Volkan Kursun |
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 62-67, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD |
36 | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
Register binding for clock period minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 439-444, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, clock skew, timing optimization |
36 | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown |
Clock buffer and wire sizing using sequential programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1041-1046, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
skew, robust design, clock tree synthesis |
36 | Hendrik Knoche, Hermann de Meer, David Kirsh |
Compensating for low frame rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: Extended Abstracts Proceedings of the 2005 Conference on Human Factors in Computing Systems, CHI 2005, Portland, Oregon, USA, April 2-7, 2005, pp. 1553-1556, 2005, ACM, 1-59593-002-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
audio-visual integration, skew, frame rates, speech perception |
36 | Kai Wang 0011, Malgorzata Marek-Sadowska |
Clock network sizing via sequential linear programming with time-domain analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 182-189, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sequential linear programming, sizing, clock skew, time-domain analysis |
36 | Jiahong Wang, Masatoshi Miyazaki, Hisao Kameda, Jie Li 0002 |
Improving Performance of Parallel Transaction Processing Systems by Balancing Data Load on Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: Seventh International Conference on Parallel and Distributed Systems, ICPADS 2000, Iwate, Japan, July 4-7, 2000, pp. 331-338, 2000, IEEE Computer Society, 0-7695-0568-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
parallel transaction processing, on-line data redistribution, load balancing, Parallel databases, data skew |
36 | Mohamed Nekili, Yvon Savaria, Guy Bois |
Design of Clock Distribution Networks in Presence of Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 95-102, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
process variations, clock skew, clock distribution |
36 | Naresh Maheshwari, Sachin S. Sapatnekar |
A Practical Algorithm for Retiming Level-Clocked Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 440-445, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
level-clocked, retiming, clock skew, timing optimization |
36 | K. Arvind |
Probabilistic Clock Synchronization in Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(5), pp. 474-487, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
distributedsystems, probability of invalidity, deterministicalgorithm, master-slave scheme, time transmission protocol, distributed processing, probability, synchronisation, clock synchronization, probabilistic algorithm, clock skew, synchronization messages |
35 | Maheshwar Umasankar, Ahmed El-Amawy |
Generalized Algorithms for Systematic Synthesis of Branch-and-Combine Clock Networks for Meshes, Tori, and Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(12), pp. 1283-1300, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
skew bound, Branch-and-Combine, feature cycle length, hypercube, mesh, tile, torus, Clock skew, clock network |
35 | Alan Olson, Kang G. Shin |
Fault-Tolerant Clock Synchronization in Large Multicomputer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(9), pp. 912-923, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm |
34 | Arjun Dasgupta, Nan Zhang 0004, Gautam Das 0001 |
Turbo-charging hidden database samplers with overflowing queries and skew reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDBT ![In: EDBT 2010, 13th International Conference on Extending Database Technology, Lausanne, Switzerland, March 22-26, 2010, Proceedings, pp. 51-62, 2010, ACM, 978-1-60558-945-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
34 | Qasim M. Chaudhari, Erchin Serpedin, Khalid A. Qaraqe |
On Maximum Likelihood Estimation of Clock Offset and Skew in Networks With Exponential Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(4), pp. 1685-1697, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Muhammad Sarfraz 0001, Zeehasham Rasheed |
Skew Estimation and Correction of Text Using Bounding Box. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGIV ![In: Fifth International Conference on Computer Graphics, Imaging and Visualization: Modern Techniques and Applications, CGIV 2008, Penang, Malaysia, August 25-28, 2008, pp. 259-264, 2008, IEEE Computer Society, 978-0-7695-3359-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin |
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 224-229, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | An Hu, Fei Yuan |
Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1740-1743, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Risi Kondor, Karsten M. Borgwardt |
The skew spectrum of graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICML ![In: Machine Learning, Proceedings of the Twenty-Fifth International Conference (ICML 2008), Helsinki, Finland, June 5-9, 2008, pp. 496-503, 2008, ACM, 978-1-60558-205-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Delphine Boucher, Willi Geiselmann, Felix Ulmer |
Skew-cyclic codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Algebra Eng. Commun. Comput. ![In: Appl. Algebra Eng. Commun. Comput. 18(4), pp. 379-389, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Cyclic codes, Finite rings |
34 | Shih-Hsu Huang, Yow-Tyng Nieh |
Clock skew scheduling with race conditions considered. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 45, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Sequential circuits, logic synthesis, performance optimization, timing optimization |
34 | Aradhya V. N. Manjunath, Ashok Rao, G. Hemantha Kumar 0001 |
Language Independent Skew Estimation Technique Based on Gaussian Mixture Models: A Case Study on South Indian Scripts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PReMI ![In: Pattern Recognition and Machine Intelligence, Second International Conference, PReMI 2007, Kolkata, India, December 18-22, 2007, Proceedings, pp. 487-494, 2007, Springer, 978-3-540-77045-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino |
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1061-1064, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Vineet Wason, Rajeev Murgai, William W. Walker |
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 271-277, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo |
Analytical bound for unwanted clock skew due to wire width variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1869-1876, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | M. Y. Ashkan, D. S. Guru, P. Punitha 0001 |
Skew Estimation in Persian Documents: A Novel Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGIV ![In: Third International Conference on Computer Graphics, Imaging and Visualization (CGIV 2006), 26-28 July 2006, Sydney, Australia, pp. 64-70, 2006, IEEE Computer Society, 0-7695-2606-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Min-Seok Kim, Jiang Hu |
Associative skew clock routing for difficult instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 762-767, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | B. V. Dhandra, V. S. Malemath, Mallikarjun Hangarge, Ravindra S. Hegadi |
Skew Detection in Binary Image Documents Based on Image Dilation and Region labeling Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR (2) ![In: 18th International Conference on Pattern Recognition (ICPR 2006), 20-24 August 2006, Hong Kong, China, pp. 954-957, 2006, IEEE Computer Society, 0-7695-2521-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Anand Rajaram, David Z. Pan |
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 79-84, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Kai Wang 0011, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska |
General skew constrained clock network sizing based on sequential linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5), pp. 773-782, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Jeng-Liang Tsai, Charlie Chung-Ping Chen |
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1168-1171, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Xiaoguang Li, Ge Yu 0001, Daling Wang, Yubin Bao |
ESPClust: An Effective Skew Prevention Method for Model-Based Document Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICLing ![In: Computational Linguistics and Intelligent Text Processing, 6th International Conference, CICLing 2005, Mexico City, Mexico, February 13-19, 2005, Proceedings, pp. 735-745, 2005, Springer, 3-540-24523-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
Low Cost Scheme for On-Line Clock Skew Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 90-95, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen |
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 565-572, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | P. Shivakumara, G. Hemantha Kumar 0001, D. S. Guru, P. Nagabhushan |
An Efficient Skew Estimation Technique for Binary Document Images Based on Boundary Growing and Linear Regression Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP ![In: Neural Information Processing, 11th International Conference, ICONIP 2004, Calcutta, India, November 22-25, 2004, Proceedings, pp. 659-665, 2004, Springer, 3-540-23931-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu |
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 401-407, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Rishi Chaturvedi, Jiang Hu |
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 282-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta |
A digitally skew correctable multi-phase clock generator using a master-slave DLL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 105-108, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
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