Search results for "skew"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Majdi Ben Hadj Ali	An Object/Segment Oriented Skew-Correction Technique for Document Images.	ICDAR	1997	DBLP DOI BibTeX RDF	Connected components, Skew detection, Skew correction, optical character recognition systems
45	Xin-Wei Shih, Yao-Wen Chang	Fast timing-model independent buffered clock-tree synthesis.	DAC	2010	DBLP DOI BibTeX RDF
45	Fabian Kuhn, Thomas Locher, Rotem Oshman	Gradient clock synchronization in dynamic networks.	SPAA	2009	DBLP DOI BibTeX RDF	distributed algorithms, clock synchronization, dynamic networks
45	Hongyu Chen, Chung-Kuan Cheng	A multi-level transmission line network approach for multi-giga hertz clock distribution.	ASP-DAC	2005	DBLP DOI BibTeX RDF
45	Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri	A novel clock distribution and dynamic de-skewing methodology.	ICCAD	2004	DBLP DOI BibTeX RDF
45	Amith R. Mamidala, Jiuxing Liu, Dhabaleswar K. Panda 0001	Efficient Barrier and Allreduce on Infiniband clusters using multicast and adaptive algorithms.	CLUSTER	2004	DBLP DOI BibTeX RDF
44	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
42	Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Clock skew reduction by self-compensating manufacturing variability with on-chip sensors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	on-chip sensors, self-compensation, clock distribution, manufacturing variability
42	Vinayak Honkote, Baris Taskin	Zero clock skew synchronization with rotary clocking technology.	ISQED	2009	DBLP DOI BibTeX RDF
42	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.	ISQED	2009	DBLP DOI BibTeX RDF
42	Atanu Chattopadhyay, Zeljko Zilic	Built-in Clock Skew System for On-line Debug and Repair.	DATE	2008	DBLP DOI BibTeX RDF
42	Abinash Roy, Masud H. Chowdhury	Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.	ISCAS	2008	DBLP DOI BibTeX RDF
42	Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
42	Lichun Zhang, Yue Lu, Guoyue Chen, Patrick S. P. Wang	Image Skew Detection for Formulas without Fraction Bars Using Connected Components Analysis.	CIT	2007	DBLP DOI BibTeX RDF
42	Sherif A. Tawfik, Volkan Kursun	Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Pingli Huang, Yun Chiu	A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Sherif A. Tawfik, Volkan Kursun	Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.	ISQED	2007	DBLP DOI BibTeX RDF
42	Shih-Hsu Huang, Yow-Tyng Nieh	Synthesis of nonzero clock skew circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
42	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via crosslinks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
42	Ganesh Venkataraman, Jiang Hu, Frank Liu 0001, Cliff C. N. Sze	Integrated placement and skew optimization for rotary clocking.	DATE	2006	DBLP DOI BibTeX RDF
42	Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee	Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.	APCCAS	2006	DBLP DOI BibTeX RDF
42	Dihua Xi, Mohamed Kamel, Seong-Whan Lee	Skew Estimation and Correction for Form Documents Using Wavelet Decomposition.	ICIAR	2005	DBLP DOI BibTeX RDF
42	Adnan Amin, Sue Wu	Robust Skew Detection in mixed Text/Graphics Documents.	ICDAR	2005	DBLP DOI BibTeX RDF
42	Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida	Skew measurements in clock distribution circuits using an analytic signal method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
42	Shih-Hsu Huang, Yow-Tyng Nieh	Clock Period Minimization of Non-Zero Clock Skew Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
42	Sei Hyung Jang	A new synchronous mirror delay with an auto-skew-generation circuit.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
42	Mohamed Nekili, Yvon Savaria, Guy Bois	Minimizing process-induced skew using delay tuning.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
42	Mostafa Bamha, Gaétan Hains	A Skew-insensitive Algorithm for Join and Multi-join Operations on Shared Nothing Machines.	DEXA	2000	DBLP DOI BibTeX RDF
42	Xiaohong Jiang 0001, Susumu Horiguchi	Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model.	DFT	2000	DBLP DOI BibTeX RDF
42	Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas	Impact of interconnect variations on the clock skew of a gigahertz microprocessor.	DAC	2000	DBLP DOI BibTeX RDF
42	Ivan S. Kourtev, Eby G. Friedman	Clock skew scheduling for improved reliability via quadratic programming.	ICCAD	1999	DBLP DOI BibTeX RDF
42	Andrew V. Goldberg, Alexander V. Karzanov	Maximum Skew-Symmetric Flows.	ESA	1995	DBLP DOI BibTeX RDF
42	Jae Chung, Chung-Kuan Cheng	Skew sensitivity minimization of buffered clock tree.	ICCAD	1994	DBLP DOI BibTeX RDF
42	Shen Lin, C. K. Wong	Process-variation-tolerant clock skew minimization.	ICCAD	1994	DBLP DOI BibTeX RDF
42	Ren-Song Tsay	An exact zero-skew clock routing algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
42	Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Yazawa, Teruo Tanaka, Yasuhiro Inagami, Yoshiko Tamaki	Scalable Parallel Memory Architecture with a Skew Scheme.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF	ILLIAC IV
40	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
40	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Power efficient tree-based crosslinks for skew reduction.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	crosslink, non-tree clock distribution network, power, mesh, skew, clock tree
40	Yi Wang, Wai-Shing Luk, Xuan Zeng 0001, Jun Tao 0001, Changhao Yan, Jiarong Tong, Wei Cai 0003, Jia Ni	Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.	DAC	2008	DBLP DOI BibTeX RDF	non-Gaussian, process variations, yield, clock skew scheduling
40	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
40	Charbel J. Akl, Magdy A. Bayoumi	Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transition skew coding, global on-chip interconnects, bus encoding technique, encoding latencies, decoding latencies, 90 nm
40	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Dynamic thermal clock skew compensation using tunable delay buffers.	ISLPED	2006	DBLP DOI BibTeX RDF	temperature aware design methodology, tunable delay buffers, clock skew, clock tree
40	David Camarero, Jean-François Naviner, Patrick Loumeau	Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters.	SBCCI	2004	DBLP DOI BibTeX RDF	digital calibration, parallel ADC, sample-time errors, time-interleaved, adaptive filters, clock skew
40	Yu-lung Lo, Yu-chen Huang	Effective Skew Handling for Parallel Sorting in Multiprocessor Database Systems.	ICPADS	2002	DBLP DOI BibTeX RDF	Load Balancing, Parallel Sort, Data Skew
40	Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao	Power Supply Noise Suppression via Clock Skew Scheduling.	ISQED	2002	DBLP DOI BibTeX RDF	Skew Scheduling, Power noise, Clock
40	Baris Taskin, Ivan S. Kourtev	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	optimization, linear programming, clock skew, cycle stealing
40	Amit Kumar Das 0001, Bhabatosh Chanda	A fast algorithm for skew detection of document images using morphology.	Int. J. Document Anal. Recognit.	2001	DBLP DOI BibTeX RDF	OCR, Mathematical morphology, Text segmentation, Document processing, Skew detection
40	Oleg Okun, Matti Pietikäinen, Jaakko J. Sauvola	Document skew estimation without angle range restriction.	Int. J. Document Anal. Recognit.	1999	DBLP DOI BibTeX RDF	Skew estimation, Image processing, Document image analysis
40	Junichi Kanai, Andrew D. Bagdanov	Projection profile based skew estimation algorithm for JBIG compressed images.	Int. J. Document Anal. Recognit.	1998	DBLP DOI BibTeX RDF	Skew estimation, JBIG compression -Document image analysis, Performance evaluation
40	B. B. Chaudhuri 0001, U. Pal 0001	Skew Angle Detection of Digitized Indian Script Documents.	IEEE Trans. Pattern Anal. Mach. Intell.	1997	DBLP DOI BibTeX RDF	document structure analysis, digital library, optical character recognition (OCR), Document processing, skew detection
40	Nadine Rondel, Gilles Burel	Cooperation of multi-layer perceptrons for the estimation of skew angle in text document images.	ICDAR	1995	DBLP DOI BibTeX RDF	skew angle estimation, text document images, sensor array processing technique, three-layer perceptron, maximum likelihood-like optimization, simulated radar data, noisy handwritten texts, optical character recognition, optical character recognition, neural net, multilayer perceptrons
39	Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao	Bounded-skew clock and Steiner routing.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	(inter)connection, boundary merging and embedding, bounded-skew, interior merging and embedding, merging region, merging segment, pathlength delay, VLSI, low power, synchronization, Steiner tree, clock tree, Elmore delay, zero-skew
38	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Process-induced skew reduction in nominal zero-skew clock trees.	ASP-DAC	2006	DBLP DOI BibTeX RDF
38	Zena M. Ariola, Stefan Blom	Skew and omega-Skew Confluence and Abstract Böhm Semantics.	Processes, Terms and Cycles	2005	DBLP DOI BibTeX RDF
38	Lei Wang 0003	An energy-efficient skew compensation technique for high-speed skew-sensitive signaling.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
37	Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou	Experimental Evaluation of Resonant Clock Distribution.	ISVLSI	2004	DBLP DOI BibTeX RDF
37	Darius Buntinas, Dhabaleswar K. Panda 0001, Ron Brightwell	Application-Bypas Broadcast in MPICH over GM.	CCGRID	2003	DBLP DOI BibTeX RDF
37	Adam Wagner, Darius Buntinas, Dhabaleswar K. Panda 0001, Ron Brightwell	Application-Bypass Reduction for Large-Scale Clusters.	CLUSTER	2003	DBLP DOI BibTeX RDF
37	Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt	Statistical analysis of timing rules for high-speed synchronous VLSI systems.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
37	Ahmed El-Amawy, Priyalal Kulasinghe	Properties of Generalized Branch and Combine Clock Networks.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
36	Christoph Lenzen 0001, Thomas Locher, Roger Wattenhofer	Tight bounds for clock synchronization.	PODC	2009	DBLP DOI BibTeX RDF	gradient property, optimal skew bounds, clock synchronization
36	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
36	Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen	IR Drop Reduction via a Flip-Flop Resynthesis Technique.	ISQED	2008	DBLP DOI BibTeX RDF	Peak Current Reduction, IR Drop, Clock Skew Scheduling
36	Duc Thanh Nguyen	A rotation method for binary document images using DDA algorithm.	ACM Symposium on Document Engineering	2008	DBLP DOI BibTeX RDF	DDA, rotation algorithm, skew correction
36	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
36	Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu	Register binding for clock period minimization.	DAC	2006	DBLP DOI BibTeX RDF	high-level synthesis, clock skew, timing optimization
36	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Clock buffer and wire sizing using sequential programming.	DAC	2006	DBLP DOI BibTeX RDF	skew, robust design, clock tree synthesis
36	Hendrik Knoche, Hermann de Meer, David Kirsh	Compensating for low frame rates.	CHI Extended Abstracts	2005	DBLP DOI BibTeX RDF	audio-visual integration, skew, frame rates, speech perception
36	Kai Wang 0011, Malgorzata Marek-Sadowska	Clock network sizing via sequential linear programming with time-domain analysis.	ISPD	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew, time-domain analysis
36	Jiahong Wang, Masatoshi Miyazaki, Hisao Kameda, Jie Li 0002	Improving Performance of Parallel Transaction Processing Systems by Balancing Data Load on Line.	ICPADS	2000	DBLP DOI BibTeX RDF	parallel transaction processing, on-line data redistribution, load balancing, Parallel databases, data skew
36	Mohamed Nekili, Yvon Savaria, Guy Bois	Design of Clock Distribution Networks in Presence of Process Variations.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	process variations, clock skew, clock distribution
36	Naresh Maheshwari, Sachin S. Sapatnekar	A Practical Algorithm for Retiming Level-Clocked Circuits.	ICCD	1996	DBLP DOI BibTeX RDF	level-clocked, retiming, clock skew, timing optimization
36	K. Arvind	Probabilistic Clock Synchronization in Distributed Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	distributedsystems, probability of invalidity, deterministicalgorithm, master-slave scheme, time transmission protocol, distributed processing, probability, synchronisation, clock synchronization, probabilistic algorithm, clock skew, synchronization messages
35	Maheshwar Umasankar, Ahmed El-Amawy	Generalized Algorithms for Systematic Synthesis of Branch-and-Combine Clock Networks for Meshes, Tori, and Hypercubes.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	skew bound, Branch-and-Combine, feature cycle length, hypercube, mesh, tile, torus, Clock skew, clock network
35	Alan Olson, Kang G. Shin	Fault-Tolerant Clock Synchronization in Large Multicomputer Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm
34	Arjun Dasgupta, Nan Zhang 0004, Gautam Das 0001	Turbo-charging hidden database samplers with overflowing queries and skew reduction.	EDBT	2010	DBLP DOI BibTeX RDF
34	Qasim M. Chaudhari, Erchin Serpedin, Khalid A. Qaraqe	On Maximum Likelihood Estimation of Clock Offset and Skew in Networks With Exponential Delays.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
34	Muhammad Sarfraz 0001, Zeehasham Rasheed	Skew Estimation and Correction of Text Using Bounding Box.	CGIV	2008	DBLP DOI BibTeX RDF
34	Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
34	An Hu, Fei Yuan	Inter-signal timing skew compensation of parallel links with voltage-mode incremental signaling.	ISCAS	2008	DBLP DOI BibTeX RDF
34	Risi Kondor, Karsten M. Borgwardt	The skew spectrum of graphs.	ICML	2008	DBLP DOI BibTeX RDF
34	Delphine Boucher, Willi Geiselmann, Felix Ulmer	Skew-cyclic codes.	Appl. Algebra Eng. Commun. Comput.	2007	DBLP DOI BibTeX RDF	Cyclic codes, Finite rings
34	Shih-Hsu Huang, Yow-Tyng Nieh	Clock skew scheduling with race conditions considered.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Sequential circuits, logic synthesis, performance optimization, timing optimization
34	Aradhya V. N. Manjunath, Ashok Rao, G. Hemantha Kumar 0001	Language Independent Skew Estimation Technique Based on Gaussian Mixture Models: A Case Study on South Indian Scripts.	PReMI	2007	DBLP DOI BibTeX RDF
34	Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino	Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Vineet Wason, Rajeev Murgai, William W. Walker	An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
34	Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo	Analytical bound for unwanted clock skew due to wire width variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
34	M. Y. Ashkan, D. S. Guru, P. Punitha 0001	Skew Estimation in Persian Documents: A Novel Approach.	CGIV	2006	DBLP DOI BibTeX RDF
34	Min-Seok Kim, Jiang Hu	Associative skew clock routing for difficult instances.	DATE	2006	DBLP DOI BibTeX RDF
34	B. V. Dhandra, V. S. Malemath, Mallikarjun Hangarge, Ravindra S. Hegadi	Skew Detection in Binary Image Documents Based on Image Dilation and Region labeling Approach.	ICPR (2)	2006	DBLP DOI BibTeX RDF
34	Anand Rajaram, David Z. Pan	Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction.	ISQED	2006	DBLP DOI BibTeX RDF
34	Kai Wang 0011, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska	General skew constrained clock network sizing based on sequential linear programming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
34	Jeng-Liang Tsai, Charlie Chung-Ping Chen	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Xiaoguang Li, Ge Yu 0001, Daling Wang, Yubin Bao	ESPClust: An Effective Skew Prevention Method for Model-Based Document Clustering.	CICLing	2005	DBLP DOI BibTeX RDF
34	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Low Cost Scheme for On-Line Clock Skew Compensation.	VTS	2005	DBLP DOI BibTeX RDF
34	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
34	P. Shivakumara, G. Hemantha Kumar 0001, D. S. Guru, P. Nagabhushan	An Efficient Skew Estimation Technique for Binary Document Images Based on Boundary Growing and Linear Regression Analysis.	ICONIP	2004	DBLP DOI BibTeX RDF
34	Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu	Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.	ICCAD	2003	DBLP DOI BibTeX RDF
34	Rishi Chaturvedi, Jiang Hu	A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.	ICCD	2003	DBLP DOI BibTeX RDF
34	Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta	A digitally skew correctable multi-phase clock generator using a master-slave DLL.	ISCAS (1)	2003	DBLP DOI BibTeX RDF