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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1160 occurrences of 532 keywords
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Results
Found 1093 publication records. Showing 1093 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
34 | Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans |
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 163-172, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | D. K. Arvind 0001, Robert D. Mullins |
A Fully Asynchronous Superscalar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 17-22, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Andrew Wolfe, Derek B. Noonburg |
A Superscalar 3D Graphics Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 50-61, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath |
The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 256-275, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Eliseu M. Chaves Filho, Edil S. T. Fernandes |
The Effect of the Speculation Depth on the Performance of Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 1061-1065, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Sriram Vajapeyam, Tulika Mitra |
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 1-12, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Ulrich Sigmund, Theo Ungerer |
Identifying Bottlenecks in a Multithreaded Superscalar Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 797-800, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
34 | Derek B. Noonburg, John Paul Shen |
Theoretical modeling of superscalar processor performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 52-62, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Mauricio J. Serrano, Wayne Yamamoto, Roger C. Wood, Mario Nemirovsky |
A Model for Performance Estimation in a Multistreamed Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Performance Evaluation ![In: Computer Performance Evaluation, Modeling Techniques and Tools, 7th International Conference, Vienna, Austria, May 3-6, 1994, Proceedings, pp. 213-230, 1994, Springer, 3-540-58021-2. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker |
Sentinel Scheduling for VLIW and Superscalar Processors. (long version: TOCS 11(4): 376-408) ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-V Proceedings - Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, October 12-15, 1992., pp. 238-247, 1992, ACM Press, 0-89791-534-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Yen-Jen Oyang |
Exploiting multi-way branching to boost superscalar processor performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 26(3), pp. 68-78, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
34 | Pradeep K. Dubey, George B. Adams III, Michael J. Flynn |
Spectrum of choices: superpipelined, superscalar, or multiprocessor? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, SPDP 1991, 2-5 December 1991, Dallas, Texas, USA, pp. 233-240, 1991, IEEE Computer Society, 0-8186-2310-1. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
34 | Ali Mustafa Zaidi, David J. Greaves |
Achieving Superscalar Performance without Superscalar Overheads - A Dataflow Compiler IR for Custom Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSW ![In: 2013 Imperial College Computing Student Workshop, ICCSW 2013, September 26/27, 2013, London, United Kingdom, pp. 136-143, 2013, Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, 978-3-939897-63-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita |
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 19(4), pp. 14-29, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
32 | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001 |
A Top-Down Approach to Architecting CPI Component Performance Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(1), pp. 84-93, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hardware performance counter architecture, superscalar processor performance modeling, performance, measurement, experimentation, modeling techniques |
32 | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001 |
A performance counter architecture for computing accurate CPI components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 175-184, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hardware performance counter architecture, superscalar processor performance modeling |
32 | Kenneth M. Wilson, Kunle Olukotun |
High Bandwidth On-Chip Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 292-307, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth |
32 | Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose |
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 90-101, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling |
32 | Isak Jonsson, Bo Kågström |
Parallel Triangular Sylvester-Type Matrix Equation Solvers for SMP Systems Using Recursive Blocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing, New Paradigms for HPC in Industry and Academia, 5th International Workshop, PARA 2000 Bergen, Norway, June 18-20, 2000 Proceedings, pp. 64-73, 2000, Springer, 3-540-41729-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Sylvester-type matrix equations, recursion, superscalar, level 3 BLAS, GEMM-based, automatic blocking |
32 | Kiyeon Lee, Sangyeun Cho |
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2011, 19th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Singapore, 25-27 July, 2011, pp. 126-135, 2011, IEEE Computer Society, 978-1-4577-0468-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Superscalar out-of-order processor, performance modeling, trace-driven simulation |
32 | Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao |
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(1), pp. 4-20, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures |
32 | Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev 0001, Peter M. Kogge |
Energy: efficient instruction dispatch buffer design for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 237-242, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
bitline segmentation, low power comparator, low power instruction scheduling, low-power superscalar datapath |
32 | Meng-chou Chang, Feipei Lai |
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(3), pp. 278-293, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors |
32 | Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai |
A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(7), pp. 891-902, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CPI, operand cache, object compatibility, performance, pipeline, RISC, superscalar, CPU, OLTP, hardware cost, CISC, mainframe computer, Arithmetic unit |
32 | C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven |
Hades-towards the design of an asynchronous superscalar processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 200-209, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design |
32 | Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore |
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 196-203, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz |
32 | Eric Sprangle, Yale N. Patt |
Facilitating superscalar processing via a combined static/dynamic register renaming scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 143-147, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
superscalar processors, out-of-order execution, register renaming, predicated execution |
32 | Soo-Mook Moon, Kemal Ebcioglu |
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992, pp. 55-71, 1992, ACM / IEEE Computer Society, 0-8186-3175-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
compile-time parallelization, instruction-level parallelism, VLIW, superscalar |
25 | James Laudon, Lawrence Spracklen |
The Coming Wave of Multithreaded Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(3), pp. 299-330, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, parallel programming, multithreading, Chip multiprocessing |
25 | Ali R. Iranpour, Krzysztof Kuchcinski |
Performance Improvement for H.264 Video Encoding using ILP Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 515-521, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | David Wentzlaff, Anant Agarwal |
Constructing Virtual Architectures on a Tiled Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 26-29 March 2006, New York, New York, USA, pp. 173-184, 2006, IEEE Computer Society, 0-7695-2499-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Ryuichi Takahashi, Hajime Ohiwa |
Legitimate Peripheral Participation on FPGA for Fine-Grain Microprocessor Design Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 99-100, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | You-Jan Tsai, Jong-Jiann Shieh |
Speculative Issue Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 323-335, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Leonid Oliker, Jonathan Carter, Michael F. Wehner, Andrew Canning, Stéphane Ethier, Arthur A. Mirin, David Parks, Patrick H. Worley, Shigemune Kitawaki, Yoshinori Tsuda |
Leading Computational Methods on Scalar and Vector HEC Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 62, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Hongzhang Shan, Erich Strohmaier |
Performance characteristics of the Cray X1 and their implications for application performance tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004, pp. 175-183, 2004, ACM, 1-58113-839-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance measurement, performance optimization, vector processing, performance characterization |
25 | A. Murat Fiskiran, Ruby B. Lee |
Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 125-136, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | T. N. Vijaykumar, Zeshan Chishti |
Wire Delay is Not a Problem for SMT (In the Near Future). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 40-51, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | John Patrick McGregor, Ruby B. Lee |
Architectural techniques for accelerating subword permutations with repetitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 325-335, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Chen-Yong Cher, T. N. Vijaykumar |
Skipper: a microarchitecture for exploiting control-flow independence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 4-15, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Anthony C. J. Fox, Neal A. Harman |
Algebraic Models of Correctness for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 12(4), pp. 298-312, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Formal Verification, Microprocessors, Algebraic Models |
25 | Artur Klauser, Abhijit Paithankar, Dirk Grunwald |
Selective Eager Execution on the PolyPath Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 250-259, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Corinna G. Lee, Derek J. DeVries |
Initial Results on the Performance and Cost of Vector Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 171-182, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm |
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 191-202, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Pradeep K. Dubey, George B. Adams III, Michael J. Flynn |
Evaluating Performance Tradeoffs Between Fine-Grained and Coarse-Grained Alternatives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(1), pp. 17-27, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz |
Enhanced LEON3 core for superscalar processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 238-241, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Stijn Eyerman, Lieven Eeckhout, James E. Smith 0001 |
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 114-129, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Sven van Haastregt, Peter M. W. Knijnenburg |
Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 606-611, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Andrew Lines |
The Vortex: A Superscalar Asynchronous Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA, pp. 39-48, 2007, IEEE Computer Society, 978-0-7695-2771-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni |
On the latency, energy and area of checkpointed, superscalar register alias tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 379-382, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
latency, checkpointing, energy, register renaming |
25 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López |
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 423-432, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Hai Li 0001, Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh |
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 158-163, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Nick A. Mould, Brian F. Veale, Monte P. Tull, John K. Antonio |
Dynamic configuration steering for a reconfigurable superscalar processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Junwei Zhou, Andrew J. Mason |
A two-level hybrid select logic for wide-issue superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Clint W. Smullen, Tarek M. Taha |
PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2006 Workshop on Computer Architecture Education, WCAE 2006, Boston, Massachusetts, USA, Saturday, June 17, 2006, pp. 3, 2006, ACM, 978-1-4503-4735-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar |
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 40-48, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Yongxin Zhu 0001, Weng-Fai Wong, Stefan Andrei |
An integrated performance and power model for superscalar processor designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 948-951, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Brian F. Veale, John K. Antonio, Monte P. Tull |
Configuration Steering for a Reconfigurable Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Christine Rochange, Pascal Sainrat |
A time-predictable execution mode for superscalar pipelines with instruction prescheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 307-314, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
real-time, pipeline, WCET, processor architecture |
25 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Energy Efficient Comparators for Superscalar Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 892-904, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero |
A low-complexity fetch architecture for high-performance superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(2), pp. 220-245, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fetch architecture, instruction stream, high performance, Branch prediction, low complexity |
25 | Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour |
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(5), pp. 553-567, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
COTS processors, fault injection, performance monitoring, analytical evaluation, watchdog processor, error detection coverage |
25 | Carlo Brandolese, William Fornaciari, Fabio Salice |
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 238-247, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Aneesh Aggarwal |
Single FU Bypass Networks for High Clock Rate Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2004, 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings, pp. 319-332, 2004, Springer, 3-540-24129-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Juan Rubio 0001, Lizy Kurian John |
Analysis of the Execution of a Next Generation Application on Superscalar and Grid Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 10th International Conference on Parallel and Distributed Systems, ICPADS 2004, Newport Beach, CA, USA, July 7-9, 2004, pp. 307-314, 2004, IEEE Computer Society, 0-7695-2152-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Amir Rajabzadeh, Mirzad Mohandespour, Seyed Ghassem Miremadi |
Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 3-5 March 2004, Papeete, Tahiti, pp. 49-54, 2004, IEEE Computer Society, 0-7695-2076-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Yue Luo, Juan Rubio 0001, Lizy Kurian John, Pattabi Seshadri, Alex E. Mericas |
Benchmarking Internet Servers on Superscalar Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 36(2), pp. 34-40, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Kenneth K. C. Lee, Karl-Erwin Großpietsch, Y. K. Chan |
An Alternative Superscalar Architecture with Integer Execution Units Only. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Programming Technologies, 5th International Workshop, APPT 2003, Xiamen, China, September 17-19, 2003, Proceedings, pp. 57-65, 2003, Springer, 3-540-20054-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Miroslav N. Velev |
Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 138-147, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Leonid Oliker, Andrew Canning, Jonathan Carter, John Shalf, David Skinner, Stéphane Ethier, Rupak Biswas, M. Jahed Djomehri, Rob F. Van der Wijngaart |
Evaluation of Cache-based Superscalar and Cacheless Vector Architectures for Scientific Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2003 Conference on High Performance Networking and Computing, 15-21 November 2003, Phoenix, AZ, USA, CD-Rom, pp. 38, 2003, ACM, 1-58113-695-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose |
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 124-129, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera |
Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 218-225, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Gabriel H. Loh |
Exploiting data-width locality to increase superscalar execution bandwidth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 395-405, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Chee How Lim, W. Robert Daasch, George Cai |
A Thermal-Aware Superscalar Microprocessor (invited). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 517-522, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Sébastien Nussbaum, James E. Smith 0001 |
Modeling Superscalar Processors via Statistical Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 15-24, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi |
Reducing the complexity of the register file in dynamic superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 237-248, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Mauro Olivieri |
A genetic approach to the design space exploration of superscalar microprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 69-72, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Jian Huang, David J. Lilja |
Exploring Sub-Block Value Reuse for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 100-110, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Yong Zhang, Min Zhang |
A Novel Superscalar Architecture for Fast DCT Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 171-177, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Xianfeng Zhou, Margaret Martonosi |
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 941-950, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis |
Counter Based Superscalar Instruction Issuing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1307-1315, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami |
Circuits for wide-window superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 236-247, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Jörn Schneider, Christian Ferdinand |
Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, and Tools for Embedded Systems ![In: Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'99), Atlanta, Georgia, USA, May 5, 1999, pp. 35-44, 1999, ACM, 1-58113-136-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | José González 0002, Antonio González 0001 |
Control-Flow Speculation through Value Prediction for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 57-65, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Path-based Selector, Branch Prediction, Value Prediction, Hybrid predictor |
25 | Alan Pita, Nadeem Malik |
Sectored renaming for superscalar microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the IEEE International Performance Computing and Communications Conference, IPCCC 1999, Phoenix/Scottsdale, Arizona, USA, 10-12 February 1999, pp. 59-64, 1999, IEEE, 0-7803-5258-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada |
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 279-280, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch |
25 | Sangyeun Cho, Pen-Chung Yew, Gyungho Lee |
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 100-110, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Omar Hammami |
Performance Impacts of Superscalar Microarchitecture on SOM Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 31st Annual Simulation Symposium (SS '98), 5-9 April 1998, Boston, MA, USA, pp. 202-209, 1998, IEEE Computer Society, 0-8186-8418-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Sorin Cotofana, Stamatis Vassiliadis |
On the Design Complexity of the Issue Logic of Superscalar Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10277-10284, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey |
Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 638-643, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
21264, coverage anaysis, verification, architecture, validation, microprocessor, pseudo-random, Alpha |
25 | Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura |
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 246-249, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
25 | James J. Carrig Jr., Gerard G. L. Meyer |
Efficient Householder QR Factorization for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 23(3), pp. 362-378, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Householder QR factorization, register model, cache model |
25 | Derek B. Noonburg, John Paul Shen |
A Framework for Statistical Modeling of Superscalar Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 298-309, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Craig S. K. Clapp |
Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSE ![In: Fast Software Encryption, 4th International Workshop, FSE '97, Haifa, Israel, January 20-22, 1997, Proceedings, pp. 273-287, 1997, Springer, 3-540-63247-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Unnikrishnan R. Nair, Donna J. Quammen, Daniel Tabak |
Superscalar Extension for the Multris Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 482-486, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Subbarao Palacharla, Norman P. Jouppi, James E. Smith 0001 |
Complexity-Effective Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 206-218, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Anne M. Holler |
Optimization for a Superscalar Out-of-Order Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 336-348, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Steven Wallace, Nader Bagherzadeh |
Instruction Fetching Mechanisms for Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 747-756, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Richard D. Potter, Gordon B. Steven |
Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 779-788, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe |
Functionality Distribution on a Superscalar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 773-778, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Stéphan Jourdan, Pascal Sainrat, Daniel Litaize |
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 117-125, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
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