Search results for "superscalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans	Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures.	ICCD	2000	DBLP DOI BibTeX RDF
34	D. K. Arvind 0001, Robert D. Mullins	A Fully Asynchronous Superscalar Architecture.	IEEE PACT	1999	DBLP DOI BibTeX RDF
34	Andrew Wolfe, Derek B. Noonburg	A Superscalar 3D Graphics Engine.	MICRO	1999	DBLP DOI BibTeX RDF
34	Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath	The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture.	ARVLSI	1999	DBLP DOI BibTeX RDF
34	Eliseu M. Chaves Filho, Edil S. T. Fernandes	The Effect of the Speculation Depth on the Performance of Superscalar Architectures.	Euro-Par	1997	DBLP DOI BibTeX RDF
34	Sriram Vajapeyam, Tulika Mitra	Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences.	ISCA	1997	DBLP DOI BibTeX RDF
34	Ulrich Sigmund, Theo Ungerer	Identifying Bottlenecks in a Multithreaded Superscalar Microprocessor.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
34	Derek B. Noonburg, John Paul Shen	Theoretical modeling of superscalar processor performance.	MICRO	1994	DBLP DOI BibTeX RDF
34	Mauricio J. Serrano, Wayne Yamamoto, Roger C. Wood, Mario Nemirovsky	A Model for Performance Estimation in a Multistreamed Superscalar Processor.	Computer Performance Evaluation	1994	DBLP DOI BibTeX RDF
34	Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors. (long version: TOCS 11(4): 376-408)	ASPLOS	1992	DBLP DOI BibTeX RDF
34	Yen-Jen Oyang	Exploiting multi-way branching to boost superscalar processor performance.	ACM SIGPLAN Notices	1991	DBLP DOI BibTeX RDF
34	Pradeep K. Dubey, George B. Adams III, Michael J. Flynn	Spectrum of choices: superpipelined, superscalar, or multiprocessor?	SPDP	1991	DBLP DOI BibTeX RDF
34	Ali Mustafa Zaidi, David J. Greaves	Achieving Superscalar Performance without Superscalar Overheads - A Dataflow Compiler IR for Custom Computing.	ICCSW	2013	DBLP DOI BibTeX RDF
34	Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita	DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture.	SIGARCH Comput. Archit. News	1991	DBLP DOI BibTeX RDF
32	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A Top-Down Approach to Architecting CPI Component Performance Counters.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware performance counter architecture, superscalar processor performance modeling, performance, measurement, experimentation, modeling techniques
32	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A performance counter architecture for computing accurate CPI components.	ASPLOS	2006	DBLP DOI BibTeX RDF	hardware performance counter architecture, superscalar processor performance modeling
32	Kenneth M. Wilson, Kunle Olukotun	High Bandwidth On-Chip Cache Design.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth
32	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.	MICRO	2001	DBLP DOI BibTeX RDF	energy-efficient datapath, superscalar processor, power reduction, dynamic instruction scheduling
32	Isak Jonsson, Bo Kågström	Parallel Triangular Sylvester-Type Matrix Equation Solvers for SMP Systems Using Recursive Blocking.	PARA	2000	DBLP DOI BibTeX RDF	Sylvester-type matrix equations, recursion, superscalar, level 3 BLAS, GEMM-based, automatic blocking
32	Kiyeon Lee, Sangyeun Cho	In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces.	MASCOTS	2011	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, performance modeling, trace-driven simulation
32	Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures
32	Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev 0001, Peter M. Kogge	Energy: efficient instruction dispatch buffer design for superscalar processors.	ISLPED	2001	DBLP DOI BibTeX RDF	bitline segmentation, low power comparator, low power instruction scheduling, low-power superscalar datapath
32	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
32	Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai	A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	CPI, operand cache, object compatibility, performance, pipeline, RISC, superscalar, CPU, OLTP, hardware cost, CISC, mainframe computer, Arithmetic unit
32	C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven	Hades-towards the design of an asynchronous superscalar processor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design
32	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
32	Eric Sprangle, Yale N. Patt	Facilitating superscalar processing via a combined static/dynamic register renaming scheme.	MICRO	1994	DBLP DOI BibTeX RDF	superscalar processors, out-of-order execution, register renaming, predicated execution
32	Soo-Mook Moon, Kemal Ebcioglu	An efficient resource-constrained global scheduling technique for superscalar and VLIW processors.	MICRO	1992	DBLP DOI BibTeX RDF	compile-time parallelization, instruction-level parallelism, VLIW, superscalar
25	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
25	Ali R. Iranpour, Krzysztof Kuchcinski	Performance Improvement for H.264 Video Encoding using ILP Embedded Processor.	DSD	2006	DBLP DOI BibTeX RDF
25	David Wentzlaff, Anant Agarwal	Constructing Virtual Architectures on a Tiled Processor.	CGO	2006	DBLP DOI BibTeX RDF
25	Ryuichi Takahashi, Hajime Ohiwa	Legitimate Peripheral Participation on FPGA for Fine-Grain Microprocessor Design Education.	MSE	2005	DBLP DOI BibTeX RDF
25	You-Jan Tsai, Jong-Jiann Shieh	Speculative Issue Logic.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
25	Leonid Oliker, Jonathan Carter, Michael F. Wehner, Andrew Canning, Stéphane Ethier, Arthur A. Mirin, David Parks, Patrick H. Worley, Shigemune Kitawaki, Yoshinori Tsuda	Leading Computational Methods on Scalar and Vector HEC Platforms.	SC	2005	DBLP DOI BibTeX RDF
25	Hongzhang Shan, Erich Strohmaier	Performance characteristics of the Cray X1 and their implications for application performance tuning.	ICS	2004	DBLP DOI BibTeX RDF	performance measurement, performance optimization, vector processing, performance characterization
25	A. Murat Fiskiran, Ruby B. Lee	Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields.	ASAP	2004	DBLP DOI BibTeX RDF
25	T. N. Vijaykumar, Zeshan Chishti	Wire Delay is Not a Problem for SMT (In the Near Future).	ISCA	2004	DBLP DOI BibTeX RDF
25	John Patrick McGregor, Ruby B. Lee	Architectural techniques for accelerating subword permutations with repetitions.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
25	Chen-Yong Cher, T. N. Vijaykumar	Skipper: a microarchitecture for exploiting control-flow independence.	MICRO	2001	DBLP DOI BibTeX RDF
25	Anthony C. J. Fox, Neal A. Harman	Algebraic Models of Correctness for Microprocessors.	Formal Aspects Comput.	2000	DBLP DOI BibTeX RDF	Formal Verification, Microprocessors, Algebraic Models
25	Artur Klauser, Abhijit Paithankar, Dirk Grunwald	Selective Eager Execution on the PolyPath Architecture.	ISCA	1998	DBLP DOI BibTeX RDF
25	Corinna G. Lee, Derek J. DeVries	Initial Results on the Performance and Cost of Vector Microprocessors.	MICRO	1997	DBLP DOI BibTeX RDF
25	Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm	Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.	ISCA	1996	DBLP DOI BibTeX RDF
25	Pradeep K. Dubey, George B. Adams III, Michael J. Flynn	Evaluating Performance Tradeoffs Between Fine-Grained and Coarse-Grained Alternatives.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
25	Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz	Enhanced LEON3 core for superscalar processing.	DDECS	2009	DBLP DOI BibTeX RDF
25	Stijn Eyerman, Lieven Eeckhout, James E. Smith 0001	Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.	HiPEAC	2008	DBLP DOI BibTeX RDF
25	Sven van Haastregt, Peter M. W. Knijnenburg	Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search.	DATE	2007	DBLP DOI BibTeX RDF
25	Andrew Lines	The Vortex: A Superscalar Asynchronous Processor.	ASYNC	2007	DBLP DOI BibTeX RDF
25	Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni	On the latency, energy and area of checkpointed, superscalar register alias tables.	ISLPED	2007	DBLP DOI BibTeX RDF	latency, checkpointing, energy, register renaming
25	José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López	Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.	DSD	2006	DBLP DOI BibTeX RDF
25	Hai Li 0001, Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
25	Nick A. Mould, Brian F. Veale, Monte P. Tull, John K. Antonio	Dynamic configuration steering for a reconfigurable superscalar processor.	IPDPS	2006	DBLP DOI BibTeX RDF
25	Junwei Zhou, Andrew J. Mason	A two-level hybrid select logic for wide-issue superscalar processors.	ISCAS	2006	DBLP DOI BibTeX RDF
25	Clint W. Smullen, Tarek M. Taha	PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis.	WCAE	2006	DBLP DOI BibTeX RDF
25	Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar	Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.	PATMOS	2005	DBLP DOI BibTeX RDF
25	Yongxin Zhu 0001, Weng-Fai Wong, Stefan Andrei	An integrated performance and power model for superscalar processor designs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Brian F. Veale, John K. Antonio, Monte P. Tull	Configuration Steering for a Reconfigurable Superscalar Processor.	IPDPS	2005	DBLP DOI BibTeX RDF
25	Christine Rochange, Pascal Sainrat	A time-predictable execution mode for superscalar pipelines with instruction prescheduling.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	real-time, pipeline, WCET, processor architecture
25	Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Energy Efficient Comparators for Superscalar Datapaths.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
25	Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	A low-complexity fetch architecture for high-performance superscalar processors.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	fetch architecture, instruction stream, high performance, Branch prediction, low complexity
25	Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour	Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	COTS processors, fault injection, performance monitoring, analytical evaluation, watchdog processor, error detection coverage
25	Carlo Brandolese, William Fornaciari, Fabio Salice	Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.	PATMOS	2004	DBLP DOI BibTeX RDF
25	Aneesh Aggarwal	Single FU Bypass Networks for High Clock Rate Superscalar Processors.	HiPC	2004	DBLP DOI BibTeX RDF
25	Juan Rubio 0001, Lizy Kurian John	Analysis of the Execution of a Next Generation Application on Superscalar and Grid Processors.	ICPADS	2004	DBLP DOI BibTeX RDF
25	Amir Rajabzadeh, Mirzad Mohandespour, Seyed Ghassem Miremadi	Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features.	PRDC	2004	DBLP DOI BibTeX RDF
25	Yue Luo, Juan Rubio 0001, Lizy Kurian John, Pattabi Seshadri, Alex E. Mericas	Benchmarking Internet Servers on Superscalar Machines.	Computer	2003	DBLP DOI BibTeX RDF
25	Kenneth K. C. Lee, Karl-Erwin Großpietsch, Y. K. Chan	An Alternative Superscalar Architecture with Integer Execution Units Only.	APPT	2003	DBLP DOI BibTeX RDF
25	Miroslav N. Velev	Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs.	ITC	2003	DBLP DOI BibTeX RDF
25	Leonid Oliker, Andrew Canning, Jonathan Carter, John Shalf, David Skinner, Stéphane Ethier, Rupak Biswas, M. Jahed Djomehri, Rob F. Van der Wijngaart	Evaluation of Cache-based Superscalar and Cacheless Vector Architectures for Scientific Computations.	SC	2003	DBLP DOI BibTeX RDF
25	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.	DATE	2002	DBLP DOI BibTeX RDF
25	Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera	Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor.	DSD	2002	DBLP DOI BibTeX RDF
25	Gabriel H. Loh	Exploiting data-width locality to increase superscalar execution bandwidth.	MICRO	2002	DBLP DOI BibTeX RDF
25	Chee How Lim, W. Robert Daasch, George Cai	A Thermal-Aware Superscalar Microprocessor (invited).	ISQED	2002	DBLP DOI BibTeX RDF
25	Sébastien Nussbaum, James E. Smith 0001	Modeling Superscalar Processors via Statistical Simulation.	IEEE PACT	2001	DBLP DOI BibTeX RDF
25	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
25	Mauro Olivieri	A genetic approach to the design space exploration of superscalar microprocessor architectures.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
25	Jian Huang, David J. Lilja	Exploring Sub-Block Value Reuse for Superscalar Processors.	IEEE PACT	2000	DBLP DOI BibTeX RDF
25	Yong Zhang, Min Zhang	A Novel Superscalar Architecture for Fast DCT Implementation.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
25	Xianfeng Zhou, Margaret Martonosi	Augmenting Modern Superscalar Architectures with Configurable Extended Instructions.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
25	Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis	Counter Based Superscalar Instruction Issuing.	EUROMICRO	2000	DBLP DOI BibTeX RDF
25	Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami	Circuits for wide-window superscalar processors.	ISCA	2000	DBLP DOI BibTeX RDF
25	Jörn Schneider, Christian Ferdinand	Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation.	Workshop on Languages, Compilers, and Tools for Embedded Systems	1999	DBLP DOI BibTeX RDF
25	José González 0002, Antonio González 0001	Control-Flow Speculation through Value Prediction for Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Path-based Selector, Branch Prediction, Value Prediction, Hybrid predictor
25	Alan Pita, Nadeem Malik	Sectored renaming for superscalar microprocessors.	IPCCC	1999	DBLP DOI BibTeX RDF
25	Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada	A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing.	ICCD	1999	DBLP DOI BibTeX RDF	scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch
25	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor.	ISCA	1999	DBLP DOI BibTeX RDF
25	Omar Hammami	Performance Impacts of Superscalar Microarchitecture on SOM Execution.	Annual Simulation Symposium	1998	DBLP DOI BibTeX RDF
25	Sorin Cotofana, Stamatis Vassiliadis	On the Design Complexity of the Issue Logic of Superscalar Machines.	EUROMICRO	1998	DBLP DOI BibTeX RDF
25	Scott A. Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey	Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, pseudo-random, Alpha
25	Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura	Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
25	James J. Carrig Jr., Gerard G. L. Meyer	Efficient Householder QR Factorization for Superscalar Processors.	ACM Trans. Math. Softw.	1997	DBLP DOI BibTeX RDF	Householder QR factorization, register model, cache model
25	Derek B. Noonburg, John Paul Shen	A Framework for Statistical Modeling of Superscalar Processor Performance.	HPCA	1997	DBLP DOI BibTeX RDF
25	Craig S. K. Clapp	Optimizing a Fast Stream Cipher for VLIW, SIMD, and Superscalar Processors.	FSE	1997	DBLP DOI BibTeX RDF
25	Unnikrishnan R. Nair, Donna J. Quammen, Daniel Tabak	Superscalar Extension for the Multris Processor.	EUROMICRO	1997	DBLP DOI BibTeX RDF
25	Subbarao Palacharla, Norman P. Jouppi, James E. Smith 0001	Complexity-Effective Superscalar Processors.	ISCA	1997	DBLP DOI BibTeX RDF
25	Anne M. Holler	Optimization for a Superscalar Out-of-Order Machine.	MICRO	1996	DBLP DOI BibTeX RDF
25	Steven Wallace, Nader Bagherzadeh	Instruction Fetching Mechanisms for Superscalar Microprocessors.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
25	Richard D. Potter, Gordon B. Steven	Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
25	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Functionality Distribution on a Superscalar Architecture.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
25	Stéphan Jourdan, Pascal Sainrat, Daniel Litaize	Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor.	ISCA	1995	DBLP DOI BibTeX RDF