Search results for "verification"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Tae-Seung Lee, Ho-Jin Choi, Seung-Hoe Choi, Byong-Won Hwang	A Method on Improving of Enrolling Speed for the MLP-Based Speaker Verification System through Reducing Learning Data.	PRICAI	2002	DBLP DOI BibTeX RDF
30	Takuya Katayama, Yutaka Hoshino	Verification of Attribute Grammars.	POPL	1981	DBLP DOI BibTeX RDF
30	Leon G. Stucki	Validation and verification vs. The software life cycle(Position Statement).	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF
30	Hiromasa Shin, Yusuke Endoh, Yoshio Kataoka	ARVE: Aspect-Oriented Runtime Verification Environment.	RV	2007	DBLP DOI BibTeX RDF
30	Patrick Lincoln, John M. Rushby	The Formal Verification of an Algorithm for Interactive Consistency under a Hybrid Fault Model.	CAV	1993	DBLP DOI BibTeX RDF
29	Natalia Sidorova, Martin Steffen	Verifying Large SDL-Specifications Using Model Checking.	SDL Forum	2001	DBLP DOI BibTeX RDF	SDL model checking, bottom-up verification, verification case study, compositional, abstraction
29	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
29	Kenneth L. McMillan	Proofs, Interpolants, and Relevance Heuristics.	Haifa Verification Conference	2008	DBLP DOI BibTeX RDF
29	Malay K. Ganai	Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT().	Haifa Verification Conference	2008	DBLP DOI BibTeX RDF
29	Saddek Bensalem, Doron A. Peled, Hongyang Qu 0001, Stavros Tripakis, Lenore D. Zuck	Test Case Generation for Ultimately Periodic Paths.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
29	Saddek Bensalem, Susanne Graf, Yassine Lakhnech	Abstraction as the Key for Invariant Verification.	Verification: Theory and Practice	2003	DBLP DOI BibTeX RDF
29	David A. Basin, Peter Del Vecchio	Verification Of Combinational Logic in Nuprl.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
29	Warren A. Hunt Jr., Bishop Brock	The Verification of a Bit-slice ALU.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
29	Daniel Weise	Constraints, Abstraction and Verification.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
29	Ivan Christoff	A Method for Verification of Trace and Test Equivalence.	Automatic Verification Methods for Finite State Systems	1989	DBLP DOI BibTeX RDF
29	Shengru Tu, Sehun James Oh, Rushikesh Kale, Aditya Kallem, Shireesha Tankashala	Developing verification-driven learning cases.	ITiCSE	2010	DBLP DOI BibTeX RDF	TDL, verification-driven learning, software verification
29	Joonhyuk Yoo, Manoj Franklin	Hierarchical Verification for Increasing Performance in Reliable Processors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Active verification management, Filter checker, Correctness non-critically, Fault tolerance, Performance, Hierarchical verification
29	André Platzer, Edmund M. Clarke	Computing Differential Invariants of Hybrid Systems as Fixedpoints.	CAV	2008	DBLP DOI BibTeX RDF	verification of hybrid systems, verification logic, fixedpoint engine, differential invariants
29	Kun Peng, Colin Boyd, Ed Dawson	Batch zero-knowledge proof and verification and its applications.	ACM Trans. Inf. Syst. Secur.	2007	DBLP DOI BibTeX RDF	Batch proof and verification of reencryption, batch proof and verification of decryption, mix network
29	Abdul Wahab, Geok See Ng, A. Jonatan	Integrated Biometric Verification System Using Soft Computing Approach.	Neural Process. Lett.	2007	DBLP DOI BibTeX RDF	biometric verification, false acceptance, false rejection, fuzzy neural network, fingerprint verification, minutiae
29	Stuart Swan	SystemC transaction level models and RTL verification.	DAC	2006	DBLP DOI BibTeX RDF	RTL verification, hardware/software co-verification, systemC, hardware/software co-design, transaction level model, TLM
29	Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy	VLIW: a case study of parallelism verification.	DAC	2005	DBLP DOI BibTeX RDF	parallelism, test generation, VLIW, functional verification, processor verification
29	Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas	Formal Verification of a Complex Pipelined Processor.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	completion functions, formal verification, PVS, processor verification
29	Xiao Sun 0002, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage.	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
29	William L. Bradley, Ranga Vemuri	Transformations for functional verification of synthesized designs.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
29	David Guaspari, Carla Marceau, Wolfgang Polak	Formal Verification of Ada Programs.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	Penelope verification editor, formal basis, interactive development, logical soundness, interface languages, software engineering, Ada, program verification, correctness proof, prototype system, predicate transformers, Ada programs
29	Bernhard Beckert, Sarah Grebing, Mattias Ulbrich	An Interaction Concept for Program Verification Systems with Explicit Proof Object.	Haifa Verification Conference	2017	DBLP DOI BibTeX RDF
29	Ryo Watanabe, Kozo Okano, Toshifusa Sekizawa	Towards Verification of Robot Design for Self-localization.	Haifa Verification Conference	2017	DBLP DOI BibTeX RDF
29	Cuong K. Chau, Warren A. Hunt Jr., Marly Roncken, Ivan E. Sutherland	A Framework for Asynchronous Circuit Modeling and Verification in ACL2.	Haifa Verification Conference	2017	DBLP DOI BibTeX RDF
29	Dirk Beyer 0001, Thomas Lemberger 0002	Software Verification: Testing vs. Model Checking - A Comparative Evaluation of the State of the Art.	Haifa Verification Conference	2017	DBLP DOI BibTeX RDF
29	Luca Pulina, Armando Tacchella	More Adaptive Does not Imply Less Safe (with Formal Verification).	Haifa Verification Conference	2017	DBLP DOI BibTeX RDF
29	Fedor Shmarov, Paolo Zuliani	Probabilistic Hybrid Systems Verification via SMT and Monte Carlo Techniques.	Haifa Verification Conference	2016	DBLP DOI BibTeX RDF
29	Ping Yeung, Eugene Mandel	Multi-Domain Verification of Power, Clock and Reset Domains.	Haifa Verification Conference	2015	DBLP DOI BibTeX RDF
29	Dejanira Araiza-Illan, David G. Western, Anthony G. Pipe, Kerstin Eder	Coverage-Driven Verification - An Approach to Verify Code for Robots that Directly Interact with Humans.	Haifa Verification Conference	2015	DBLP DOI BibTeX RDF
29	Juan Pablo Galeotti, Carlo A. Furia, Eva May, Gordon Fraser 0001, Andreas Zeller	DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification.	Haifa Verification Conference	2014	DBLP DOI BibTeX RDF
29	Mikhail Lukin, Maxim Buzdalov 0001, Anatoly Shalyto 0001	Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study.	Haifa Verification Conference	2014	DBLP DOI BibTeX RDF
29	Oliver Schwarz, Mads Dam	Formal Verification of Secure User Mode Device Execution with DMA.	Haifa Verification Conference	2014	DBLP DOI BibTeX RDF
29	Robert Könighofer, Ronald Toegl, Roderick Bloem	Automatic Error Localization for Software Using Deductive Verification.	Haifa Verification Conference	2014	DBLP DOI BibTeX RDF
29	Tim Lange 0001, Martin R. Neuhäußer, Thomas Noll 0001	Speeding Up the Safety Verification of Programmable Logic Controller Code.	Haifa Verification Conference	2013	DBLP DOI BibTeX RDF
29	Maciej J. Ciesielski, Walter Brown, André Rossi	Arithmetic Bit-Level Verification Using Network Flow Model.	Haifa Verification Conference	2013	DBLP DOI BibTeX RDF
29	Andreas Abel 0004, Allon Adir, Torsten Blochwitz, Lev Greenberg, Tamer Salman	Development and Verification of Complex Hybrid Systems Using Synthesizable Monitors.	Haifa Verification Conference	2013	DBLP DOI BibTeX RDF
29	Nikolaj S. Bjørner	SMT in Verification, Modeling, and Testing at Microsoft.	Haifa Verification Conference	2012	DBLP DOI BibTeX RDF
29	Allon Adir, Alex Goryachev, Lev Greenberg, Tamer Salman, Gil Shurek	A New Test-Generation Methodology for System-Level Verification of Production Processes.	Haifa Verification Conference	2012	DBLP DOI BibTeX RDF
29	Phillip James, Arnold Beckmann, Markus Roggenbach	Using Domain Specific Languages to Support Verification in the Railway Domain.	Haifa Verification Conference	2012	DBLP DOI BibTeX RDF
29	Alex Goryachev	Special Session on Security Verification.	Haifa Verification Conference	2012	DBLP DOI BibTeX RDF
29	Yoav Katz, Michal Rimon, Avi Ziv	A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs.	Haifa Verification Conference	2012	DBLP DOI BibTeX RDF
29	Klaus-Dieter Schubert	Verification Challenges of Workload Optimized Hardware Systems.	Haifa Verification Conference	2011	DBLP DOI BibTeX RDF
29	Marcela Simková, Ondrej Lengál, Michal Kajan	HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware.	Haifa Verification Conference	2011	DBLP DOI BibTeX RDF
29	Kathryn Kranen	Pioneering the Future of Verification: A Spiral of Technological and Business Innovation.	Haifa Verification Conference	2011	DBLP DOI BibTeX RDF
29	Michael Katelman, José Meseguer 0001	vlogsl: A Strategy Language for Simulation-Based Verification of Hardware.	Haifa Verification Conference	2010	DBLP DOI BibTeX RDF
29	Valeria Bertacco	Verification Failures: What to Do When Things Go Wrong.	Haifa Verification Conference	2010	DBLP DOI BibTeX RDF
29	Harry Foster	Pain, Possibilities, and Prescriptions Industry Trends in Advanced Functional Verification.	Haifa Verification Conference	2009	DBLP DOI BibTeX RDF
29	Mark Harman	The SBSE Approach to Automated Optimization of Verification and Testing.	Haifa Verification Conference	2009	DBLP DOI BibTeX RDF
29	Sharon Barner, Cindy Eisner, Ziv Glazberg, Daniel Kroening, Ishai Rabinovitz	ExpliSAT: Guiding SAT-Based Software Verification with Explicit States.	Haifa Verification Conference	2006	DBLP DOI BibTeX RDF
29	Deepinder P. Sidhu	Protocol Verification via Executable Logic Specifications.	Protocol Specification, Testing, and Verification	1983	DBLP BibTeX RDF
29	Heiko Krumm, Oswald Drobnik	Specification, Implementation, and Verification of Communication Services on the Basis of CIL.	Protocol Specification, Testing, and Verification	1983	DBLP BibTeX RDF
29	Carl A. Sunshine	Experience with automated Protocol Verification.	Protocol Specification, Testing, and Verification	1983	DBLP BibTeX RDF
29	Claude Marché	Jessie: an intermediate language for Java and C verification.	PLPV	2007	DBLP DOI BibTeX RDF	behavioral properties, verification conditions generator, verification
29	Pavlína Vareková, Pavel Moravec 0002, Ivana Cerná, Barbora Zimmerová	Effective verification of systems with a dynamic number of components.	SAVCBS	2007	DBLP DOI BibTeX RDF	dynamic number of components, formal verification, software verification, component-based systems, finite-state systems
28	Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford	Providing a formal linkage between MDG and HOL.	Formal Methods Syst. Des.	2007	DBLP DOI BibTeX RDF	Verification system correctness, Hybrid verification systems, Formal hardware verification, Usability verification
28	Babu Turumella, Mukesh Sharma	Assertion-based verification of a 32 thread SPARCTM CMT microprocessor.	DAC	2008	DBLP DOI BibTeX RDF	simulation, verification, coverage, assertions, multi-threading
28	Raj S. Mitra	Strategies for mainstream usage of formal verification.	DAC	2008	DBLP DOI BibTeX RDF	formal verification, emerging technologies
28	Terence Sim, Sheng Zhang 0007, Rajkumar Janakiraman, Sandeep Kumar	Continuous Verification Using Multimodal Biometrics.	IEEE Trans. Pattern Anal. Mach. Intell.	2007	DBLP DOI BibTeX RDF	Pattern recognition, verification, biometrics, fusion
28	Katarzyna Radecka, Zeljko Zilic	Design Verification by Test Vectors and Arithmetic Transform Universal Test Set.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	arithmetic transform, Verification, spectral methods, error modeling, Universal Test Set, Reed-Muller transform, Walsh-Hadamard transform
28	Tae-Seung Lee, Byong-Won Hwang	Continuants Based Neural Speaker Verification System.	MICAI	2004	DBLP DOI BibTeX RDF	multiplayer perceptrons, pattern recognition, continuants, Speaker verification, biometric authentication
28	Yves Mathys, André Chátelain	Verification strategy for integration 3G baseband SoC.	DAC	2003	DBLP DOI BibTeX RDF	3G baseband, verification, architecture, SoC
28	Ying-Tsai Chang, Kwang-Ting Cheng	Self-referential verification of gate-level implementations of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	arithmetic circuit verification
28	Byeong Min, Gwan Choi	Verification Simulation Acceleration Using Code-Perturbation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	code-perturbation, simulation, verification, coverage, fault
28	Changqing Wang, David R. Musser	Dynamic Verification of C++ Generic Algorithms.	IEEE Trans. Software Eng.	1997	DBLP DOI BibTeX RDF	verification, C++, Specification, templates, software libraries, generic algorithms, Standard Template Library
28	Dave Whipp	Exploiting "architecture for verification" to streamline the verification process.	DAC	2009	DBLP DOI BibTeX RDF	verification, executable specification, ESL
28	Jaeha Kim	Mixed-Signal System Verification: A High-Speed Link Example.	CAV	2009	DBLP DOI BibTeX RDF	analog and mixed-signal verification, analog design intent, linear system models
27	F. Keith Hanna, Neil Daeche, Mark Longley	Veritas+: A Specification Language Based on Type Theory.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF	Formal verification, Specification languages, Type theory
27	Eyad Alkassar, Mark A. Hillebrand, Dirk Leinenbach, Norbert Schirmer, Artem Starostin, Alexandra Tsyban	Balancing the Load.	J. Autom. Reason.	2009	DBLP DOI BibTeX RDF	Pervasive formal verification, Software verification, Systems verification
27	Paul Curzon, Ian M. Leslie	A case study on design for provability.	ICECCS	1995	DBLP DOI BibTeX RDF	design for provability, verification task, ATM network switch, formal specification, formal specification, formal verification, formal verification, switching fabric
27	Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson	Verification of the cell broadband engineTM processor.	DAC	2006	DBLP DOI BibTeX RDF	directed random verification, processor reference model, trace-based verification, hierarchical verification
27	Victor Berman	An update on IEEE P1647: The e system verification language.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	IEEE P1647, e language, verification process automation, verification, standardization, functional verification
27	Eric Y. T. Juan, Jeffrey J. P. Tsai, Tadao Murata	A new compositional method for condensed state-space verification.	HASE	1996	DBLP DOI BibTeX RDF	compositional method, condensed state-space verification, large-scale systems analysis, condensation rules, tightly coupled modules, reachable marking detection, Petri nets, program verification, reachability analysis, concurrent systems, compositional verification, deadlock detection, dynamic behavior, dynamic properties, state space explosion
27	Riccardo Focardi, Roberto Gorrieri, V. Panini	The security checker: a semantics-based tool for the verification of security properties.	CSFW	1995	DBLP DOI BibTeX RDF	security checker, semantics-based tool, security properties verification, security process algebra, concurrency workbench, formal specification, formal verification, specifications, process algebra, confidentiality, security of data, automatic verification
27	Radu Negulescu, Janusz A. Brzozowski	Relative liveness: from intuition to automated verification.	ASYNC	1995	DBLP DOI BibTeX RDF	relative liveness, finite trace theory, safety condition, hierarchical verification theorems, program verification, safety, multiprocessing systems, automata, finite automata, liveness, equivalence, multiprocessing programs, automated verification
27	Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham	Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.	ICCD	1995	DBLP DOI BibTeX RDF	control flow machine, verification vectors, formal verification, logic testing, digital simulation, circuit analysis computing, design verification, functional specification
27	Oleg Petlin, Wilson Snyder	Functional Verification of SiCortex Multiprocessor System-on-a-Chip.	DAC	2007	DBLP DOI BibTeX RDF
27	Carmine Ventre	Mechanisms with Verification for Any Finite Domain.	WINE	2006	DBLP DOI BibTeX RDF
27	Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang 0016	VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.	ITNG	2006	DBLP DOI BibTeX RDF
27	Changhan Park, Myungseok Ki, Jaechan Namkung, Joon Ki Paik	Multimodal Priority Verification of Face and Speech Using Momentum Back-Propagation Neural Network.	ISNN (2)	2006	DBLP DOI BibTeX RDF
27	Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel	Challenges in the Formal Verification of Complete State-of-the-Art Processors.	ICCD	2005	DBLP DOI BibTeX RDF
27	Ann E. Kelley Sobel, Richard C. Linger	Advances in Software Specification and Verification - Introduction.	HICSS	2000	DBLP DOI BibTeX RDF
27	Ray Turner	System-Level Verification - A Comparison of Approaches.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF
27	Pierre Wodey, Fabrice Baray	Linking Codesign and Verification by Means of E-LOTOS FDT.	EUROMICRO	1999	DBLP DOI BibTeX RDF
27	Fong Pong, Michel Dubois 0001	Formal Verification of Complex Coherence Protocols Using Symbolic State Models.	J. ACM	1998	DBLP DOI BibTeX RDF	state abstraction, state enumeration methods, formal methods, shared-memory multiprocessors, cache coherence protocols
27	Jeffrey M. Voas, Keith W. Miller 0001	Software Testability: The New Verification.	IEEE Softw.	1995	DBLP DOI BibTeX RDF
27	Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik	Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.	CAV	2009	DBLP DOI BibTeX RDF
27	Giuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari	A mixed-signal verification kit for verification of analogue-digital circuits.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
27	Yuhong Zhao 0001, Martin Kardos, Simon Oberthür, Franz J. Rammig	Comprehensive Verification Framework for Dependability of Self-optimizing Systems.	ATVA	2005	DBLP DOI BibTeX RDF
27	Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli	Integrating RAM and Disk Based Verification within the Mur-phi Verifier.	CHARME	2003	DBLP DOI BibTeX RDF
27	Fady Copty, Amitai Irron, Osnat Weissberg, Nathan P. Kropp, Gila Kamhi	Efficient Debugging in a Formal Verification Environment.	CHARME	2001	DBLP DOI BibTeX RDF
27	Brian T. Graham, Graham M. Birtwistle	Formalising the Design of an SECD chip.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
27	George J. Milne	Design for Verifiability.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
27	Rance Cleaveland, Joachim Parrow, Bernhard Steffen	The Concurrency Workbench.	Automatic Verification Methods for Finite State Systems	1989	DBLP DOI BibTeX RDF
26	Andrea Bracciali, Gianluigi Ferrari 0002, Emilio Tuosto	A symbolic framework for multi-faceted security protocol analysis.	Int. J. Inf. Sec.	2008	DBLP DOI BibTeX RDF	Automated verification tools, Formal verification, Security protocols, Symbolic model checking
26	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer	AQUILA: An Equivalence Checking System for Large Sequential Designs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	state exploration, formal verification, Design verification, equivalence checking