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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 19541 occurrences of 5230 keywords
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Results
Found 53773 publication records. Showing 53773 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Tae-Seung Lee, Ho-Jin Choi, Seung-Hoe Choi, Byong-Won Hwang |
A Method on Improving of Enrolling Speed for the MLP-Based Speaker Verification System through Reducing Learning Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRICAI ![In: PRICAI 2002: Trends in Artificial Intelligence, 7th Pacific Rim International Conference on Artificial Intelligence, Tokyo, Japan, August 18-22, 2002, Proceedings, pp. 619, 2002, Springer, 3-540-44038-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Takuya Katayama, Yutaka Hoshino |
Verification of Attribute Grammars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of the Eighth Annual ACM Symposium on Principles of Programming Languages, Williamsburg, Virginia, USA, January 1981, pp. 177-186, 1981, ACM Press, 0-89791-029-X. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
30 | Leon G. Stucki |
Validation and verification vs. The software life cycle(Position Statement). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Annual Conference (2) ![In: Proceedings 1978 ACM Annual Conference, Washington, DC, USA, December 4-6, 1978, Volume II, pp. 783, 1978, ACM, 978-0-89791-000-2. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
|
30 | Hiromasa Shin, Yusuke Endoh, Yoshio Kataoka |
ARVE: Aspect-Oriented Runtime Verification Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RV ![In: Runtime Verification, 7th International Workshop, RV 2007, Vancouver, Canada, March 13, 2007, Revised Selected Papers, pp. 87-96, 2007, Springer, 978-3-540-77394-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Patrick Lincoln, John M. Rushby |
The Formal Verification of an Algorithm for Interactive Consistency under a Hybrid Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 292-304, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Natalia Sidorova, Martin Steffen |
Verifying Large SDL-Specifications Using Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SDL Forum ![In: SDL 2001: Meeting UML, 10th International SDL Forum Copenhagen, Denmark, June 27-29, 2001, Proceedings, pp. 403-420, 2001, Springer, 3-540-42281-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
SDL model checking, bottom-up verification, verification case study, compositional, abstraction |
29 | Pranav Ashar, Aarti Gupta, Sharad Malik |
Using complete-1-distinguishability for FSM equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 346-353, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification |
29 | Kenneth L. McMillan |
Proofs, Interpolants, and Relevance Heuristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 3, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Malay K. Ganai |
Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT(). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 68-83, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Saddek Bensalem, Doron A. Peled, Hongyang Qu 0001, Stavros Tripakis, Lenore D. Zuck |
Test Case Generation for Ultimately Periodic Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 120-135, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Saddek Bensalem, Susanne Graf, Yassine Lakhnech |
Abstraction as the Key for Invariant Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Verification: Theory and Practice ![In: Verification: Theory and Practice, Essays Dedicated to Zohar Manna on the Occasion of His 64th Birthday, pp. 67-99, 2003, Springer, 3-540-21002-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | David A. Basin, Peter Del Vecchio |
Verification Of Combinational Logic in Nuprl. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 333-357, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Warren A. Hunt Jr., Bishop Brock |
The Verification of a Bit-slice ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 282-306, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Daniel Weise |
Constraints, Abstraction and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 25-39, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Ivan Christoff |
A Method for Verification of Trace and Test Equivalence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 81-88, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Shengru Tu, Sehun James Oh, Rushikesh Kale, Aditya Kallem, Shireesha Tankashala |
Developing verification-driven learning cases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 15th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2010, Bilkent, Ankara, Turkey, June 26-30, 2010, pp. 58-62, 2010, ACM, 978-1-60558-729-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
TDL, verification-driven learning, software verification |
29 | Joonhyuk Yoo, Manoj Franklin |
Hierarchical Verification for Increasing Performance in Reliable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 117-128, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Active verification management, Filter checker, Correctness non-critically, Fault tolerance, Performance, Hierarchical verification |
29 | André Platzer, Edmund M. Clarke |
Computing Differential Invariants of Hybrid Systems as Fixedpoints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 176-189, 2008, Springer, 978-3-540-70543-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
verification of hybrid systems, verification logic, fixedpoint engine, differential invariants |
29 | Kun Peng, Colin Boyd, Ed Dawson |
Batch zero-knowledge proof and verification and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Inf. Syst. Secur. ![In: ACM Trans. Inf. Syst. Secur. 10(2), pp. 6, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Batch proof and verification of reencryption, batch proof and verification of decryption, mix network |
29 | Abdul Wahab, Geok See Ng, A. Jonatan |
Integrated Biometric Verification System Using Soft Computing Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Process. Lett. ![In: Neural Process. Lett. 25(2), pp. 111-126, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
biometric verification, false acceptance, false rejection, fuzzy neural network, fingerprint verification, minutiae |
29 | Stuart Swan |
SystemC transaction level models and RTL verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 90-92, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RTL verification, hardware/software co-verification, systemC, hardware/software co-design, transaction level model, TLM |
29 | Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy |
VLIW: a case study of parallelism verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 779-782, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parallelism, test generation, VLIW, functional verification, processor verification |
29 | Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas |
Formal Verification of a Complex Pipelined Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 23(2), pp. 171-213, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
completion functions, formal verification, PVS, processor verification |
29 | Xiao Sun 0002, Carmie Hull |
Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 108-116, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time |
29 | William L. Bradley, Ranga Vemuri |
Transformations for functional verification of synthesized designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 243-248, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states |
29 | David Guaspari, Carla Marceau, Wolfgang Polak |
Formal Verification of Ada Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(9), pp. 1058-1075, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Penelope verification editor, formal basis, interactive development, logical soundness, interface languages, software engineering, Ada, program verification, correctness proof, prototype system, predicate transformers, Ada programs |
29 | Bernhard Beckert, Sarah Grebing, Mattias Ulbrich |
An Interaction Concept for Program Verification Systems with Explicit Proof Object. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 13th International Haifa Verification Conference, HVC 2017, Haifa, Israel, November 13-15, 2017, Proceedings, pp. 163-178, 2017, Springer, 978-3-319-70388-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Ryo Watanabe, Kozo Okano, Toshifusa Sekizawa |
Towards Verification of Robot Design for Self-localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 13th International Haifa Verification Conference, HVC 2017, Haifa, Israel, November 13-15, 2017, Proceedings, pp. 245-248, 2017, Springer, 978-3-319-70388-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Cuong K. Chau, Warren A. Hunt Jr., Marly Roncken, Ivan E. Sutherland |
A Framework for Asynchronous Circuit Modeling and Verification in ACL2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 13th International Haifa Verification Conference, HVC 2017, Haifa, Israel, November 13-15, 2017, Proceedings, pp. 3-18, 2017, Springer, 978-3-319-70388-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Dirk Beyer 0001, Thomas Lemberger 0002 |
Software Verification: Testing vs. Model Checking - A Comparative Evaluation of the State of the Art. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 13th International Haifa Verification Conference, HVC 2017, Haifa, Israel, November 13-15, 2017, Proceedings, pp. 99-114, 2017, Springer, 978-3-319-70388-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Luca Pulina, Armando Tacchella |
More Adaptive Does not Imply Less Safe (with Formal Verification). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 13th International Haifa Verification Conference, HVC 2017, Haifa, Israel, November 13-15, 2017, Proceedings, pp. 237-240, 2017, Springer, 978-3-319-70388-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Fedor Shmarov, Paolo Zuliani |
Probabilistic Hybrid Systems Verification via SMT and Monte Carlo Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 12th International Haifa Verification Conference, HVC 2016, Haifa, Israel, November 14-17, 2016, Proceedings, pp. 152-168, 2016, 978-3-319-49051-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
29 | Ping Yeung, Eugene Mandel |
Multi-Domain Verification of Power, Clock and Reset Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 11th International Haifa Verification Conference, HVC 2015, Haifa, Israel, November 17-19, 2015, Proceedings, pp. 245-255, 2015, Springer, 978-3-319-26286-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
29 | Dejanira Araiza-Illan, David G. Western, Anthony G. Pipe, Kerstin Eder |
Coverage-Driven Verification - An Approach to Verify Code for Robots that Directly Interact with Humans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 11th International Haifa Verification Conference, HVC 2015, Haifa, Israel, November 17-19, 2015, Proceedings, pp. 69-84, 2015, Springer, 978-3-319-26286-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
29 | Juan Pablo Galeotti, Carlo A. Furia, Eva May, Gordon Fraser 0001, Andreas Zeller |
DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014. Proceedings, pp. 48-53, 2014, Springer, 978-3-319-13337-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Mikhail Lukin, Maxim Buzdalov 0001, Anatoly Shalyto 0001 |
Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014. Proceedings, pp. 165-170, 2014, Springer, 978-3-319-13337-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Oliver Schwarz, Mads Dam |
Formal Verification of Secure User Mode Device Execution with DMA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014. Proceedings, pp. 236-251, 2014, Springer, 978-3-319-13337-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Robert Könighofer, Ronald Toegl, Roderick Bloem |
Automatic Error Localization for Software Using Deductive Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014. Proceedings, pp. 92-98, 2014, Springer, 978-3-319-13337-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Tim Lange 0001, Martin R. Neuhäußer, Thomas Noll 0001 |
Speeding Up the Safety Verification of Programmable Logic Controller Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings, pp. 44-60, 2013, Springer, 978-3-319-03076-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Maciej J. Ciesielski, Walter Brown, André Rossi |
Arithmetic Bit-Level Verification Using Network Flow Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings, pp. 327-343, 2013, Springer, 978-3-319-03076-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Andreas Abel 0004, Allon Adir, Torsten Blochwitz, Lev Greenberg, Tamer Salman |
Development and Verification of Complex Hybrid Systems Using Synthesizable Monitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings, pp. 182-198, 2013, Springer, 978-3-319-03076-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Nikolaj S. Bjørner |
SMT in Verification, Modeling, and Testing at Microsoft. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers, pp. 3, 2012, Springer, 978-3-642-39610-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Allon Adir, Alex Goryachev, Lev Greenberg, Tamer Salman, Gil Shurek |
A New Test-Generation Methodology for System-Level Verification of Production Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers, pp. 178-192, 2012, Springer, 978-3-642-39610-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Phillip James, Arnold Beckmann, Markus Roggenbach |
Using Domain Specific Languages to Support Verification in the Railway Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers, pp. 274-275, 2012, Springer, 978-3-642-39610-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Alex Goryachev |
Special Session on Security Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers, pp. 5, 2012, Springer, 978-3-642-39610-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Yoav Katz, Michal Rimon, Avi Ziv |
A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 8th International Haifa Verification Conference, HVC 2012, Haifa, Israel, November 6-8, 2012. Revised Selected Papers, pp. 148-161, 2012, Springer, 978-3-642-39610-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Klaus-Dieter Schubert |
Verification Challenges of Workload Optimized Hardware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers, pp. 4, 2011, Springer, 978-3-642-34187-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
29 | Marcela Simková, Ondrej Lengál, Michal Kajan |
HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers, pp. 247-253, 2011, Springer, 978-3-642-34187-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
29 | Kathryn Kranen |
Pioneering the Future of Verification: A Spiral of Technological and Business Innovation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers, pp. 2, 2011, Springer, 978-3-642-34187-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
29 | Michael Katelman, José Meseguer 0001 |
vlogsl: A Strategy Language for Simulation-Based Verification of Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 6th International Haifa Verification Conference, HVC 2010, Haifa, Israel, October 4-7, 2010. Revised Selected Papers, pp. 129-145, 2010, Springer, 978-3-642-19582-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
29 | Valeria Bertacco |
Verification Failures: What to Do When Things Go Wrong. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 6th International Haifa Verification Conference, HVC 2010, Haifa, Israel, October 4-7, 2010. Revised Selected Papers, pp. 23, 2010, Springer, 978-3-642-19582-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
29 | Harry Foster |
Pain, Possibilities, and Prescriptions Industry Trends in Advanced Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 5th International Haifa Verification Conference, HVC 2009, Haifa, Israel, October 19-22, 2009, Revised Selected Papers, pp. 2, 2009, Springer, 978-3-642-19236-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Mark Harman |
The SBSE Approach to Automated Optimization of Verification and Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing - 5th International Haifa Verification Conference, HVC 2009, Haifa, Israel, October 19-22, 2009, Revised Selected Papers, pp. 3, 2009, Springer, 978-3-642-19236-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Sharon Barner, Cindy Eisner, Ziv Glazberg, Daniel Kroening, Ishai Rabinovitz |
ExpliSAT: Guiding SAT-Based Software Verification with Explicit States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers, pp. 138-154, 2006, Springer, 978-3-540-70888-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Deepinder P. Sidhu |
Protocol Verification via Executable Logic Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Protocol Specification, Testing, and Verification ![In: Protocol Specification, Testing, and Verification, III, Proceedings of the IFIP WG 6.1 Third International Workshop on Protocol Specification, Testing and Verification, organized by IBM Research, Rüschlikon, Switzerland, 31 May - 2 June, 1983, pp. 237-248, 1983, North-Holland, 0-444-86769-4. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
29 | Heiko Krumm, Oswald Drobnik |
Specification, Implementation, and Verification of Communication Services on the Basis of CIL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Protocol Specification, Testing, and Verification ![In: Protocol Specification, Testing, and Verification, III, Proceedings of the IFIP WG 6.1 Third International Workshop on Protocol Specification, Testing and Verification, organized by IBM Research, Rüschlikon, Switzerland, 31 May - 2 June, 1983, pp. 301-316, 1983, North-Holland, 0-444-86769-4. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
29 | Carl A. Sunshine |
Experience with automated Protocol Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Protocol Specification, Testing, and Verification ![In: Protocol Specification, Testing, and Verification, III, Proceedings of the IFIP WG 6.1 Third International Workshop on Protocol Specification, Testing and Verification, organized by IBM Research, Rüschlikon, Switzerland, 31 May - 2 June, 1983, pp. 229-236, 1983, North-Holland, 0-444-86769-4. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
29 | Claude Marché |
Jessie: an intermediate language for Java and C verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLPV ![In: Proceedings of the ACM Workshop Programming Languages meets Program Verification, PLPV 2007, Freiburg, Germany, October 5, 2007, pp. 1-2, 2007, ACM, 978-1-59593-677-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
behavioral properties, verification conditions generator, verification |
29 | Pavlína Vareková, Pavel Moravec 0002, Ivana Cerná, Barbora Zimmerová |
Effective verification of systems with a dynamic number of components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAVCBS ![In: Proceedings of the 2007 Conference Specification and Verification of Component-Based Systems, SAVCBS 2007, Dubrovnik, Croatia, September 3-4, 2007, pp. 3-13, 2007, ACM, 978-1-59593-721-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dynamic number of components, formal verification, software verification, component-based systems, finite-state systems |
28 | Haiyan Xiong, Paul Curzon, Sofiène Tahar, Ann Blandford |
Providing a formal linkage between MDG and HOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 30(2), pp. 83-116, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Verification system correctness, Hybrid verification systems, Formal hardware verification, Usability verification |
28 | Babu Turumella, Mukesh Sharma |
Assertion-based verification of a 32 thread SPARCTM CMT microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 256-261, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, verification, coverage, assertions, multi-threading |
28 | Raj S. Mitra |
Strategies for mainstream usage of formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 800-805, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal verification, emerging technologies |
28 | Terence Sim, Sheng Zhang 0007, Rajkumar Janakiraman, Sandeep Kumar |
Continuous Verification Using Multimodal Biometrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 29(4), pp. 687-700, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Pattern recognition, verification, biometrics, fusion |
28 | Katarzyna Radecka, Zeljko Zilic |
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(5), pp. 628-640, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
arithmetic transform, Verification, spectral methods, error modeling, Universal Test Set, Reed-Muller transform, Walsh-Hadamard transform |
28 | Tae-Seung Lee, Byong-Won Hwang |
Continuants Based Neural Speaker Verification System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICAI ![In: MICAI 2004: Advances in Artificial Intelligence, Third Mexican International Conference on Artificial Intelligence, Mexico City, Mexico, April 26-30, 2004, Proceedings, pp. 89-98, 2004, Springer, 3-540-21459-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiplayer perceptrons, pattern recognition, continuants, Speaker verification, biometric authentication |
28 | Yves Mathys, André Chátelain |
Verification strategy for integration 3G baseband SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 7-10, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
3G baseband, verification, architecture, SoC |
28 | Ying-Tsai Chang, Kwang-Ting Cheng |
Self-referential verification of gate-level implementations of arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 311-316, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
arithmetic circuit verification |
28 | Byeong Min, Gwan Choi |
Verification Simulation Acceleration Using Code-Perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 83-90, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
code-perturbation, simulation, verification, coverage, fault |
28 | Changqing Wang, David R. Musser |
Dynamic Verification of C++ Generic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 23(5), pp. 314-323, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
verification, C++, Specification, templates, software libraries, generic algorithms, Standard Template Library |
28 | Dave Whipp |
Exploiting "architecture for verification" to streamline the verification process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 212-215, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
verification, executable specification, ESL |
28 | Jaeha Kim |
Mixed-Signal System Verification: A High-Speed Link Example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 16, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analog and mixed-signal verification, analog design intent, linear system models |
27 | F. Keith Hanna, Neil Daeche, Mark Longley |
Veritas+: A Specification Language Based on Type Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 358-379, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
Formal verification, Specification languages, Type theory |
27 | Eyad Alkassar, Mark A. Hillebrand, Dirk Leinenbach, Norbert Schirmer, Artem Starostin, Alexandra Tsyban |
Balancing the Load. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Autom. Reason. ![In: J. Autom. Reason. 42(2-4), pp. 389-454, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Pervasive formal verification, Software verification, Systems verification |
27 | Paul Curzon, Ian M. Leslie |
A case study on design for provability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 1st IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '95), November 6-10, 1995, Fort Lauderdale, Florida, USA, pp. 59-62, 1995, IEEE Computer Society, 0-8186-7123-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design for provability, verification task, ATM network switch, formal specification, formal specification, formal verification, formal verification, switching fabric |
27 | Kanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson |
Verification of the cell broadband engineTM processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 338-343, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
directed random verification, processor reference model, trace-based verification, hierarchical verification |
27 | Victor Berman |
An update on IEEE P1647: The e system verification language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(5), pp. 484-486, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IEEE P1647, e language, verification process automation, verification, standardization, functional verification |
27 | Eric Y. T. Juan, Jeffrey J. P. Tsai, Tadao Murata |
A new compositional method for condensed state-space verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 1st High-Assurance Systems Engineering Workshop (HASE '96), October 22, 1996, Niagara, Canada, Proceedings, pp. 104-111, 1996, IEEE Computer Society, 0-8186-7629-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
compositional method, condensed state-space verification, large-scale systems analysis, condensation rules, tightly coupled modules, reachable marking detection, Petri nets, program verification, reachability analysis, concurrent systems, compositional verification, deadlock detection, dynamic behavior, dynamic properties, state space explosion |
27 | Riccardo Focardi, Roberto Gorrieri, V. Panini |
The security checker: a semantics-based tool for the verification of security properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSFW ![In: The Eighth IEEE Computer Security Foundations Workshop (CSFW '95), March 13-15, 1995, Kenmare, County Kerry, Ireland, pp. 60-69, 1995, IEEE Computer Society, 0-8186-7033-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
security checker, semantics-based tool, security properties verification, security process algebra, concurrency workbench, formal specification, formal verification, specifications, process algebra, confidentiality, security of data, automatic verification |
27 | Radu Negulescu, Janusz A. Brzozowski |
Relative liveness: from intuition to automated verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 108-117, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
relative liveness, finite trace theory, safety condition, hierarchical verification theorems, program verification, safety, multiprocessing systems, automata, finite automata, liveness, equivalence, multiprocessing programs, automated verification |
27 | Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham |
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 532-537, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
control flow machine, verification vectors, formal verification, logic testing, digital simulation, circuit analysis computing, design verification, functional specification |
27 | Oleg Petlin, Wilson Snyder |
Functional Verification of SiCortex Multiprocessor System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 906-909, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Carmine Ventre |
Mechanisms with Verification for Any Finite Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WINE ![In: Internet and Network Economics, Second International Workshop, WINE 2006, Patras, Greece, December 15-17, 2006, Proceedings, pp. 37-49, 2006, Springer, 3-540-68138-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang 0016 |
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 245-249, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Changhan Park, Myungseok Ki, Jaechan Namkung, Joon Ki Paik |
Multimodal Priority Verification of Face and Speech Using Momentum Back-Propagation Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part II, pp. 140-149, 2006, Springer, 3-540-34437-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel |
Challenges in the Formal Verification of Complete State-of-the-Art Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 603-608, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Ann E. Kelley Sobel, Richard C. Linger |
Advances in Software Specification and Verification - Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 4-7 January, 2000, Maui, Hawaii, USA, 2000, IEEE Computer Society, 0-7695-0493-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Ray Turner |
System-Level Verification - A Comparison of Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 154-159, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Pierre Wodey, Fabrice Baray |
Linking Codesign and Verification by Means of E-LOTOS FDT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1487-1491, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Fong Pong, Michel Dubois 0001 |
Formal Verification of Complex Coherence Protocols Using Symbolic State Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 45(4), pp. 557-587, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
state abstraction, state enumeration methods, formal methods, shared-memory multiprocessors, cache coherence protocols |
27 | Jeffrey M. Voas, Keith W. Miller 0001 |
Software Testability: The New Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Softw. ![In: IEEE Softw. 12(3), pp. 17-28, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik |
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 414-429, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Giuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari |
A mixed-signal verification kit for verification of analogue-digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 88-93, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Yuhong Zhao 0001, Martin Kardos, Simon Oberthür, Franz J. Rammig |
Comprehensive Verification Framework for Dependability of Self-optimizing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, Third International Symposium, ATVA 2005, Taipei, Taiwan, October 4-7, 2005, Proceedings, pp. 39-53, 2005, Springer, 3-540-29209-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli |
Integrating RAM and Disk Based Verification within the Mur-phi Verifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 277-282, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Fady Copty, Amitai Irron, Osnat Weissberg, Nathan P. Kropp, Gila Kamhi |
Efficient Debugging in a Formal Verification Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001, Proceedings, pp. 275-292, 2001, Springer, 3-540-42541-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Brian T. Graham, Graham M. Birtwistle |
Formalising the Design of an SECD chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 40-66, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | George J. Milne |
Design for Verifiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 1-13, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Rance Cleaveland, Joachim Parrow, Bernhard Steffen |
The Concurrency Workbench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Automatic Verification Methods for Finite State Systems ![In: Automatic Verification Methods for Finite State Systems, International Workshop, Grenoble, France, June 12-14, 1989, Proceedings, pp. 24-37, 1989, Springer, 3-540-52148-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Andrea Bracciali, Gianluigi Ferrari 0002, Emilio Tuosto |
A symbolic framework for multi-faceted security protocol analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Sec. ![In: Int. J. Inf. Sec. 7(1), pp. 55-84, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Automated verification tools, Formal verification, Security protocols, Symbolic model checking |
26 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer |
AQUILA: An Equivalence Checking System for Large Sequential Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(5), pp. 443-464, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
state exploration, formal verification, Design verification, equivalence checking |
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