Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Svetla Boytcheva, Galia Angelova, Zhivko Angelov, Dimitar Tcharaktchiev	Data Mining and Analytics for Exploring Bulgarian Diabetic Register.	DAMDID/RCDL (Selected Papers)	2017	DBLP DOI BibTeX RDF
11	Veronika Laippala, Juhani Luotolahti, Aki-Juhani Kyröläinen, Tapio Salakoski, Filip Ginter	Creating register sub-corpora for the Finnish Internet Parsebank.	NODALIDA	2017	DBLP BibTeX RDF
11	Gustavo Armando Guancha Taquez, Octavio José Salcedo Parra, Brayan Steven Reyes Daza	Data Register for the Automobile Control Flow in Real-Time Using UAV.	WEA	2017	DBLP DOI BibTeX RDF
11	Sparsh Mittal, Haonan Wang, Adwait Jog, Jeffrey S. Vetter	Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File.	VLSID	2017	DBLP DOI BibTeX RDF
11	Leo Nicolle, Julien Bonneton, Hubert Konik, Damien Muselet, Laure Tougne	Towards an electronic orientation table: using features extracted from the image to register Digital Elevation Model.	VISIGRAPP (6: VISAPP)	2017	DBLP DOI BibTeX RDF
11	Jan Schat	Soft-error detection in Register Files using circular scan.	DTIS	2017	DBLP DOI BibTeX RDF
11	Sumanth Gudaparthi, Rahul Shrestha	Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization.	VDAT	2017	DBLP DOI BibTeX RDF
11	Mauro Ianni, Alessandro Pellegrini 0001, Francesco Quaglia	A Wait-Free Multi-word Atomic (1, N) Register for Large-Scale Data Sharing on Multi-core Machines.	CLUSTER	2017	DBLP DOI BibTeX RDF
11	Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery	Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.	DAC	2017	DBLP DOI BibTeX RDF
11	Thomas Winn Dabbs	The Extended Language of Religious Reform: Marking Up a Register for Early Modern Sermons.	DH	2017	DBLP BibTeX RDF
11	Bogdan Ludusan, Reiko Mazuka, Mathieu Bernard, Alejandrina Cristià, Emmanuel Dupoux	The Role of Prosody and Speech Register in Word Segmentation: A Computational Modelling Perspective.	ACL (2)	2017	DBLP DOI BibTeX RDF
11	Elke Teich, Stefania Degaetano-Ortlieb, Peter Fankhauser, Hannah Kermes, Ekaterina Lapshinova-Koltunski	The linguistic construal of disciplinarity: A data-mining approach using register features.	J. Assoc. Inf. Sci. Technol.	2016	DBLP DOI BibTeX RDF
11	Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De	A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
11	Abdulaziz Eker, Oguz Ergin	Exploiting Existing Copies in Register File for Soft Error Correction.	IEEE Comput. Archit. Lett.	2016	DBLP DOI BibTeX RDF
11	Khawar Sarfraz, Mansun Chan	A compact low-power 4-port register file with grounded write bitlines and single-ended read operations.	Integr.	2016	DBLP DOI BibTeX RDF
11	Diego Figueira, Piotr Hofman, Slawomir Lasota 0001	Relating timed and register automata.	Math. Struct. Comput. Sci.	2016	DBLP DOI BibTeX RDF
11	Boris Murmann	The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.	IEEE Commun. Mag.	2016	DBLP DOI BibTeX RDF
11	Yun Liang 0001, Shuo Wang 0009	Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs.	J. Comput. Sci. Technol.	2016	DBLP DOI BibTeX RDF
11	Michael Moeng, Haifeng Xu, Rami G. Melhem, Alex K. Jones	ContextPreRF: Enhancing the Performance and Energy of GPUs With Nonuniform Register Access.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
11	Yung-Hsiang Ho, Chia-Yu Yao	A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
11	Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu	Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
11	Masaki Nakanishi, Miki Matsuyama, Yumi Yokoo	A Fast Quantum Computer Simulator Based on Register Reordering.	IEICE Trans. Inf. Syst.	2016	DBLP DOI BibTeX RDF
11	Petr Sosík, Miroslav Langer	Small (purely) catalytic P systems simulating register machines.	Theor. Comput. Sci.	2016	DBLP DOI BibTeX RDF
11	Jingweijia Tan, Mingsong Chen, Yang Yi 0002, Xin Fu	Mitigating the Impact of Hardware Variability for GPGPUs Register File.	IEEE Trans. Parallel Distributed Syst.	2016	DBLP DOI BibTeX RDF
11	Licheng Yu, Yulong Pei, Tianzhou Chen, Minghui Wu 0001	Architecture supported register stash for GPGPU.	J. Parallel Distributed Comput.	2016	DBLP DOI BibTeX RDF
11	Yilin Zhang, Wei-Ming Lin	Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
11	Liping Wang, Guang Zeng	On the matrix feedback shift register synthesis for matrix sequences.	Sci. China Inf. Sci.	2016	DBLP DOI BibTeX RDF
11	Vladimir V. Sergeichik, Alexander A. Ivaniuk	Digital watermark and fingerprint in variable rank linear-feedback shift register.	Autom. Control. Comput. Sci.	2016	DBLP DOI BibTeX RDF
11	Yi-Ping You, Szu-Chien Chen	VecRA: A Vector-Aware Register Allocator for GPU Shader Processors.	ACM Trans. Embed. Comput. Syst.	2016	DBLP DOI BibTeX RDF
11	Hang Zhang, Xuhao Chen 0001, Nong Xiao, Lei Wang 0011, Fang Liu 0002, Wei Chen 0009, Zhiguang Chen	Shielding STT-RAM Based Register Files on GPUs against Read Disturbance.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
11	Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol	Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
11	Chang Xu 0005, Guojie Luo, Peixin Li, Yiyu Shi 0001, Iris Hui-Ru Jiang	Analytical Clustering Score with Application to Postplacement Register Clustering.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
11	Jingweijia Tan, Zhi Li 0016, Mingsong Chen, Xin Fu	Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
11	Ruijie Fang, Siqi Liu	A Performance Survey on Stack-based and Register-based Virtual Machines.	CoRR	2016	DBLP BibTeX RDF
11	Patricia Bouyer, Nicolas Markey, Mickael Randour, Arnaud Sangnier, Daniel Stan	Reachability in Networks of Register Protocols under Stochastic Schedulers.	CoRR	2016	DBLP BibTeX RDF
11	Achour Mostéfaoui, Michel Raynal	Time-Efficient Read/Write Register in Crash-prone Asynchronous Message-Passing Systems.	CoRR	2016	DBLP BibTeX RDF
11	Silvia Bonomi, Antonella Del Pozzo, Maria Potop-Butucaru, Sébastien Tixeuil	Self-Stabilizing Mobile Byzantine-Tolerant Regular Register with bounded timestamp.	CoRR	2016	DBLP BibTeX RDF
11	Radu Grigore, Nikos Tzevelekos	History-Register Automata	Log. Methods Comput. Sci.	2016	DBLP DOI BibTeX RDF
11	Gaétan de Rassenfosse, Martin Kracker, Gianluca Tarasconi	Getting Started with PATSTAT Register.	CoRR	2016	DBLP BibTeX RDF
11	Motoya Machida, Alexander Y. Shibakov	Stack and register complexity of radix conversions.	CoRR	2016	DBLP BibTeX RDF
11	Marcelo Cicconet, David G. C. Hildebrand, Hunter Elliott	To Find the Symmetry Plane in Any Dimension, Reflect, Register, and Compute a -1 Eigenvector.	CoRR	2016	DBLP BibTeX RDF
11	Sanjay Burman, Seetal Potluri, Debdeep Mukhopadhyay, Kamakoti Veezhinathan	Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures.	J. Low Power Electron.	2016	DBLP DOI BibTeX RDF
11	Santosh Koppa, Manouchehr Mohandesi, Eugene John	An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications.	J. Low Power Electron.	2016	DBLP DOI BibTeX RDF
11	Samaneh Mashhadi	Share secrets stage by stage with homogeneous linear feedback shift register in the standard model.	Secur. Commun. Networks	2016	DBLP DOI BibTeX RDF
11	Deepa Yagain, A. Vijaya Krishna	Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters.	J. Signal Process. Syst.	2016	DBLP DOI BibTeX RDF
11	Elena Dubrova, Maxim Teslenko	A SAT-Based Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers.	IACR Cryptol. ePrint Arch.	2016	DBLP BibTeX RDF
11	Merlin Carl	Randomness and degree theory for infinite time register machines.	Comput.	2016	DBLP DOI BibTeX RDF
11	Donghwan Jeong, Young H. Oh, Jae W. Lee, Yongjun Park 0001	An eDRAM-Based Approximate Register File for GPUs.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
11	Florina Maria Gabor-Harosa, Ovidiu Petru Stan, Lucia Daina, Floarea Mocean	Proposed model for a Romanian register of chronic diseases in children.	Comput. Methods Programs Biomed.	2016	DBLP DOI BibTeX RDF
11	Zhihua Chen, Juan-juan He, Ying Zheng, Tao Song, Zhonghua Deng	An Optimized Feedforward Decoupling PD Register Control Method of Roll-to-Roll Web Printing Systems.	IEEE Trans Autom. Sci. Eng.	2016	DBLP DOI BibTeX RDF
11	Neil Burroughs	Register allocation and spilling using the expected distance heuristic.	Softw. Pract. Exp.	2016	DBLP DOI BibTeX RDF
11	Ge Wei, Jinjiang Yang, Jun Yang 0006	High performance and area efficiency design of global register file for coarse-grained reconfigurable cryptographic processor.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
11	Toshihiro Takahashi, Ryo Numaguchi, Yuki Yamanashi, Nobuyuki Yoshikawa	High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
11	Josef Eisl, Matthias Grimmer, Doug Simon, Thomas Würthinger, Hanspeter Mössenböck	Trace-based Register Allocation in a JIT Compiler.	PPPJ	2016	DBLP DOI BibTeX RDF
11	Thomas Windbacher, Alexander Makarov, Viktor Sverdlov, Siegfried Selberherr	The exploitation of magnetization orientation encoded spin-transfer torque for an ultra dense non-volatile magnetic shift register.	ESSDERC	2016	DBLP DOI BibTeX RDF
11	Jingweijia Tan, Shuaiwen Leon Song, Kaige Yan, Xin Fu, Andrès Márquez, Darren J. Kerbyson	Combating the Reliability Challenge of GPU Register File at Low Supply Voltage.	PACT	2016	DBLP DOI BibTeX RDF
11	Khawar Sarfraz, Mansun Chan	A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files.	MWSCAS	2016	DBLP DOI BibTeX RDF
11	Ningxi Liu, Benton H. Calhoun	Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool.	ISVLSI	2016	DBLP DOI BibTeX RDF
11	Ehsan Atoofian	A low power STT-RAM based register file for GPGPUs.	SAC	2016	DBLP DOI BibTeX RDF
11	Parvaneh Babari, Manfred Droste, Vitaly Perevoshchikov	Weighted Register Automata and Weighted Logic on Data Words.	ICTAC	2016	DBLP DOI BibTeX RDF
11	Tuo Li 0001, Jude Angelo Ambrose, Sri Parameswaran	RECORD: Reducing register traffic for checkpointing in embedded processors.	DATE	2016	DBLP BibTeX RDF
11	Ang Li 0006, Shuaiwen Leon Song, Akash Kumar 0001, Eddy Z. Zhang, Daniel G. Chavarría-Miranda, Henk Corporaal	Critical points based register-concurrency autotuning for GPUs.	DATE	2016	DBLP BibTeX RDF
11	Arthur Perais, Fernando A. Endo, André Seznec	Register sharing for equality prediction.	MICRO	2016	DBLP DOI BibTeX RDF
11	Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang 0002, Chao Li 0009, Xiaoyao Liang	Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.	MICRO	2016	DBLP DOI BibTeX RDF
11	Arthur Perais, André Seznec	Cost effective physical register sharing.	HPCA	2016	DBLP DOI BibTeX RDF
11	Mengyao Jin, Haohuan Fu, Zihong Lv, Guangwen Yang	Libra: an automated code generation and tuning framework for register-limited stencils on GPUs.	Conf. Computing Frontiers	2016	DBLP DOI BibTeX RDF
11	Laure Daviaud, Pierre-Alain Reynier, Jean-Marc Talbot	A Generalised Twinning Property for Minimisation of Cost Register Automata.	LICS	2016	DBLP DOI BibTeX RDF
11	Shuo Wang 0009, Yun Liang 0001, Chao Zhang 0007, Xiaolong Xie, Guangyu Sun 0003, Yongpan Liu, Yu Wang 0002, Xiuhong Li	Performance-centric register file design for GPUs using racetrack memory.	ASP-DAC	2016	DBLP DOI BibTeX RDF
11	Menghui Xu, Xiao Liang 0005, Chuan Zhang 0001, Zhizheng Wu 0003, Xiaohu You 0001	Stochastic BP Polar Decoding and Architecture with Efficient Re-Randomization and Directive Register.	SiPS	2016	DBLP DOI BibTeX RDF
11	Patricia Bouyer, Nicolas Markey, Mickael Randour, Arnaud Sangnier, Daniel Stan	Reachability in Networks of Register Protocols under Stochastic Schedulers.	ICALP	2016	DBLP DOI BibTeX RDF
11	Roberto Castañeda Lozano, Mats Carlsson, Gabriel Hjort Blindell, Christian Schulte 0001	Register allocation and instruction scheduling in Unison.	CC	2016	DBLP DOI BibTeX RDF
11	Lukasz Domagala, Duco van Amstel, Fabrice Rastello, P. Sadayappan	Register allocation and promotion through combined instruction scheduling and loop unrolling.	CC	2016	DBLP DOI BibTeX RDF
11	Wei He, Jakub Breier, Shivam Bhasin, Dirmanto Jap, Hock Guan Ong, Chee Lip Gan	Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 Nm FPGA.	SPACE	2016	DBLP DOI BibTeX RDF
11	Silvia Bonomi, Antonella Del Pozzo, Maria Potop-Butucaru	Tight self-stabilizing mobile byzantine-tolerant atomic register.	ICDCN	2016	DBLP DOI BibTeX RDF
11	Jori Winderickx, Joan Daemen, Nele Mentens	Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs.	FPL	2016	DBLP DOI BibTeX RDF
11	Sang-Chul Kim	Software monitoring system for register marker detection.	ICUFN	2016	DBLP DOI BibTeX RDF
11	Atieh Zarabzadeh, Ronan McDonnell, Stefan Paz Berrios, John Dempsey, Emma Harrington, Susan M. Smith, Tom Fahey	Utility of Electronic International Register of Clinical Prediction Rules Relevant to Primary Care.	CBMS	2016	DBLP DOI BibTeX RDF
11	You Zhou 0003, Yian Zhou, Min Chen 0007, Qingjun Xiao, Shigang Chen	Highly Compact Virtual Counters for Per-Flow Traffic Measurement through Register Sharing.	GLOBECOM	2016	DBLP DOI BibTeX RDF
11	Parvaneh Babari, Karin Quaas, Mahsa Shirmohammadi	Synchronizing Data Words for Register Automata.	MFCS	2016	DBLP DOI BibTeX RDF
11	Teng Yang, Peter R. Kinget, Mingoo Seok	Register file circuits and post-deployment framework to monitor aging effects in field.	ESSCIRC	2016	DBLP DOI BibTeX RDF
11	Achour Mostéfaoui, Michel Raynal	Time-Efficient Read/Write Register in Crash-Prone Asynchronous Message-Passing Systems.	NETYS	2016	DBLP DOI BibTeX RDF
11	Markus Weinhardt	Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm.	ARC	2016	DBLP DOI BibTeX RDF
11	Víctor H. Flores-Morales, Byron G. Contreras-Bermeo, Freddy L. Bueno-Palomeque, Luis Javier Serpa-Andrade	Analysis of a Mobile System to Register the Kinematic Parameters in Ankle, Knee, and Hip based in Inertial Sensors.	icSPORTS	2016	DBLP DOI BibTeX RDF
11	Eli Ben-Sasson, Matan Hamilis, Mark Silberstein, Eran Tromer	Fast Multiplication in Binary Fields on GPUs via Register Cache.	ICS	2016	DBLP DOI BibTeX RDF
11	Shao-Chung Wang, Li-Chen Kan, Yuan-Shin Hwang, Jenq Kuen Lee	Energy Efficient Affine Register File for GPU Microarchitecture.	ICPP Workshops	2016	DBLP DOI BibTeX RDF
11	Mengyao Jin, Haohuan Fu, Zihong Lv, Guangwen Yang	Graph-Oriented Code Transformation Approach for Register-Limited Stencils on GPUs.	CCGrid	2016	DBLP DOI BibTeX RDF
11	Filip Mazowiecki, Cristian Riveros	Copyless Cost-Register Automata: Structure, Expressiveness, and Closure Properties.	STACS	2016	DBLP DOI BibTeX RDF
11	Kathrin Bögelsack, Sven Michaelis	Mapping Norway - A Method to Register and Survey the Status of Accessibility.	UD	2016	DBLP DOI BibTeX RDF
11	Ehsan Atoofian	Temperature-Aware Register Mapping in GPGPUs.	Trustcom/BigDataSE/ISPA	2016	DBLP DOI BibTeX RDF
11	Tianjian Li, Li Jiang 0002, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang	CNFET-based high throughput register file architecture.	ICCD	2016	DBLP DOI BibTeX RDF
11	Elliott Forbes, Eric Rotenberg	Fast register consolidation and migration for heterogeneous multi-core processors.	ICCD	2016	DBLP DOI BibTeX RDF
11	Travis Meade, Yier Jin, Mark M. Tehranipoor, Shaojie Zhang	Gate-level netlist reverse engineering for hardware security: Control logic register identification.	ISCAS	2016	DBLP DOI BibTeX RDF
11	Miguel Garcia-Bosque, Carlos Sánchez-Azqueta, Santiago Celma	Secure communication system based on a logistic map and a linear feedback shift register.	ISCAS	2016	DBLP DOI BibTeX RDF
11	Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike	Implementation of pseudo linear feedback shift register physical unclonable function on silicon.	ISCAS	2016	DBLP DOI BibTeX RDF
11	Abhishek Roy 0002, Benton H. Calhoun	Exploring circuit robustness to power supply variation in low-voltage latch and register-based digital systems.	ISCAS	2016	DBLP DOI BibTeX RDF
11	Tiago Oliveira 0008, Ricardo Mendes, Alysson Neves Bessani	Exploring Key-Value Stores in Multi-Writer Byzantine-Resilient Register Emulations.	OPODIS	2016	DBLP DOI BibTeX RDF
11	Kyle Guan, Junho Cho, Peter J. Winzer	A computationally efficient shift-register based information scrambling approach to physical layer security in MIMO-SDM systems.	OFC	2016	DBLP BibTeX RDF
11	Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin	Register grouping for synthesis of clock gating logic.	ICICDT	2016	DBLP DOI BibTeX RDF
11	Salin Junsangsri, Jie Han 0001, Fabrizio Lombardi	A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF
11	Hang Zhang, Xuhao Chen 0001, Nong Xiao, Fang Liu 0002, Zhiguang Chen	Red-Shield: Shielding Read Disturbance for STT-RAM Based Register Files on GPUs.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF