Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura	A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns.	IOLTS	2018	DBLP DOI BibTeX RDF
11	Jennifer L. Welch	Complexity of Multi-Valued Register Simulations: A Retrospective (Keynote).	OPODIS	2018	DBLP DOI BibTeX RDF
11	Stefano D'Amico, Stefano Marinaci	Low-power reference buffer for successive approximation register analog-to-digital converters.	ICICDT	2018	DBLP DOI BibTeX RDF
11	Tarun Agrawal, Anjan Kumar, Priyanka, Pooja Aggarwal, Syed Saad Tirmizi	LVCMOS Based 4-Bit Register.	ICCCNT	2018	DBLP DOI BibTeX RDF
11	Johanne Cohen, George Manoussakis, Laurence Pilard, Devan Sohier	A Self-Stabilizing Algorithm for Maximal Matching in Link-Register Model.	SIROCCO	2018	DBLP DOI BibTeX RDF
11	Duarte Nuno Gonçalves-Ferreira, Mariana Leite, Cátia Santos-Pereira, Manuel Eduardo Correia, Luis Filipe Coelho Antunes, Ricardo Cruz-Correia	HS.Register - An Audit-Trail Tool to Respond to the General Data Protection Regulation (GDPR).	MIE	2018	DBLP DOI BibTeX RDF
11	Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan	Associative instruction reordering to alleviate register pressure.	SC	2018	DBLP BibTeX RDF
11	Junhong Liu, Xin He, Weifeng Liu 0002, Guangming Tan	Register-based implementation of the sparse general matrix-matrix multiplication on GPUs.	PPoPP	2018	DBLP DOI BibTeX RDF
11	Prashant Singh Rawat, Fabrice Rastello, Aravind Sukumaran-Rajam, Louis-Noël Pouchet, Atanas Rountev, P. Sadayappan	Register optimizations for stencils on GPUs.	PPoPP	2018	DBLP DOI BibTeX RDF
11	Adrien Boiret, Radoslaw Piórkowski, Janusz Schmude	Reducing Transducer Equivalence to Register Automata Problems Solved by "Hilbert Method".	FSTTCS	2018	DBLP DOI BibTeX RDF
11	Xin Wang 0056, Wei Zhang 0002	Energy-Efficient DNN Computing on GPUs Through Register File Management.	HPEC	2018	DBLP DOI BibTeX RDF
11	Farzad Khorasani, Hodjat Asghari Esfeden, Amin Farmahini Farahani, Nuwan Jayasena, Vivek Sarkar	RegMutex: Inter-Warp GPU Register Time-Sharing.	ISCA	2018	DBLP DOI BibTeX RDF
11	T. S. Manivannan, Meena Srinivasan	A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches.	VDAT	2018	DBLP DOI BibTeX RDF
11	Corey Miller, Danielle Silverman, Vanesa Jurica, Elizabeth Schroeder Richerson, Rodney Morris, Elisabeth Mallard	Embedding Register-Aware MT into the CAT Workflow.	AMTA (2)	2018	DBLP BibTeX RDF
11	Tak-Sum Wong, John Lee 0001	Register-sensitive Translation: a Case Study of Mandarin and Cantonese (Non-archival Extended Abstract).	AMTA (1)	2018	DBLP BibTeX RDF
11	Roberto Castañeda Lozano	Constraint-Based Register Allocation and Instruction Scheduling.		2018	RDF
11		Property Register.	Encyclopedia of GIS	2017	DBLP DOI BibTeX RDF
11	You Zhou 0003, Yian Zhou, Min Chen 0007, Shigang Chen	Persistent Spread Measurement for Big Network Data Based on Register Intersection.	Proc. ACM Meas. Anal. Comput. Syst.	2017	DBLP DOI BibTeX RDF
11	Erzsébet Csuhaj-Varjú, Rudolf Freund, György Vaszil	Watson-Crick T0L Systems and Red-Green Register Machines.	Fundam. Informaticae	2017	DBLP DOI BibTeX RDF
11	Michal Chromiak	Heterogeneous Indexing Register for Object Database.	Ann. UMCS Informatica	2017	DBLP DOI BibTeX RDF
11	Sparsh Mittal	A survey of techniques for designing and managing CPU register file.	Concurr. Comput. Pract. Exp.	2017	DBLP DOI BibTeX RDF
11	Jinlong Yan, Qi Zeng, Yuan Liang, Lei He 0001, Zhengping Li	Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems.	IEEE Access	2017	DBLP DOI BibTeX RDF
11	Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie	FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
11	Naifeng Jing, Shunning Jiang, Shuang Chen 0002, Jingjie Zhang, Li Jiang 0002, Chao Li 0009, Xiaoyao Liang	Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
11	Reiley Jeyapaul, Roberto Flores, Alfonso Ávila 0001, Aviral Shrivastava	Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
11	Nastaran Rajaei, Ramin Rajaei, Mahmoud Tabandeh	A soft error tolerant register file for highly reliable microprocessor design.	Int. J. High Perform. Syst. Archit.	2017	DBLP DOI BibTeX RDF
11	Robert Carroll, Sreeram V. Ramagopalan, Javier Cid-Ruzafa, Dimitra Lambrelli, Laura McDonald	An analysis of characteristics of post-authorisation studies registered on the ENCePP EU PAS Register.	F1000Research	2017	DBLP DOI BibTeX RDF
11	Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai	Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
11	Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai	Skewed Multistaged Multibanked Register File for Area and Energy Efficiency.	IEICE Trans. Inf. Syst.	2017	DBLP DOI BibTeX RDF
11	Vikas Mahor, Manisha Pattanaik	An Aging-Aware Reliable FinFET-Based Low-Power 32-Word $\times $ 32-bit Register File.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
11	Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, Seyed Vahid Azhari	Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file.	IET Comput. Digit. Tech.	2017	DBLP DOI BibTeX RDF
11	Qingjun Xiao, Shigang Chen, You Zhou 0003, Min Chen 0007, Junzhou Luo, Tengli Li, Yibei Ling	Cardinality Estimation for Elephant Flows: A Compact Solution Based on Virtual Register Sharing.	IEEE/ACM Trans. Netw.	2017	DBLP DOI BibTeX RDF
11	Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv	Generating ASIPs with Reduced Number of Connections to the Register-File.	Int. J. Parallel Program.	2017	DBLP DOI BibTeX RDF
11	Jeongrim Seo, Seok-Jeong Song, Dowon Kim, Hyoungsik Nam	Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs.	Displays	2017	DBLP DOI BibTeX RDF
11	Sondre Rønjom	Improving algebraic attacks on stream ciphers based on linear feedback shift register over $$\mathbb {F}_{2^k}$$ F 2 k.	Des. Codes Cryptogr.	2017	DBLP DOI BibTeX RDF
11	Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio G. M. Strollo	A SISO Register Circuit Tailored for Input Data with Low Transition Probability.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
11	Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Hai Li 0001	An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
11	Sparsh Mittal	A Survey of Techniques for Architecting and Managing GPU Register File.	IEEE Trans. Parallel Distributed Syst.	2017	DBLP DOI BibTeX RDF
11	Je-Hyung Lee, Soo-Mook Moon, Jinpyo Park	Region-based dual bank register allocation for reduced instruction encoding Architectures.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
11	Chenhao Xie 0001, Jingweijia Tan, Mingsong Chen, Yang Yi 0002, Lu Peng 0001, Xin Fu	Emerging technology enabled energy-efficient GPGPUs register file.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
11	Andrzej S. Murawski, Steven J. Ramsay, Nikos Tzevelekos	Reachability in pushdown register automata.	J. Comput. Syst. Sci.	2017	DBLP DOI BibTeX RDF
11	Eric Allender, Andreas Krebs, Pierre McKenzie	Better Complexity Bounds for Cost Register Machines.	Electron. Colloquium Comput. Complex.	2017	DBLP BibTeX RDF
11	D. C. Kiran, S. Gurunarayanan 0001, Janardan Prasad Misra, Munish Bhatia	Register allocation for fine grain threads on multicore processor.	J. King Saud Univ. Comput. Inf. Sci.	2017	DBLP DOI BibTeX RDF
11	Adrian Florea, Arpad Gellert	Developing Heuristics for the Graph Coloring Problem Applied to Register Allocation in Embedded Systems.	J. Multim. Process. Technol.	2017	DBLP BibTeX RDF
11	Xuesong Su, Hui Wu 0001, Jingling Xue	An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors.	ACM Trans. Embed. Comput. Syst.	2017	DBLP DOI BibTeX RDF
11	Pradeep Kumar Biswal, Santosh Biswas	On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
11	Hagit Attiya, Hyun Chul Chung, Faith Ellen, Saptaparni Kumar, Jennifer L. Welch	Simulating a Shared Register in a System that Never Stops Changing.	CoRR	2017	DBLP BibTeX RDF
11	Vishwesh Jatala, Jayvant Anantpur, Amey Karkare	GREENER: A Tool for Improving Energy Efficiency of Register Files.	CoRR	2017	DBLP BibTeX RDF
11	Karin Quaas, Mahsa Shirmohammadi	Synchronizing Data Words for Register Automata.	CoRR	2017	DBLP BibTeX RDF
11	Johanne Cohen, George Manoussakis, Laurence Pilard, Devan Sohier	A self-stabilizing algorithm for maximal matching in link-register model in $O(nΔ^3)$ moves.	CoRR	2017	DBLP BibTeX RDF
11	Yu-Fang Chen 0001, Ondrej Lengál, Tony Tan, Zhilin Wu	Register automata with linear arithmetic.	CoRR	2017	DBLP BibTeX RDF
11		One Password: An Encryption Scheme for Hiding Users' Register Information.	CoRR	2017	DBLP BibTeX RDF
11	Siamak Solat	RDV: Register, Deposit, Vote: a full decentralized consensus algorithm for blockchain based networks.	CoRR	2017	DBLP BibTeX RDF
11	You Zhou 0003, Yian Zhou, Min Chen 0007, Shigang Chen	Persistent Spread Measurement for Big Network Data Based on Register Intersection.	CoRR	2017	DBLP BibTeX RDF
11	Mauro Ianni, Alessandro Pellegrini 0001, Francesco Quaglia	A Wait-free Multi-word Atomic (1, N) Register for Large-scale Data Sharing on Multi-core Machines.	CoRR	2017	DBLP BibTeX RDF
11	Gregory V. Chockler, Alexander Spiegelman	Space Complexity of Fault Tolerant Register Emulations.	CoRR	2017	DBLP BibTeX RDF
11	John Wallert, Mattia Tomasoni, Guy Madison, Claes Held	Predicting two-year survival versus non-survival after first myocardial infarction using machine learning and Swedish national register data.	BMC Medical Informatics Decis. Mak.	2017	DBLP DOI BibTeX RDF
11	Jie Lin, Jiann-Shiun Yuan	A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
11	Asmita Pal, Aatreyi Bal, Koushik Chakraborty, Sanghamitra Roy	Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
11	Marcio Gonçalves, Mateus Saquetti, Fernanda Lima Kastensmidt, José Rodrigo Azambuja	A low-level software-based fault tolerance approach to detect SEUs in GPUs' register files.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
11	Khawar Sarfraz, Mansun Chan	A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
11	Meng-Chou Chang, Po-Hung Yang, Ze-Gang Pan	Register-Less NULL Convention Logic.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
11	Hu He 0001, Xu Yang 0003, Yanjun Zhang	On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage.	Comput. J.	2017	DBLP DOI BibTeX RDF
11	Yongwoo Lee 0002, Young-Sik Kim, Jong-Seon No	Ciphertext-Only Attack on Linear Feedback Shift Register-Based Esmaeili-Gulliver Cryptosystem.	IEEE Commun. Lett.	2017	DBLP DOI BibTeX RDF
11	Josef Eisl, Stefan Marr, Thomas Würthinger, Hanspeter Mössenböck	Trace Register Allocation Policies: Compile-time vs. Performance Trade-offs.	ManLang	2017	DBLP DOI BibTeX RDF
11	Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu	Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions.	LCTES	2017	DBLP DOI BibTeX RDF
11	Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu	Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation.	PACT	2017	DBLP DOI BibTeX RDF
11	Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan	POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs.	PACT	2017	DBLP DOI BibTeX RDF
11	Li Tan, Nathan DeBardeleben, Qiang Guan, Sean Blanchard, Michael Lang 0003	RSVP: Soft Error Resilient Power Savings at Near-Threshold Voltage Using Register Vulnerability.	DSN Workshops	2017	DBLP DOI BibTeX RDF
11	Florian Giesemann, Guillermo Payá Vayá, Lukas Gerlach 0001, Holger Blume, Fabian Pflug, Gabriele von Voigt	Using a genetic algorithm approach to reduce register file pressure during instruction scheduling.	SAMOS	2017	DBLP DOI BibTeX RDF
11	Yong Chen 0014, Emil Matús, Gerhard P. Fettweis	Register-Exchange Based Connection Allocator for Circuit Switching NoCs.	PDP	2017	DBLP DOI BibTeX RDF
11	Emmanuelle Anceaume, Romaric Ludinard, Maria Potop-Butucaru, Frédéric Tronel	Bitcoin a Distributed Shared Register.	SSS	2017	DBLP DOI BibTeX RDF
11	Ignace Tchangou Toudjeu, Prosper Zanu Sotenga	Design and implementation of an RFID based smart attendance register.	AFRICON	2017	DBLP DOI BibTeX RDF
11	Franck Michel, Olivier Gargominy, Sandrine Tercerie, Catherine Faron-Zucker	A Model to Represent Nomenclatural and Taxonomic Information as Linked Data. Application to the French Taxonomic Register, TAXREF.	S4BioDiv@ISWC	2017	DBLP BibTeX RDF
11	Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Baradaran Tahoori, Adwait Jog, Jeffrey S. Vetter	Architecting SOT-RAM Based GPU Register File.	ISVLSI	2017	DBLP DOI BibTeX RDF
11	Lei Yang, Shaolin Xie, Zijun Liu, Xueliang Du, Donglin Wang	A self-indexed register file for efficient arithmetical computing hardware.	CEEC	2017	DBLP DOI BibTeX RDF
11	Armaiti Ardeshiricham, Wei Hu 0008, Joshua Marxen, Ryan Kastner	Register transfer level information flow tracking for provably secure hardware design.	DATE	2017	DBLP DOI BibTeX RDF
11	Alireza Namazi, Meisam Abdollahi	PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files.	DSD	2017	DBLP DOI BibTeX RDF
11	Yu-Fang Chen 0001, Ondrej Lengál, Tony Tan, Zhilin Wu	Register automata with linear arithmetic.	LICS	2017	DBLP DOI BibTeX RDF
11	Jan Schat	ISO26262-compliant soft-error mitigation in register banks.	ETS	2017	DBLP DOI BibTeX RDF
11	João F. N. Carvalho, Bruno Luan de Sousa, Marcus R. Araújo, Mariza A. S. Bigonha	The Register Allocation and Instruction Scheduling Challenge.	SBLP	2017	DBLP DOI BibTeX RDF
11	Christina Keller	A Third Person in the Room: a Case Study of the Swedish rheumatoid Register.	ECIS	2017	DBLP BibTeX RDF
11	Henning Puttnies, Christoph Niemann 0002, Sascha Rohde, Dirk Timmermann, Joerg Schacht	Towards software performance estimation based on register-transfer level descriptions.	NORCAS	2017	DBLP DOI BibTeX RDF
11	You Zhou 0003, Yian Zhou, Min Chen 0007, Shigang Chen	Persistent Spread Measurement for Big Network Data Based on Register Intersection.	SIGMETRICS (Abstracts)	2017	DBLP DOI BibTeX RDF
11	Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel	Exploiting cache locality to speedup register clustering.	SBCCI	2017	DBLP DOI BibTeX RDF
11	Eric Allender, Andreas Krebs, Pierre McKenzie	Better Complexity Bounds for Cost Register Automata.	MFCS	2017	DBLP DOI BibTeX RDF
11	Abubaker Sasi, Amirali Amirsoleimani, Arash Ahmadi, Majid Ahmadi	Hybrid memristor-CMOS based linear feedback shift register design.	ICECS	2017	DBLP DOI BibTeX RDF
11	Yu Hong, Chuck-Jee Chau, Andrew Horner	Mode and Register Categorizations for Predicting Mood in Classical Piano Music2.	ICMC	2017	DBLP BibTeX RDF
11	Apan Qasem, Samuel Teich	Mitigating register pressure in GPU kernels for improved energy efficiency.	IGSC	2017	DBLP DOI BibTeX RDF
11	Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang 0002	Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design.	ICCAD	2017	DBLP DOI BibTeX RDF
11	Xin Wang 0056, Wei Zhang 0002	Drowsy Register Files for Reducing GPU Leakage Energy.	ICPADS	2017	DBLP DOI BibTeX RDF
11	Daniel Gabric, Joe Sawada	A de Bruijn Sequence Construction by Concatenating Cycles of the Complemented Cycling Register.	WORDS	2017	DBLP DOI BibTeX RDF
11	Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Efficient pulsed-latch implementation for multiport register files: work-in-progress.	CASES	2017	DBLP DOI BibTeX RDF
11	Gregory V. Chockler, Alexander Spiegelman	Space Complexity of Fault-Tolerant Register Emulations.	PODC	2017	DBLP DOI BibTeX RDF
11	Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park 0001	Bit-width reduction and customized register for low cost convolutional neural network accelerator.	ISLPED	2017	DBLP DOI BibTeX RDF
11	Siva Nishok Dhanuskodi, Daniel E. Holcomb	An improved clocking methodology for energy efficient low area AES architectures using register renaming.	ISLPED	2017	DBLP DOI BibTeX RDF
11	Xin Wang 0056, Wei Zhang 0002	GPU Register Packing: Dynamically Exploiting Narrow-Width Operands to Improve Performance.	TrustCom/BigDataSE/ICESS	2017	DBLP DOI BibTeX RDF
11	Luigi Tatarelli, Marco Schillaci, Adriana Galli	The implementation of the Italian Register of Railway Infrastructure.	MT-ITS	2017	DBLP DOI BibTeX RDF
11	Sean Kramer, Zhiming Zhang, Jaya Dofe, Qiaoyan Yu	Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
11	Francisco Candel, Alejandro Valero, Salvador Petit, Darío Suárez Gracia, Julio Sahuquillo	Exploiting Data Compression to Mitigate Aging in GPU Register Files.	SBAC-PAD	2017	DBLP DOI BibTeX RDF