|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 4401 occurrences of 2030 keywords
|
|
|
Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura |
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018, pp. 228-231, 2018, IEEE, 978-1-5386-5992-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Jennifer L. Welch |
Complexity of Multi-Valued Register Simulations: A Retrospective (Keynote). ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: 22nd International Conference on Principles of Distributed Systems, OPODIS 2018, December 17-19, 2018, Hong Kong, China, pp. 1:1-1:1, 2018, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-098-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Stefano D'Amico, Stefano Marinaci |
Low-power reference buffer for successive approximation register analog-to-digital converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018, pp. 45-48, 2018, IEEE, 978-1-5386-2550-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Tarun Agrawal, Anjan Kumar, Priyanka, Pooja Aggarwal, Syed Saad Tirmizi |
LVCMOS Based 4-Bit Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 9th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2018, Bengaluru, India, July 10-12, 2018, pp. 1-3, 2018, IEEE, 978-1-5386-4430-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Johanne Cohen, George Manoussakis, Laurence Pilard, Devan Sohier |
A Self-Stabilizing Algorithm for Maximal Matching in Link-Register Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIROCCO ![In: Structural Information and Communication Complexity - 25th International Colloquium, SIROCCO 2018, Ma'ale HaHamisha, Israel, June 18-21, 2018, Revised Selected Papers, pp. 14-19, 2018, Springer, 978-3-030-01324-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Duarte Nuno Gonçalves-Ferreira, Mariana Leite, Cátia Santos-Pereira, Manuel Eduardo Correia, Luis Filipe Coelho Antunes, Ricardo Cruz-Correia |
HS.Register - An Audit-Trail Tool to Respond to the General Data Protection Regulation (GDPR). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIE ![In: Building Continents of Knowledge in Oceans of Data: The Future of Co-Created eHealth - Proceedings of MIE 2018, Medical Informatics Europe, Gothenburg, Sweden, April 24-26, 2018, pp. 81-85, 2018, IOS Press, 978-1-61499-851-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan |
Associative instruction reordering to alleviate register pressure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018, Dallas, TX, USA, November 11-16, 2018, pp. 46:1-46:13, 2018, IEEE / ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
11 | Junhong Liu, Xin He, Weifeng Liu 0002, Guangming Tan |
Register-based implementation of the sparse general matrix-matrix multiplication on GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2018, Vienna, Austria, February 24-28, 2018, pp. 407-408, 2018, ACM, 978-1-4503-4982-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Prashant Singh Rawat, Fabrice Rastello, Aravind Sukumaran-Rajam, Louis-Noël Pouchet, Atanas Rountev, P. Sadayappan |
Register optimizations for stencils on GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2018, Vienna, Austria, February 24-28, 2018, pp. 168-182, 2018, ACM, 978-1-4503-4982-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Adrien Boiret, Radoslaw Piórkowski, Janusz Schmude |
Reducing Transducer Equivalence to Register Automata Problems Solved by "Hilbert Method". ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: 38th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, FSTTCS 2018, December 11-13, 2018, Ahmedabad, India, pp. 48:1-48:16, 2018, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-093-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Xin Wang 0056, Wei Zhang 0002 |
Energy-Efficient DNN Computing on GPUs Through Register File Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPEC ![In: 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018, Waltham, MA, USA, September 25-27, 2018, pp. 1-7, 2018, IEEE, 978-1-5386-5989-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Farzad Khorasani, Hodjat Asghari Esfeden, Amin Farmahini Farahani, Nuwan Jayasena, Vivek Sarkar |
RegMutex: Inter-Warp GPU Register Time-Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018, Los Angeles, CA, USA, June 1-6, 2018, pp. 816-828, 2018, IEEE Computer Society, 978-1-5386-5984-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | T. S. Manivannan, Meena Srinivasan |
A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers, pp. 521-537, 2018, Springer, 978-981-13-5949-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
11 | Corey Miller, Danielle Silverman, Vanesa Jurica, Elizabeth Schroeder Richerson, Rodney Morris, Elisabeth Mallard |
Embedding Register-Aware MT into the CAT Workflow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMTA (2) ![In: Proceedings of the 13th Conference of the Association for Machine Translation in the Americas, AMTA 2018, Boston, MA, USA, March 17-21, 2018 - Volume 2: User Papers, pp. 275-282, 2018, Association for Machine Translation in the Americas. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
11 | Tak-Sum Wong, John Lee 0001 |
Register-sensitive Translation: a Case Study of Mandarin and Cantonese (Non-archival Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMTA (1) ![In: Proceedings of the 13th Conference of the Association for Machine Translation in the Americas, AMTA 2018, Boston, MA, USA, March 17-21, 2018 - Volume 1: Research Papers, pp. 89-96, 2018, Association for Machine Translation in the Americas. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
11 | Roberto Castañeda Lozano |
Constraint-Based Register Allocation and Instruction Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2018 |
RDF |
|
11 | |
Property Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of GIS ![In: Encyclopedia of GIS., pp. 1678, 2017, Springer, 978-3-319-17884-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | You Zhou 0003, Yian Zhou, Min Chen 0007, Shigang Chen |
Persistent Spread Measurement for Big Network Data Based on Register Intersection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Meas. Anal. Comput. Syst. ![In: Proc. ACM Meas. Anal. Comput. Syst. 1(1), pp. 15:1-15:29, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Erzsébet Csuhaj-Varjú, Rudolf Freund, György Vaszil |
Watson-Crick T0L Systems and Red-Green Register Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fundam. Informaticae ![In: Fundam. Informaticae 155(1-2), pp. 111-129, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Michal Chromiak |
Heterogeneous Indexing Register for Object Database. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. UMCS Informatica ![In: Ann. UMCS Informatica 16(2), pp. 7, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Sparsh Mittal |
A survey of techniques for designing and managing CPU register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 29(4), 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Jinlong Yan, Qi Zeng, Yuan Liang, Lei He 0001, Zhengping Li |
Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 5, pp. 1649-1657, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie |
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 725-734, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Naifeng Jing, Shunning Jiang, Shuang Chen 0002, Jingjie Zhang, Li Jiang 0002, Chao Li 0009, Xiaoyao Liang |
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 520-533, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Reiley Jeyapaul, Roberto Flores, Alfonso Ávila 0001, Aviral Shrivastava |
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 547-555, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Nastaran Rajaei, Ramin Rajaei, Mahmoud Tabandeh |
A soft error tolerant register file for highly reliable microprocessor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 7(3), pp. 113-119, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Robert Carroll, Sreeram V. Ramagopalan, Javier Cid-Ruzafa, Dimitra Lambrelli, Laura McDonald |
An analysis of characteristics of post-authorisation studies registered on the ENCePP EU PAS Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
F1000Research ![In: F1000Research 6, pp. 1447-, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai |
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(3), pp. 232-244, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai |
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 100-D(4), pp. 822-837, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Vikas Mahor, Manisha Pattanaik |
An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 36(12), pp. 4789-4808, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Bahar Asgari, Mahdi Fazeli, Ahmad Patooghy, Seyed Vahid Azhari |
Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 11(1), pp. 1-7, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Qingjun Xiao, Shigang Chen, You Zhou 0003, Min Chen 0007, Junzhou Luo, Tengli Li, Yibei Ling |
Cardinality Estimation for Elephant Flows: A Compact Solution Based on Virtual Register Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 25(6), pp. 3738-3752, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv |
Generating ASIPs with Reduced Number of Connections to the Register-File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 45(6), pp. 1461-1487, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Jeongrim Seo, Seok-Jeong Song, Dowon Kim, Hyoungsik Nam |
Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Displays ![In: Displays 49, pp. 65-71, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Sondre Rønjom |
Improving algebraic attacks on stream ciphers based on linear feedback shift register over $$\mathbb {F}_{2^k}$$ F 2 k. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 82(1-2), pp. 27-41, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio G. M. Strollo |
A SISO Register Circuit Tailored for Input Data with Low Transition Probability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(1), pp. 45-51, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Hai Li 0001 |
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(9), pp. 1478-1490, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Sparsh Mittal |
A Survey of Techniques for Architecting and Managing GPU Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 28(1), pp. 16-28, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Je-Hyung Lee, Soo-Mook Moon, Jinpyo Park |
Region-based dual bank register allocation for reduced instruction encoding Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 55, pp. 26-43, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Chenhao Xie 0001, Jingweijia Tan, Mingsong Chen, Yang Yi 0002, Lu Peng 0001, Xin Fu |
Emerging technology enabled energy-efficient GPGPUs register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 50, pp. 175-188, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Andrzej S. Murawski, Steven J. Ramsay, Nikos Tzevelekos |
Reachability in pushdown register automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Syst. Sci. ![In: J. Comput. Syst. Sci. 87, pp. 58-83, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Eric Allender, Andreas Krebs, Pierre McKenzie |
Better Complexity Bounds for Cost Register Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR17, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | D. C. Kiran, S. Gurunarayanan 0001, Janardan Prasad Misra, Munish Bhatia |
Register allocation for fine grain threads on multicore processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. King Saud Univ. Comput. Inf. Sci. ![In: J. King Saud Univ. Comput. Inf. Sci. 29(1), pp. 85-92, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Adrian Florea, Arpad Gellert |
Developing Heuristics for the Graph Coloring Problem Applied to Register Allocation in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Multim. Process. Technol. ![In: J. Multim. Process. Technol. 8(3), pp. 74-87, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Xuesong Su, Hui Wu 0001, Jingling Xue |
An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 16(5s), pp. 120:1-120:21, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Pradeep Kumar Biswal, Santosh Biswas |
On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 67, pp. 88-100, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Hagit Attiya, Hyun Chul Chung, Faith Ellen, Saptaparni Kumar, Jennifer L. Welch |
Simulating a Shared Register in a System that Never Stops Changing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1708.03274, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Vishwesh Jatala, Jayvant Anantpur, Amey Karkare |
GREENER: A Tool for Improving Energy Efficiency of Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1709.04697, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Karin Quaas, Mahsa Shirmohammadi |
Synchronizing Data Words for Register Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1710.02329, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Johanne Cohen, George Manoussakis, Laurence Pilard, Devan Sohier |
A self-stabilizing algorithm for maximal matching in link-register model in $O(nΔ^3)$ moves. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1709.04811, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Yu-Fang Chen 0001, Ondrej Lengál, Tony Tan, Zhilin Wu |
Register automata with linear arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1704.03972, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | |
One Password: An Encryption Scheme for Hiding Users' Register Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1710.04353, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Siamak Solat |
RDV: Register, Deposit, Vote: a full decentralized consensus algorithm for blockchain based networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1707.05091, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | You Zhou 0003, Yian Zhou, Min Chen 0007, Shigang Chen |
Persistent Spread Measurement for Big Network Data Based on Register Intersection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1704.03911, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Mauro Ianni, Alessandro Pellegrini 0001, Francesco Quaglia |
A Wait-free Multi-word Atomic (1, N) Register for Large-scale Data Sharing on Multi-core Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1707.07478, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Gregory V. Chockler, Alexander Spiegelman |
Space Complexity of Fault Tolerant Register Emulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1705.07212, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | John Wallert, Mattia Tomasoni, Guy Madison, Claes Held |
Predicting two-year survival versus non-survival after first myocardial infarction using machine learning and Swedish national register data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMC Medical Informatics Decis. Mak. ![In: BMC Medical Informatics Decis. Mak. 17(1), pp. 99:1-99:11, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Jie Lin, Jiann-Shiun Yuan |
A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 13(3), pp. 497-510, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Asmita Pal, Aatreyi Bal, Koushik Chakraborty, Sanghamitra Roy |
Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 13(3), pp. 419-427, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Marcio Gonçalves, Mateus Saquetti, Fernanda Lima Kastensmidt, José Rodrigo Azambuja |
A low-level software-based fault tolerance approach to detect SEUs in GPUs' register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 76-77, pp. 665-669, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Khawar Sarfraz, Mansun Chan |
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2), pp. 360-372, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Meng-Chou Chang, Po-Hung Yang, Ze-Gang Pan |
Register-Less NULL Convention Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 64-II(3), pp. 314-318, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Hu He 0001, Xu Yang 0003, Yanjun Zhang |
On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 60(9), pp. 1338-1352, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Yongwoo Lee 0002, Young-Sik Kim, Jong-Seon No |
Ciphertext-Only Attack on Linear Feedback Shift Register-Based Esmaeili-Gulliver Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Lett. ![In: IEEE Commun. Lett. 21(5), pp. 971-974, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Josef Eisl, Stefan Marr, Thomas Würthinger, Hanspeter Mössenböck |
Trace Register Allocation Policies: Compile-time vs. Performance Trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ManLang ![In: Proceedings of the 14th International Conference on Managed Languages and Runtimes, ManLang 2017, Prague, Czech Republic, September 27 - 29, 2017, pp. 92-104, 2017, ACM, 978-1-4503-5340-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu |
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2017, Barcelona, Spain, June 21-22, 2017, pp. 31-40, 2017, ACM, 978-1-4503-5030-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu |
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017, Portland, OR, USA, September 9-13, 2017, pp. 343-355, 2017, IEEE Computer Society, 978-1-5090-6764-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan |
POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017, Portland, OR, USA, September 9-13, 2017, pp. 158-159, 2017, IEEE Computer Society, 978-1-5090-6764-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Li Tan, Nathan DeBardeleben, Qiang Guan, Sean Blanchard, Michael Lang 0003 |
RSVP: Soft Error Resilient Power Savings at Near-Threshold Voltage Using Register Vulnerability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN Workshops ![In: 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN Workshops 2017, Denver, CO, USA, June 26-29, 2017, pp. 91-98, 2017, IEEE Computer Society, 978-1-5386-2272-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Florian Giesemann, Guillermo Payá Vayá, Lukas Gerlach 0001, Holger Blume, Fabian Pflug, Gabriele von Voigt |
Using a genetic algorithm approach to reduce register file pressure during instruction scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017, pp. 179-187, 2017, IEEE, 978-1-5386-3437-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Yong Chen 0014, Emil Matús, Gerhard P. Fettweis |
Register-Exchange Based Connection Allocator for Circuit Switching NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2017, St. Petersburg, Russia, March 6-8, 2017, pp. 559-566, 2017, IEEE Computer Society, 978-1-5090-6058-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Emmanuelle Anceaume, Romaric Ludinard, Maria Potop-Butucaru, Frédéric Tronel |
Bitcoin a Distributed Shared Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSS ![In: Stabilization, Safety, and Security of Distributed Systems - 19th International Symposium, SSS 2017, Boston, MA, USA, November 5-8, 2017, Proceedings, pp. 456-468, 2017, Springer, 978-3-319-69083-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Ignace Tchangou Toudjeu, Prosper Zanu Sotenga |
Design and implementation of an RFID based smart attendance register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFRICON ![In: IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, pp. 748-751, 2017, IEEE, 978-1-5386-2775-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Franck Michel, Olivier Gargominy, Sandrine Tercerie, Catherine Faron-Zucker |
A Model to Represent Nomenclatural and Taxonomic Information as Linked Data. Application to the French Taxonomic Register, TAXREF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
S4BioDiv@ISWC ![In: Proceedings of the 2nd International Workshop on Semantics for Biodiversity co-located with 16th International Semantic Web Conference (ISWC 2017), Vienna, Austria, October 22nd, 2017., 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Baradaran Tahoori, Adwait Jog, Jeffrey S. Vetter |
Architecting SOT-RAM Based GPU Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pp. 38-44, 2017, IEEE Computer Society, 978-1-5090-6762-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Lei Yang, Shaolin Xie, Zijun Liu, Xueliang Du, Donglin Wang |
A self-indexed register file for efficient arithmetical computing hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CEEC ![In: 2017 9th Computer Science and Electronic Engineering Conference, CEEC 2017, Colchester, UK, September 27-29, 2017, pp. 13-18, 2017, IEEE. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Armaiti Ardeshiricham, Wei Hu 0008, Joshua Marxen, Ryan Kastner |
Register transfer level information flow tracking for provably secure hardware design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 1691-1696, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Alireza Namazi, Meisam Abdollahi |
PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, pp. 323-328, 2017, IEEE Computer Society, 978-1-5386-2146-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Yu-Fang Chen 0001, Ondrej Lengál, Tony Tan, Zhilin Wu |
Register automata with linear arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: 32nd Annual ACM/IEEE Symposium on Logic in Computer Science, LICS 2017, Reykjavik, Iceland, June 20-23, 2017, pp. 1-12, 2017, IEEE Computer Society, 978-1-5090-3018-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Jan Schat |
ISO26262-compliant soft-error mitigation in register banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, pp. 1-2, 2017, IEEE, 978-1-5090-5457-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | João F. N. Carvalho, Bruno Luan de Sousa, Marcus R. Araújo, Mariza A. S. Bigonha |
The Register Allocation and Instruction Scheduling Challenge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBLP ![In: Proceedings of the 21st Brazilian Symposium on Programming Languages, SBLP 2017, Fortaleza, CE, Brazil, September 21-22, 2017, pp. 3:1-3:9, 2017, ACM, 978-1-4503-5389-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Christina Keller |
A Third Person in the Room: a Case Study of the Swedish rheumatoid Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECIS ![In: 25th European Conference on Information Systems, ECIS 2017, Guimarães, Portugal, June 5-10, 2017, pp. 51, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Henning Puttnies, Christoph Niemann 0002, Sascha Rohde, Dirk Timmermann, Joerg Schacht |
Towards software performance estimation based on register-transfer level descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip (SoC), Linköping, Sweden, October 23-25, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-2844-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | You Zhou 0003, Yian Zhou, Min Chen 0007, Shigang Chen |
Persistent Spread Measurement for Big Network Data Based on Register Intersection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS (Abstracts) ![In: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 05 - 09, 2017, pp. 67, 2017, ACM, 978-1-4503-5032-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel |
Exploiting cache locality to speedup register clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017, pp. 191-197, 2017, ACM, 978-1-4503-5106-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Eric Allender, Andreas Krebs, Pierre McKenzie |
Better Complexity Bounds for Cost Register Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: 42nd International Symposium on Mathematical Foundations of Computer Science, MFCS 2017, August 21-25, 2017 - Aalborg, Denmark, pp. 24:1-24:14, 2017, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-046-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Abubaker Sasi, Amirali Amirsoleimani, Arash Ahmadi, Majid Ahmadi |
Hybrid memristor-CMOS based linear feedback shift register design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, pp. 62-65, 2017, IEEE, 978-1-5386-1911-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Yu Hong, Chuck-Jee Chau, Andrew Horner |
Mode and Register Categorizations for Predicting Mood in Classical Piano Music2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMC ![In: Proceedings of the 2017 International Computer Music Conference, ICMC 2017, Shanghai, China, October 16-20, 2017, 2017, Michigan Publishing. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
11 | Apan Qasem, Samuel Teich |
Mitigating register pressure in GPU kernels for improved energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IGSC ![In: Eighth International Green and Sustainable Computing Conference, IGSC 2017, Orlando, FL, USA, October 23-25, 2017, pp. 1-7, 2017, IEEE Computer Society, 978-1-5386-3470-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang 0002 |
Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 736-742, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Xin Wang 0056, Wei Zhang 0002 |
Drowsy Register Files for Reducing GPU Leakage Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 23rd IEEE International Conference on Parallel and Distributed Systems, ICPADS 2017, Shenzhen, China, December 15-17, 2017, pp. 632-639, 2017, IEEE Computer Society, 978-1-5386-2129-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Daniel Gabric, Joe Sawada |
A de Bruijn Sequence Construction by Concatenating Cycles of the Complemented Cycling Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WORDS ![In: Combinatorics on Words - 11th International Conference, WORDS 2017, Montréal, QC, Canada, September 11-15, 2017, Proceedings, pp. 49-58, 2017, Springer, 978-3-319-66395-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi |
Efficient pulsed-latch implementation for multiport register files: work-in-progress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic of Korea, October 15-20, 2017, pp. 5:1-5:2, 2017, ACM, 978-1-4503-5184-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Gregory V. Chockler, Alexander Spiegelman |
Space Complexity of Fault-Tolerant Register Emulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the ACM Symposium on Principles of Distributed Computing, PODC 2017, Washington, DC, USA, July 25-27, 2017, pp. 83-92, 2017, ACM, 978-1-4503-4992-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park 0001 |
Bit-width reduction and customized register for low cost convolutional neural network accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Siva Nishok Dhanuskodi, Daniel E. Holcomb |
An improved clocking methodology for energy efficient low area AES architectures using register renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Xin Wang 0056, Wei Zhang 0002 |
GPU Register Packing: Dynamically Exploiting Narrow-Width Operands to Improve Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustCom/BigDataSE/ICESS ![In: 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, pp. 745-752, 2017, IEEE Computer Society, 978-1-5090-4906-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Luigi Tatarelli, Marco Schillaci, Adriana Galli |
The implementation of the Italian Register of Railway Infrastructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MT-ITS ![In: 5th IEEE International Conference on Models and Technologies for Intelligent Transportation Systems, MT-ITS 2017, Naples, Italy, June 26-28, 2017, pp. 439-444, 2017, IEEE, 978-1-5090-6484-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Sean Kramer, Zhiming Zhang, Jaya Dofe, Qiaoyan Yu |
Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017, pp. 483-486, 2017, ACM, 978-1-4503-4972-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
11 | Francisco Candel, Alejandro Valero, Salvador Petit, Darío Suárez Gracia, Julio Sahuquillo |
Exploiting Data Compression to Mitigate Aging in GPU Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, Campinas, Brazil, October 17-20, 2017, pp. 57-64, 2017, IEEE Computer Society, 978-1-5090-1233-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
|
|