Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Fanchen Zhang, Micah Thornton, Jennifer Dworak	When Optimized N-Detect Test Sets are Biased: An Investigation of Cell-Aware-Type Faults and N-Detect Stuck-At ATPG.	NATW	2014	DBLP DOI BibTeX RDF
17	X. Cai, Peter Wohl, Daniel Martin 0002	Fault sharing in a copy-on-write based ATPG system.	ITC	2014	DBLP DOI BibTeX RDF
17	Masahiro Fujita, Alan Mishchenko	Efficient SAT-based ATPG techniques for all multiple stuck-at faults.	ITC	2014	DBLP DOI BibTeX RDF
17	Rahul Shukla, Phong Loi, Ken Pham, Arie Margulis, Kathy Yang, Nagesh Tamarapalli	Application of Test-View Modeling to Hierarchical ATPG.	VLSID	2014	DBLP DOI BibTeX RDF
17	Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy	A Cube-Aware Compaction Method for Scan ATPG.	VLSID	2014	DBLP DOI BibTeX RDF
17	Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis	ATPG for transition faults of pipelined threshold logic circuits.	DTIS	2014	DBLP DOI BibTeX RDF
17	Bernd Becker 0001, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer 0002	Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.	DTIS	2014	DBLP DOI BibTeX RDF
17	Huan Chen 0001, João Marques-Silva 0001	A Two-Variable Model for SAT-Based ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
17	Lung-Jen Lee	Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
17	Christelle Hobeika, Claude Thibeault, Jean-François Boland	Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG.	CoRR	2013	DBLP BibTeX RDF
17	S. Jayanthy, M. C. Bhuvaneswari, M. Prabhu	Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits.	Int. J. Comput. Appl. Technol.	2013	DBLP DOI BibTeX RDF
17	Marcela Simková, Zdenek Kotásek, Cristiana Bolchini	Analysis and comparison of functional verification and ATPG for testing design reliability.	DDECS	2013	DBLP DOI BibTeX RDF
17	Bao Liu 0001, Lu Wang, Juan Portillo	Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction.	MWSCAS	2013	DBLP DOI BibTeX RDF
17	Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo	FOF: Functionally Observable Fault and its ATPG techniques.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
17	Jiri Balcarek, Petr Fiser, Jan Schmidt	Simulation and SAT Based ATPG for Compressed Test Generation.	DSD	2013	DBLP DOI BibTeX RDF
17	Dominik Erb, Michael A. Kochte, Matthias Sauer 0002, Hans-Joachim Wunderlich, Bernd Becker 0001	Accurate Multi-cycle ATPG in Presence of X-Values.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
17	Chin Hai Ang	Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG Testing.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Robert Wille, Rolf Drechsler	Improved SAT-based ATPG: more constraints, better compaction.	ICCAD	2013	DBLP DOI BibTeX RDF
17	Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee 0001	A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique.	ASICON	2013	DBLP DOI BibTeX RDF
17	Matthias Sauer 0002, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker 0001	Early-life-failure detection using SAT-based ATPG.	ITC	2013	DBLP DOI BibTeX RDF
17	X. Cai, Peter Wohl	A distributed-multicore hybrid ATPG system.	ITC	2013	DBLP DOI BibTeX RDF
17	Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li	GPU-based n-detect transition fault ATPG.	DAC	2013	DBLP DOI BibTeX RDF
17	Takanori Moriyasu, Satoshi Ohtake	A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG.	CISIS	2013	DBLP DOI BibTeX RDF
17	Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo	Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool.	IEICE Trans. Inf. Syst.	2012	DBLP DOI BibTeX RDF
17	Huan Chen 0001, João Marques-Silva 0001	TG-Pro: A SAT-based ATPG System.	J. Satisf. Boolean Model. Comput.	2012	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Rolf Drechsler	A Highly Fault-Efficient SAT-Based ATPG Flow.	IEEE Des. Test Comput.	2012	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler	A new SAT-based ATPG for generating highly compacted test sets.	DDECS	2012	DBLP DOI BibTeX RDF
17	Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng	Deterministic ATPG for Low Capture Power Testing.	MTV	2012	DBLP DOI BibTeX RDF
17	Alexander Czutro, Matthias Sauer 0002, Ilia Polian, Bernd Becker 0001	Multi-conditional SAT-ATPG for power-droop testing.	ETS	2012	DBLP DOI BibTeX RDF
17	Dale Meehl, Bassilios Petrakis, Ping Zhang	LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive Circuits.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
17	Sergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, Sung Kyu Lim	TSV Stress-Aware ATPG for 3D Stacked ICs.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
17	Matthias Sauer 0002, Alexander Czutro, Ilia Polian, Bernd Becker 0001	Small-delay-fault ATPG with waveform accuracy.	ICCAD	2012	DBLP DOI BibTeX RDF
17	Ahish Mysore Somashekar, Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi	Non-enumerative generation of statistical path delays for ATPG.	ICCD	2012	DBLP DOI BibTeX RDF
17	Alexander Czutro, Matthias Sauer 0002, Tobias Schubert 0001, Ilia Polian, Bernd Becker 0001	SAT-ATPG using preferences for improved detection of complex defect mechanisms.	VTS	2012	DBLP DOI BibTeX RDF
17	Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen	DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.	ITC	2012	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Rolf Drechsler	Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
17	Robert Wille, Hongyan Zhang 0003, Rolf Drechsler	ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization.	ISVLSI	2011	DBLP DOI BibTeX RDF
17	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	ETS	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
17	Shray Khullar, Swapnil Bahl	Power Aware Shift and Capture ATPG Methodology for Low Power Designs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
17	Pey-Chang Kent Lin, Sunil P. Khatri	Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG.	GENSiPS	2011	DBLP DOI BibTeX RDF
17	Bijan Alizadeh, Masahiro Fujita	Early case splitting and false path detection to improve high level ATPG techniques.	ISCAS	2011	DBLP DOI BibTeX RDF
17	Kameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta	Low Coverage Analysis using dynamic un-testability debug in ATPG.	VTS	2011	DBLP DOI BibTeX RDF
17	V. R. Devanathan, Ishaan Santhosh Shah	Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
17	Kunal P. Ganeshpure, Sandip Kundu	On ATPG for Multiple Aggressor Crosstalk Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
17	Daniel Tille, Stephan Eggersglüß, Rolf Drechsler	Incremental Solving Techniques for SAT-based ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler	MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.	J. Electron. Test.	2010	DBLP DOI BibTeX RDF
17	Hongyan Zhang 0003, Robert Wille, Rolf Drechsler	SAT-based ATPG for reversible circuits.	IDT	2010	DBLP DOI BibTeX RDF
17	Junxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu, Sobeeh Almukhaizim	Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG.	IDT	2010	DBLP DOI BibTeX RDF
17	Jiri Balcarek, Petr Fiser, Jan Schmidt	Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG.	DSD	2010	DBLP DOI BibTeX RDF
17	Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler	Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.	ETS	2010	DBLP DOI BibTeX RDF
17	Bijan Alizadeh, Masahiro Fujita	Guided gate-level ATPG for sequential circuits using a high-level test generation approach.	ASP-DAC	2010	DBLP DOI BibTeX RDF
17	Arani Sinha	Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?	VTS	2010	DBLP DOI BibTeX RDF
17	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	Constrained ATPG for functional RTL circuits using F-Scan.	ITC	2010	DBLP DOI BibTeX RDF
17	Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab	Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.	ITC	2010	DBLP DOI BibTeX RDF
17	X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath	Highly efficient parallel ATPG based on shared memory.	ITC	2010	DBLP DOI BibTeX RDF
17	Sunghoon Chun, Taejin Kim, Sungho Kang	ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
17	Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä	Non-Clausal SAT and ATPG.	Handbook of Satisfiability	2009	DBLP DOI BibTeX RDF
17	Huan Chen 0001, João Marques-Silva 0001	TG-PRO: A new model for SAT-based ATPG.	HLDVT	2009	DBLP DOI BibTeX RDF
17	Görschwin Fey	Deterministic Algorithms for ATPG under Leakage Constraints.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
17	Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker 0001	Dynamic Compaction in SAT-Based ATPG.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
17	Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman	Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
17	Yu Huang 0005, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen	Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Daniel Tille, Rolf Drechsler	Speeding up SAT-Based ATPG Using Dynamic Clause Activation.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
17	Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada	SAT-based ATPG testing of inter- and intra-gate bridging faults.	ECCTD	2009	DBLP DOI BibTeX RDF
17	Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara	A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.	ICCAD	2009	DBLP DOI BibTeX RDF
17	Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li	Low Peak Power ATPG for n-Detection Test.	ISCAS	2009	DBLP DOI BibTeX RDF
17	Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker 0001	ATPG-based grading of strong fault-secureness.	IOLTS	2009	DBLP DOI BibTeX RDF
17	Zhen Chen, Dong Xiang, Boxue Yin	The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost.	VTS	2009	DBLP DOI BibTeX RDF
17	Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson	Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs.	ITC	2009	DBLP DOI BibTeX RDF
17	Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu	Diagnostic test generation for transition faults using a stuck-at ATPG tool.	ITC	2009	DBLP DOI BibTeX RDF
17	Kunal P. Ganeshpure, Sandip Kundu	An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.	VLSI Design	2009	DBLP DOI BibTeX RDF
17	Giuseppe Di Guglielmo	On the validation of embedded systems through functional ATPG.		2009	RDF
17	Arkan Abdulrahman, Spyros Tragoudas	Low-power multi-core ATPG to target concurrency.	Integr.	2008	DBLP DOI BibTeX RDF
17	Sunghoon Chun, YongJoon Kim, Taejin Kim, Myung-Hoon Yang, Sungho Kang 0001	XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults.	ATS	2008	DBLP DOI BibTeX RDF
17	Nitin Yogi, Vishwani D. Agrawal	Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns.	ATS	2008	DBLP DOI BibTeX RDF
17	Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita	Targeting Leakage Constraints during ATPG.	ATS	2008	DBLP DOI BibTeX RDF
17	Marc Hunger, Sybille Hellebrand	Verification and Analysis of Self-Checking Properties through ATPG.	IOLTS	2008	DBLP DOI BibTeX RDF
17	Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz	ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.	DFT	2008	DBLP DOI BibTeX RDF
17	Che-Jen Jerry Chang, Takeo Kobayashi	Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study.	ITC	2008	DBLP DOI BibTeX RDF
17	Heiko Ahrens, Rolf Schlagenhaft, Helmut Lang, V. Srinivasan, Enrico Bruzzano	DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG.	ITC	2008	DBLP DOI BibTeX RDF
17	Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chili-Mou Tseng	Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise.	ITC	2008	DBLP DOI BibTeX RDF
17	Surendra Bommu, Kameshwar Chandrasekar, Rahul Kundu, Sanjay Sengupta	CONCAT: CONflict Driven Learning in ATPG for Industrial designs.	ITC	2008	DBLP DOI BibTeX RDF
17	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Novel ATPG Method for Capture Power Reduction during Scan Testing.	IEICE Trans. Inf. Syst.	2007	DBLP DOI BibTeX RDF
17	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	High-Quality Transition Fault ATPG for Small Delay Defects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
17	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A New ATPG Technique (ExpoTan) for Testing Analog Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
17	Daniel Tille, Görschwin Fey, Rolf Drechsler	Instance Generation for SAT-based ATPG.	DDECS	2007	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel	Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.	MEMOCODE	2007	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Rolf Drechsler	Improving Test Pattern Compactness in SAT-based ATPG.	ATS	2007	DBLP DOI BibTeX RDF
17	Brion L. Keller, Tom Jackson, Anis Uzzaman	A Review of Power Strategies for DFT and ATPG.	ATS	2007	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel	Experimental Studies on SAT-Based ATPG for Gate Delay Faults.	ISMVL	2007	DBLP DOI BibTeX RDF
17	Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler	SAT-based ATPG for Path Delay Faults in Sequential Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Shun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou	An efficient SAT-based path delay fault ATPG with an unified sensitization model.	ITC	2007	DBLP DOI BibTeX RDF
17	Kunal P. Ganeshpure, Sandip Kundu	On ATPG for multiple aggressor crosstalk faults in presence of gate delays.	ITC	2007	DBLP DOI BibTeX RDF
17	Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke	Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects.	ITC	2007	DBLP DOI BibTeX RDF
17	Qingwei Wu, Michael S. Hsiao	State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Liming Gao, Christian Burmer, Frank Siegelin	ATPG scan logic failure analysis: a case study of logic ICs - fault isolation, defect mechanism identification and yield improvement.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
17	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	ATPG for Dynamic Burn-In Test in Full-Scan Circuits.	ATS	2006	DBLP DOI BibTeX RDF
17	Xijiang Lin, Kun-Han Tsai, Chen Wang 0014, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.	ATS	2006	DBLP DOI BibTeX RDF
17	Masayoshi Yoshimura, Yusuke Matsunaga	Development of practical ATPG tool with flexible interface.	ATS	2006	DBLP DOI BibTeX RDF
17	Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker 0001	A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency.	ATS	2006	DBLP DOI BibTeX RDF