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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 94 occurrences of 69 keywords
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Results
Found 699 publication records. Showing 699 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Habib ul Hasan Khan, Ahmed Kamal, Diana Goehringer |
An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Emmanuel Ofori-Attah, Xiaohang Wang 0001, Michael Opoku Agyeman |
A Survey of Low Power Design Techniques for Last Level Caches. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Rafael Fão de Moura, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, Mateus Beck Rutzig |
Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Santhi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy 0001 |
ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Luca Sterpone, Ludovica Bozzoli |
Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Lampros Pyrgas, Paris Kitsos |
A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Konstantinos Georgopoulos, Pavlos Malakonakis, Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos 0001, Apostolos Dollas, Dionysios N. Pnevmatikatos, Ioannis Papaefstathiou |
Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Julián Caba, João M. P. Cardoso, Fernando Rincón, Julio Dondo, Juan Carlos López 0001 |
Rapid Prototyping and Verification of Hardware Modules Generated Using HLS. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Zhenhua Guo 0003, Baoyu Fan, Yaqian Zhao, Xuelei Li, Shixin Wei, Long Li 0006 |
An OpenCLTM Implementation of WebP Accelerator on FPGAs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
1 | Muhammad Adeel Pasha, Umer Farooq 0001, Muhammad Ali, Bilal Siddiqui |
A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Sensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang |
Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Paul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk |
dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Geraldo F. Oliveira, Paulo C. Santos 0001, Marco A. Z. Alves, Luigi Carro |
NIM: An HMC-Based Machine for Neuron Computation. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Osvaldo Navarro, Jones Yudi Mori, Javier Hoffmann, Fabian Stuckmann, Michael Hübner 0001 |
A Machine Learning Methodology for Cache Recommendation. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Ngoc-Hung Nguyen, Sheraz Ali Khan, Cheol Hong Kim, Jong-Myon Kim |
An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu 0011 |
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Ádria Barros de Oliveira, Lucas Antunes Tambara, Fernanda Lima Kastensmidt |
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Enrico Petraglio, Rick Wertenbroek, Flavio Capitao, Nicolas Guex, Christian Iseli, Yann Thoma |
Genomic Data Clustering on FPGAs for Compression. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Théotime Bollengier, Loïc Lagadec, Mohamad Najem, Jean-Christophe Le Lann, Pierre Guilloux |
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker 0001 |
Parameter Sensitivity in Virtual FPGA Architectures. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Göbel 0001, Ahmed Elhossini, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink |
A Quantitative Analysis of the Memory Architecture of FPGA-SoCs. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Mustapha Bouhali, Farid Shamani, Zine Elabadine Dahmane, Abdelkader Belaidi, Jari Nurmi |
FPGA Applications in Unmanned Aerial Vehicles - A Review. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Dimple Sharma, Victor Dumitriu, Lev Kirischian |
Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Álvaro Avelino, Valentin Obac Roda, Naim Harb, Carlos Valderrama 0001, Glauberto Albuquerque, Paulo Da Cunha Possa |
LP-P2IP: A Low-Power Version of P1IP Architecture Using Partial Reconfiguration. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Stephan Wong, Antonio Carlos Schneider Beck, Koen Bertels, Luigi Carro (eds.) |
Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser |
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Andreas Fiessler, Daniel Loebenberger, Sven Hager, Björn Scheuermann 0001 |
On the Use of (Non-)Cryptographic Hashes on FPGAs. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Abdul Rafay Khatri, Ali Hayek, Josef Börcsök |
Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Joost Hoozemans, Rolf Heij, Jeroen van Straten, Zaid Al-Ars |
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Mostafa Morshedi, Hamid Noori |
FPGA Implementation of a Short Read Mapping Accelerator. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Habib ul Hasan Khan, Diana Göhringer |
FPGA Debugging with MATLAB Using a Rule-Based Inference System. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Nils Voss, Tobias Becker, Oskar Mencer, Georgi Gaydadjiev |
Rapid Development of Gzip with MaxJ. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Andreea-Ingrid Funie, Liucheng Guo, Xinyu Niu, Wayne Luk, Mark Salmon |
Custom Framework for Run-Time Trading Strategies. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura |
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Jan Macheta, Agnieszka Dabrowska-Boruch, Pawel Russek, Kazimierz Wiatr |
ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Ruochun Jin, Jingfei Jiang, Yong Dou |
Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | André Flores dos Santos, Lucas Antunes Tambara, Fabio Benevenuti, Jorge L. Tonfat, Fernanda Lima Kastensmidt |
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Bobda, Joshua Mead, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat |
Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip. |
ARC |
2017 |
DBLP DOI BibTeX RDF |
|
1 | Mahnaz Mohammadi, Rohit Ronge, Sanjay S. Singapuram, S. K. Nandy 0001 |
Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker 0001 |
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Leonardo P. Santos, Gabriel L. Nazar, Luigi Carro |
Low Cost Dynamic Scrubbing for Real-Time Systems. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Stephanie Friederich, Niclas Lehmann, Jürgen Becker 0001 |
Adaptive Bandwidth Router for 3D Network-on-Chips. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jeckson Dellagostin Souza, João Victor Gomes Cachola, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck |
Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano |
Zynq Cluster for CFD Parametric Survey. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Evangelinos P. Mariatos, Christos P. Antonopoulos, Nikolaos S. Voros |
EEG Feature Extraction Accelerator Enabling Long Term Epilepsy Monitoring Based on Ultra Low Power WSNs. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Markus Weinhardt |
Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira |
Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | José L. Núñez-Yáñez |
Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger F. Woods, Karen Rafferty |
FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yudai Shirakura, Taisei Segawa, Yuichiro Shibata, Kenichi Morimoto, Masaharu Tanaka, Masanori Nobe, Hidenori Maruta, Fujio Kurokawa |
A Redundant Design Approach with Diversity of FPGA Resource Mapping. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Masahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri |
A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Marlon Wijeyasinghe, David Thomas 0001 |
A Multi-codec Framework to Enhance Data Channels in FPGA Streaming Systems. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jones Yudi Mori, Frederik Kautz, Michael Hübner 0001 |
Efficient Camera Input System and Memory Partition for a Vision Soft-Processor. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | James J. Davis 0001, Peter Y. K. Cheung |
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Karim M. Abdellatif, Christian Cornesse, Jacques J. A. Fournier, Bruno Robisson |
New Partitioning Approach for Hardware Trojan Detection Using Side-Channel Measurements. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Tomasz Kryjak, Marek Gorgon, Mateusz Komorkiewicz |
An Efficient Hardware Architecture for Block Based Image Processing Algorithms. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip H. W. Leong, Yu Peng |
A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shreyas G. Singapura, Yi-Hua E. Yang, Anand V. Panangadan, Tamás Németh, Peter Ng, Viktor K. Prasanna |
FPGA-Based Acceleration of Pattern Matching in YARA. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Christoforos Kachris, Dimitrios Soudris, Georgi Gaydadjiev, Huy-Nam Nguyen, Dimitrios S. Nikolopoulos, Angelos Bilas, Neil Morgan, Christos Strydis, Christos Tsalidis, John Balafas, Ricardo Jiménez-Peris, Alexandre Almeida |
The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Abiel Aguilar-González, Miguel O. Arias-Estrada |
An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bruno da Silva 0001, Jan Lemeire, An Braeken, Abdellah Touhafi |
A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Falco K. Bapp, Oliver Sander, Timo Sandmann, Hannes Stoll, Jürgen Becker 0001 |
Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jones Yudi Mori, André Werner 0001, Arij Shallufa, Florian Fricke, Michael Hübner 0001 |
A Design Methodology for the Next Generation Real-Time Vision Processors. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Konrad Häublein, Christian Hartmann 0003, Marc Reichenbach, Dietmar Fey |
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jorge L. Tonfat, Lucas A. Tambara, André Flores dos Santos, Fernanda Gusmão de Lima Kastensmidt |
Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Tahghighi, Sharad Sinha, Wei Zhang 0012 |
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Arthur Spierer, Andres Upegui |
Real-Time Audio Group Delay Correction with FFT Convolution on FPGA. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bilal Habib, Kris Gaj |
A Comprehensive Set of Schemes for PUF Response Generation. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Vanderlei Bonato, Christos Bouganis, Marek Gorgon (eds.) |
Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Vitor Coimbra, Marcus Vinicius Lamar |
Design and Optimization of Digital Circuits by Artificial Evolution Using Hybrid Multi Chromosome Cartesian Genetic Programming. |
ARC |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos |
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ioannis Papaefstathiou, Gregory Chrysos, Lambros Sarakis |
COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ren Chen, Viktor K. Prasanna |
DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink |
An Efficient and Flexible FPGA Implementation of a Face Detection System. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel |
Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | João Carlos Resende, Ricardo Chaves |
Dual CLEFIA/AES Cipher Core on FPGA. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios N. Pnevmatikatos |
Hardware Task Scheduling for Partially Reconfigurable FPGAs. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara |
Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zoltán Endre Rákossy, Dominik Stengele, Axel Acosta-Aponte, Saumitra Chafekar, Paolo Bientinesi, Anupam Chattopadhyay |
Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Thiago Baldissera Biazus, Mateus Beck Rutzig |
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Paulo Matias, Rafael Tuma Guariento, Lírio Onofre Baptista de Almeida, Jan Frans Willem Slaets |
Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shimpei Sato, Kenji Kise |
ArchHDL: A Novel Hardware RTL Design Environment in C++. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Fynn Schwiegelshohn, Eugen Ossovski, Michael Hübner 0001 |
A Fully Parallel Particle Filter Architecture for FPGAs. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas |
Hierarchical Dynamic Power-Gating in FPGAs. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Hiroki Nakahara, Hideki Yoshida, Shin-ich Shioya, Renji Mikami, Tsutomu Sasao |
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul |
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Jens Rettkowski, Philipp Wehner, Marc Schülper, Diana Göhringer |
A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tobias Wiersema, Sen Wu 0005, Marco Platzner |
On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Takuma Usui, Ryohei Kobayashi, Kenji Kise |
A Challenge of Portable and High-Speed FPGA Accelerator. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shreyas G. Singapura, Anand V. Panangadan, Viktor K. Prasanna |
Towards Performance Modeling of 3D Memory Integrated FPGA Architectures. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid |
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zaid Al-Khatib, Samar Abdi |
Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Luca Sterpone, Boyang Du |
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Salma Hesham, Jens Rettkowski, Diana Göhringer, Mohamed A. Abd El Ghany |
Survey on Real-Time Network-on-Chip Architectures. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shinya Takamaeda-Yamazaki |
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner 0001, Diana Göhringer, Maria Dagioglou, Theodoros Giannakopoulos, Stasinos Konstantopoulos, Vangelis Karkaletsis |
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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1 | Ian Graves, Adam M. Procter, William L. Harrison, Michela Becchi, Gerard Allwein |
Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tobias Strauch |
The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yaman Umuroglu, Magnus Jahre |
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Pavlos Giakoumakis, Grigorios Chrysos 0001, Apostolos Dollas, Ioannis Papaefstathiou |
Acceleration of Data Streaming Classification using Reconfigurable Technology. |
ARC |
2015 |
DBLP DOI BibTeX RDF |
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