Search results for "ASAP"

Hits ?▲	Authors	Title	Venue	Year	Link
34	Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk	F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition.	ASAP	2019	DBLP DOI BibTeX RDF
34	Sean Murray, Will Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin	A Programmable Architecture for Robot Motion Planning Acceleration.	ASAP	2019	DBLP DOI BibTeX RDF
34	Jian Fang 0004, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee	Refine and Recycle: A Method to Increase Decompression Parallelism.	ASAP	2019	DBLP DOI BibTeX RDF
34	Byeong Kil Lee, Jordan Pattee	Implications for Hardware Acceleration of Malware Detection.	ASAP	2019	DBLP DOI BibTeX RDF
34	Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku	MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture.	ASAP	2019	DBLP DOI BibTeX RDF
34	Yuancheng Li, Jiaqi Shi	CRbS: A Code Reordering Based Speeding-up Method of Irregular Loops on CMP.	ASAP	2019	DBLP DOI BibTeX RDF
34	Dilshan Kumarathunga, Omega Gamage, Asitha Samarasinghe, Nipuna Saranga, Ranga Rodrigo, Ajith A. Pasqual	VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing.	ASAP	2019	DBLP DOI BibTeX RDF
34	Jacqueline Lagasse, Christopher Bartoli, Wayne P. Burleson	Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis.	ASAP	2019	DBLP DOI BibTeX RDF
34	Oliver Jakob Arndt, Matthias Lüders, Holger Blume	Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics.	ASAP	2019	DBLP DOI BibTeX RDF
34	Chen Yang 0010, Tong Geng, Tianqi Wang, Charles Lin, Jiayi Sheng, Vipin Sachdeva, Woody Sherman, Martin C. Herbordt	Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs.	ASAP	2019	DBLP DOI BibTeX RDF
34	Nicolas Brunie, Christoph Quirin Lauter, Guillaume Revy	Precision Adaptation for Fast and Accurate Polynomial Evaluation Generation.	ASAP	2019	DBLP DOI BibTeX RDF
34	Dionysios Diamantopoulos, Christoph Hagleitner	HelmGemm: Managing GPUs and FPGAs for Transprecision GEMM Workloads in Containerized Environments.	ASAP	2019	DBLP DOI BibTeX RDF
34		29th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2018, Milano, Italy, July 10-12, 2018	ASAP	2018	DBLP BibTeX RDF
34	Jose Raul Garcia Ordaz, Dirk Koch	A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine.	ASAP	2018	DBLP DOI BibTeX RDF
34	Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild	BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates.	ASAP	2018	DBLP DOI BibTeX RDF
34	Bin Zou, Yantao Li 0001	Touch-based Smartphone Authentication Using Import Vector Domain Description.	ASAP	2018	DBLP DOI BibTeX RDF
34	Ahmet Erdem, Cristina Silvano, Thomas Boesch, Andrea C. Ornstein, Surinder Pal Singh, Giuseppe Desoli	Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC.	ASAP	2018	DBLP DOI BibTeX RDF
34	Julie Dumas, Eric Guthmuller, Frédéric Pétrot	Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach.	ASAP	2018	DBLP DOI BibTeX RDF
34	Julian Sarcher, Christian Scheglmann, Alexander Zoellner, Tim Dolereit, Michael Schaeferling, Matthias Vahl, Gundolf Kiefer	A Configurable Framework for Hough-Transform-Based Embedded Object Recognition Systems.	ASAP	2018	DBLP DOI BibTeX RDF
34	Nasrin Akbari, Mehdi Modarressi, Masoud Daneshtalab, Mohammad Loni	A Customized Processing-in-Memory Architecture for Biological Sequence Alignment.	ASAP	2018	DBLP DOI BibTeX RDF
34	Maxime France-Pillois, Jérôme Martin, Frédéric Rousseau 0001	Linux synchronization barrier on MPSoC: Hardware/software accurate study and optimization.	ASAP	2018	DBLP DOI BibTeX RDF
34	Kaoru Saso, Yuko Hara-Azumi	Simple Instruction-Set Computer for Area and Energy-Sensitive IoT Edge Devices.	ASAP	2018	DBLP DOI BibTeX RDF
34	Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Marco D. Santambrogio	Five-point algorithm: An efficient cloud-based FPGA implementation.	ASAP	2018	DBLP DOI BibTeX RDF
34	Qiong Chang, Tsutomu Maruyama	Real-Time High-Quality Stereo Matching System on a GPU.	ASAP	2018	DBLP DOI BibTeX RDF
34	Tuan D. Nguyen, Son Bui, James E. Stine	Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication.	ASAP	2018	DBLP DOI BibTeX RDF
34	Xiebing Wang, Christopher Kiwus, Canhao Wu, Biao Hu 0001, Kai Huang 0001, Alois C. Knoll	Implementing and Parallelizing Real-time Lane Detection on Heterogeneous Platforms.	ASAP	2018	DBLP DOI BibTeX RDF
34	Zulun Zhu, Shaowu Yang, Huadong Dai	Enhanced Visual Loop Closing for Laser-Based SLAM.	ASAP	2018	DBLP DOI BibTeX RDF
34	Mitali Sinha, Sri Harsha Gade, Wazir Singh, Sujay Deb	Data-flow Aware CNN Accelerator with Hybrid Wireless Interconnection.	ASAP	2018	DBLP DOI BibTeX RDF
34	Huiren Li, Anand Ramachandran 0001, Deming Chen	GPU Acceleration of Advanced k-mer Counting for Computational Genomics.	ASAP	2018	DBLP DOI BibTeX RDF
34	Yi-Lun Liao, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu	Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator.	ASAP	2018	DBLP DOI BibTeX RDF
34	Hesam Zolfaghari, Davide Rossi, Jari Nurmi	An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks.	ASAP	2018	DBLP DOI BibTeX RDF
34	Ayesha Afzal, Christian Schmitt 0003, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig	Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study.	ASAP	2018	DBLP DOI BibTeX RDF
34	Francis P. Russell, James Stanley Targett, Wayne Luk	From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations.	ASAP	2018	DBLP DOI BibTeX RDF
34	Daniel Klimeck, Hanno Gerd Meyer, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001	Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications.	ASAP	2018	DBLP DOI BibTeX RDF
34	Zelin Rong, Peidai Xie, Jingyuan Wang, Shenglin Xu, Yongjun Wang	Clean the Scratch Registers: A Way to Mitigate Return-Oriented Programming Attacks.	ASAP	2018	DBLP DOI BibTeX RDF
34	Emanuele Del Sozzo, Riyadh Baghdadi, Saman P. Amarasinghe, Marco D. Santambrogio	A Unified Backend for Targeting FPGAs from DSLs.	ASAP	2018	DBLP DOI BibTeX RDF
34	Yang Yue, Ying Li 0012, Kexin Yi, Zhonghai Wu	Synthetic Data Approach for Classification and Regression.	ASAP	2018	DBLP DOI BibTeX RDF
34	Achim Lösch, Marco Platzner	A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes.	ASAP	2018	DBLP DOI BibTeX RDF
34	Linlong Xiao, Nanzhi Wang, Guocai Yang	A Reading Comprehension Style Question Answering Model Based On Attention Mechanism.	ASAP	2018	DBLP DOI BibTeX RDF
34	Juan Carlos Salinas-Hilburg, Marina Zapater, José Manuel Moya, José Luis Ayala	Fast Energy Estimation Through Partial Execution of HPC Applications.	ASAP	2018	DBLP DOI BibTeX RDF
34	Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau 0001, Alexander Warren, Ben Jeppesen	Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control.	ASAP	2018	DBLP DOI BibTeX RDF
34	Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich	Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.	ASAP	2018	DBLP DOI BibTeX RDF
34	Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis 0001, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Hardware Compilation of Deep Neural Networks: An Overview.	ASAP	2018	DBLP DOI BibTeX RDF
34	Dimitris Theodoropoulos, Andrea Reale, Dimitris Syrivelis, Maciej Bielski, Nikolaos Alachiotis 0001, Dionisios N. Pnevmatikatos	REMAP: Remote mEmory Manager for disAggregated Platforms.	ASAP	2018	DBLP DOI BibTeX RDF
34	Daolu Zha, Xi Jin 0002, Rui Shang, Pengfei Yang	A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions.	ASAP	2018	DBLP DOI BibTeX RDF
34	Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Donatella Sciuto, Marco D. Santambrogio	A Scalable FPGA Design for Cloud N-Body Simulation.	ASAP	2018	DBLP DOI BibTeX RDF
34	Hosein Mohammadi Makrani, Hossein Sayadi, Sai Manoj P. D., Setareh Rafatirad, Houman Homayoun	Compressive Sensing on Storage Data: An Effective Solution to Alleviate I/0 Bottleneck in Data- Intensive Workloads.	ASAP	2018	DBLP DOI BibTeX RDF
34	Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual	Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks.	ASAP	2018	DBLP DOI BibTeX RDF
34	Antonio De Vita, Gian Domenico Licciardo, Luigi Di Benedetto, Danilo Pau, Emanuele Plebani, Angelo Bosco	Low-power Design of a Gravity Rotation Module for HAR Systems Based on Inertial Sensors.	ASAP	2018	DBLP DOI BibTeX RDF
34	Hugues de Lassus Saint-Genies, Nicolas Brunie, Guillaume Revy	Meta-implementation of vectorized logarithm function in binary floating-point arithmetic.	ASAP	2018	DBLP DOI BibTeX RDF
34	Antoniette Mondigo, Kentaro Sano, Hiroyuki Takizawa	Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem.	ASAP	2018	DBLP DOI BibTeX RDF
34	Davide Sampietro, Chiara Crippa, Lorenzo Di Tucci, Emanuele Del Sozzo, Marco D. Santambrogio	FPGA-based PairHMM Forward Algorithm for DNA Variant Calling.	ASAP	2018	DBLP DOI BibTeX RDF
34	Eric Flamand, Davide Rossi, Francesco Conti 0001, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini	GAP-8: A RISC-V SoC for AI at the Edge of the IoT.	ASAP	2018	DBLP DOI BibTeX RDF
34	George Plastiras, Maria Terzi, Christos Kyrkou, Theocharis Theocharides	Edge Intelligence: Challenges and Opportunities of Near-Sensor Machine Learning Applications.	ASAP	2018	DBLP DOI BibTeX RDF
34		28th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2017, Seattle, WA, USA, July 10-12, 2017	ASAP	2017	DBLP BibTeX RDF
34	Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual	High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.	ASAP	2017	DBLP DOI BibTeX RDF
34	Jing Chen, Xue Liu	A fast and accurate logarithm accelerator for scientific applications.	ASAP	2017	DBLP DOI BibTeX RDF
34	Lukas Sommer, Jens Korinth, Andreas Koch 0001	OpenMP device offloading to FPGA accelerators.	ASAP	2017	DBLP DOI BibTeX RDF
34	Wei Zhou 0013, Dan Feng 0001, Zhipeng Tan	CFStore: Boosting Hybrid storage performance by device crossfire.	ASAP	2017	DBLP DOI BibTeX RDF
34	S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson	CGRA-ME: A unified framework for CGRA modelling and exploration.	ASAP	2017	DBLP DOI BibTeX RDF
34	S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong	High-Level Synthesis for side-channel defense.	ASAP	2017	DBLP DOI BibTeX RDF
34	Julien Hascoet, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin	Hierarchical Dataflow Model for efficient programming of clustered manycore processors.	ASAP	2017	DBLP DOI BibTeX RDF
34	Ken Eguro, Ryan Kastner	A message from the general chair and program chair.	ASAP	2017	DBLP DOI BibTeX RDF
34	Stefan Tabel, Korbinian Weikl, Walter Stechele	Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter.	ASAP	2017	DBLP DOI BibTeX RDF
34	Binyang Li, Bo Li 0098, Depei Qian	PFSI.sw: A programming framework for sea ice model algorithms based on Sunway many-core processor.	ASAP	2017	DBLP DOI BibTeX RDF
34	Hongbing Tan, Haiyan Chen, Sheng Liu 0001, Jianguo Wu	Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures.	ASAP	2017	DBLP DOI BibTeX RDF
34	Yuanfang Li, Ardavan Pedram	CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks.	ASAP	2017	DBLP DOI BibTeX RDF
34	Arman Pouraghily, Tilman Wolf, Russell Tessier	Hardware support for embedded operating system security.	ASAP	2017	DBLP DOI BibTeX RDF
34	Vinh Dang, Kevin Skadron	Acceleration of Frequent Itemset Mining on FPGA using SDAccel and Vivado HLS.	ASAP	2017	DBLP DOI BibTeX RDF
34	Jehandad Khan, Peter Athanas, Skip Booth, John Marshall	OpenCL-based design pattern for line rate packet processing.	ASAP	2017	DBLP DOI BibTeX RDF
34	M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich	Hardware design and analysis of efficient loop coarsening and border handling for image processing.	ASAP	2017	DBLP DOI BibTeX RDF
34	Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran	DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks.	ASAP	2017	DBLP DOI BibTeX RDF
34	Jie Lin, Qingbo Wu 0003, Yusong Tan, Jie Yu 0008, Qi Zhang 0028, Xiaoling Li 0002, Lei Luo 0002	MicRun: A framework for scale-free graph algorithms on SIMD architecture of the Xeon Phi.	ASAP	2017	DBLP DOI BibTeX RDF
34	Chun-Jen Tsai, Cheng-Ju Lin, Cheng-Yang Chen, Yan-Hung Lin, Wei-Jhong Ji, Sheng-Di Hong	Hardwiring the OS kernel into a Java application processor.	ASAP	2017	DBLP DOI BibTeX RDF
34	Mahdi Nazemi, Shahin Nazarian, Massoud Pedram	High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis.	ASAP	2017	DBLP DOI BibTeX RDF
34	Bikash Poudel, Naresh Kumar Giri, Arslan Munir	Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS.	ASAP	2017	DBLP DOI BibTeX RDF
34	Juan Li, Zhengguo Chen, Zhiguang Chen, Nong Xiao, Fang Liu 0002	KV-FTL: A novel key-value based FTL scheme for large scale SSDs.	ASAP	2017	DBLP DOI BibTeX RDF
34	Yuanhong Huo, Dake Liu	High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms.	ASAP	2017	DBLP DOI BibTeX RDF
34	Lin Li 0029, Adrian E. Sapio, Jiahao Wu 0001, Yanzhou Liu 0001, Kyunghun Lee, Marilyn Wolf, Shuvra S. Bhattacharyya	Design and implementation of adaptive signal processing systems using Markov decision processes.	ASAP	2017	DBLP DOI BibTeX RDF
34	Yili Gong, Jia Tang, Wenhai Li, Zihui Ye	Massive spatial query on the Kepler architecture.	ASAP	2017	DBLP DOI BibTeX RDF
34	Yangguo Liu, Junlin Lu, Dong Tong 0001, Xu Cheng 0001	A Staged Memory Resource Management Method for CMP systems.	ASAP	2017	DBLP DOI BibTeX RDF
34	Abhinav Podili, Chi Zhang 0022, Viktor K. Prasanna	Fast and efficient implementation of Convolutional Neural Networks on FPGA.	ASAP	2017	DBLP DOI BibTeX RDF
34	Yanpeng Wang, Mei Wen, Chunyuan Zhang, Jie Lin	RVNet: A fast and high energy efficiency network packet processing system on RISC-V.	ASAP	2017	DBLP DOI BibTeX RDF
34	Haoyu Liu, Huahu Xu, Honghao Gao, Danqi Chu	Model checking cloud rendering system for the QoS evaluation.	ASAP	2017	DBLP DOI BibTeX RDF
34	Aravind Vasudevan, Andrew Anderson 0001, David Gregg	Parallel Multi Channel convolution using General Matrix Multiplication.	ASAP	2017	DBLP DOI BibTeX RDF
34	Achim Lösch, Marco Platzner	reMinMin: A novel static energy-centric list scheduling approach based on real measurements.	ASAP	2017	DBLP DOI BibTeX RDF
34	Joe Edwards, Guy G. F. Lemieux	Real-time object detection in software with custom vector instructions and algorithm changes.	ASAP	2017	DBLP DOI BibTeX RDF
34	Pei Zhang 0009, Joseph Zambreno, Phillip H. Jones	An embedded scalable linear model predictive hardware-based controller using ADMM.	ASAP	2017	DBLP DOI BibTeX RDF
34	S. Navid Shahrouzi, Darshika G. Perera	An efficient embedded multi-ported memory architecture for next-generation FPGAs.	ASAP	2017	DBLP DOI BibTeX RDF
34	Ruizhe Zhao, Tim Todman, Wayne Luk, Xinyu Niu	DeepPump: Multi-pumping deep Neural Networks.	ASAP	2017	DBLP DOI BibTeX RDF
34	Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich	Efficiency in ILP processing by using orthogonality.	ASAP	2017	DBLP DOI BibTeX RDF
34		27th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2016, London, United Kingdom, July 6-8, 2016	ASAP	2016	DBLP BibTeX RDF
34	Roberto R. Osorio	Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model.	ASAP	2016	DBLP DOI BibTeX RDF
34	Hend Affes, Amal Ben Ameur, Michel Auguin, François Verdier, Calypso Barnes	An ESL framework for low power architecture design space exploration.	ASAP	2016	DBLP DOI BibTeX RDF
34	Lois Orosa 0001, Rodolfo Azevedo	Temporal frequent value locality.	ASAP	2016	DBLP DOI BibTeX RDF
34	Polydoros Petrakis, Mohammed Abuteir, Miltos D. Grammatikakis, Kyprianos Papadimitriou, Roman Obermaisser, Zaher Owda, Antonis Papagrigoriou, Michael Soulie, Marcello Coppola	On-chip networks for mixed-criticality systems.	ASAP	2016	DBLP DOI BibTeX RDF
34	Antonyus P. A. Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusébio de Lima, Victor Wanderley Costa de Medeiros	A hardware accelerator for the alignment of multiple DNA sequences in forensic identification.	ASAP	2016	DBLP DOI BibTeX RDF
34	Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang	F-CNN: An FPGA-based framework for training Convolutional Neural Networks.	ASAP	2016	DBLP DOI BibTeX RDF
34	Ahmed S. Eissa, Mahmoud A. Elmohr, Mostafa A. Saleh, Khaled E. Ahmed, Mohammed M. Farag	SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture.	ASAP	2016	DBLP DOI BibTeX RDF
34	Konstantinos Krommydas, Ruchira Sasanka, Wu-chun Feng	Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning.	ASAP	2016	DBLP DOI BibTeX RDF