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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 618 occurrences of 392 keywords
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Results
Found 665 publication records. Showing 665 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Arie Margulis, David Akselrod, Eric Rentschler, Mike Ricchetti |
Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 30(4), pp. 16-25, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Peter De Dobbelaere |
Silicon Photonics Technology Platform for integration of optical IOs with ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2013 IEEE Hot Chips 25 Symposium (HCS), Stanford University, CA, USA, August 25-27, 2013, pp. 1-18, 2013, IEEE, 978-1-4673-8881-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 625-630, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Azalia Mirhoseini, Ebrahim M. Songhori, Farinaz Koushanfar |
Idetic: A high-level synthesis approach for enabling long computations on transiently-powered ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom ![In: 2013 IEEE International Conference on Pervasive Computing and Communications, PerCom 2013, San Diego, CA, USA, March 18-22, 2013, pp. 216-224, 2013, IEEE Computer Society, 978-1-4673-4573-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Gangqiang Yang, Xinxin Fan, Mark D. Aagaard, Guang Gong |
Design space exploration of the lightweight stream cipher WG-8 for FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WESS ![In: Proceedings of the Workshop on Embedded Systems Security, WESS 2013, Montreal, Quebec, Canada, September 29 - October 4, 2013, pp. 8:1-8:10, 2013, ACM, 978-1-4503-2145-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Colin Boyd, Cas Cremers, Michèle Feltz, Kenneth G. Paterson, Bertram Poettering, Douglas Stebila |
ASICS: Authenticated Key Exchange Security Incorporating Certification Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESORICS ![In: Computer Security - ESORICS 2013 - 18th European Symposium on Research in Computer Security, Egham, UK, September 9-13, 2013. Proceedings, pp. 381-399, 2013, Springer, 978-3-642-40202-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
Towards structured ASICs using polarity-tunable Si nanowire transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, pp. 123:1-123:4, 2013, ACM, 978-1-4503-2071-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
19 | Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek |
Exploring Many-Core Design Templates for FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2012, pp. 439141:1-439141:15, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Maurizio Costagliola, Davide De Caro, Antonio Girardi, Roberto Izzi, Niccolò Rinaldi, M. Spirito, P. Spirito |
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(1), pp. 162-166, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Andreas Mauderer, Marvin Freier, Jan-Hendrik Oetjens, Wolfgang Rosenstiel |
Efficient digital design for automotive mixed-signal ASICs using simulink. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 372-377, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Vladimir Petrovic, Marko Ilic, Günter Schoof, Zoran Stamenkovic |
Design methodology for fault tolerant ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012, pp. 8-11, 2012, IEEE, 978-1-4673-1187-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | David Riddoch, Steve Pope |
FPGA augmented ASICs: The time has come. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2012 IEEE Hot Chips 24 Symposium (HCS), Cupertino, CA, USA, August 27-29, 2012, pp. 1-44, 2012, IEEE, 978-1-4673-8879-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Bojan Jovanovic, Milun Jevtic |
Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOFA ![In: Soft Computing Applications - Proceedings of the 5th International Workshop Soft Computing Applications, SOFA 2012, Szeged, Hungary, 22-14 August 2012, pp. 295-308, 2012, Springer, 978-3-642-33940-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai |
Design and analysis of via-configurable routing fabrics for structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, pp. 1479-1482, 2012, IEEE, 978-1-4577-2145-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Alejandro Cook, Dominik Ull, Melanie Elm, Hans-Joachim Wunderlich, Helmut Randoll, Stefan Dohren |
Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, pp. 214-219, 2012, IEEE Computer Society, 978-1-4673-4555-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Holger Flatt, Sebastian Schriegel, Jürgen Jasperneite, Frank Schewe |
An FPGA based approach for the enhancement of COTS switch ASICs with real-time Ethernet functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETFA ![In: Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, ETFA 2012, Krakow, Poland, September 17-21, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-4735-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
19 | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(12), pp. 2195-2208, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi |
On leakage power optimization in clock tree networks for ASICs and general-purpose processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 1(1), pp. 75-87, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Andreas Mauderer, Jan-Hendrik Oetjens, Wolfgang Rosenstiel |
System-Level Design for Automotive Mixed-Signal ASICs: An Industrial Point of View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February 21-23, 2011, pp. 229-238, 2011, OFFIS-Institut für Informatik. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
19 | Piotr Kmon, Miroslaw Zoladz, Pawel Grybos, Robert Szczygiel |
Comparision of two different architectures of multichannel readout ASICs for neurobiological experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: Proceedings of EUROCON 2011, International Conference on Computer as a Tool, 27-29 April 2011, Lisbon, Portugal, pp. 1-4, 2011, IEEE. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian |
Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011, pp. 271-275, 2011, IEEE Computer Society, 978-1-4577-1399-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Dan Alexandrescu |
A comprehensive soft error analysis methodology for SoCs/ASICs memory instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, pp. 175-176, 2011, IEEE Computer Society, 978-1-4577-1053-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin |
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, pp. 37-42, 2011, ACM, 978-1-4503-0667-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
19 | Nan Hua, Eric Norige, Sailesh Kumar, Bill Lynch |
Non-crypto Hardware Hash Functions for High Performance Networking ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Brooklyn, NY, USA, October 3-4, 2011, pp. 156-166, 2011, IEEE Computer Society, 978-1-4577-1454-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Networking ASIC, Evaluation, Hash Function |
19 | Ricardo P. Jasinski |
Jari Nurmi: Processor Design - System-on-Chip Computing for ASICs and FPGAs. Springer (2007) ISBN 978-1-4020-5529-4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 53(1), pp. 127, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin |
Power gating design for standard-cell-like structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 514-519, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge |
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy, pp. 291-297, 2010, IEEE Computer Society, 978-0-7695-4179-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su |
Via configurable three-input lookup-tables for structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 49-54, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
via-configurable, layout, look-up-table, vlsi, structured ASIC |
19 | Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen |
Clock routing for structured ASICs with via-configurable fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 777-784, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Yair Linn |
A Carrier-Independent Non-Data-Aided Real-Time SNR Estimator for M-PSK and D-MPSK Suitable for FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7), pp. 1525-1538, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Leonel Sousa |
How GPUs can outperform ASICs for fast LDPC decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 390-399, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory coalescence, parallel processing, graphics processing units, multithreading, low-density parity-check codes |
19 | Naveed A. Sherwani |
Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009, pp. 123-123, 2009, IEEE Computer Society, 978-0-7695-3839-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani |
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 473-478, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Michael E. Auer, Danilo Garbi Zutin |
A Hybrid Lab for Evaluation of Analog ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education ![In: Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education, Proceedings of the 2007 International Conference on Engineering Education, Instructional Technology, Assessment, and E-learning (EIAE 2007), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2007), Bridgeport, CT, USA, December 3-12, 2007, pp. 102-105, 2008, Springer, 978-1-4020-8738-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin |
Standard Cell Like Via-Configurable Logic Block for Structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pp. 381-386, 2008, IEEE Computer Society, 978-0-7695-3170-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan |
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 251-256, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Hariharan Sankaran |
High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2008 |
RDF |
|
19 | Pradeep R. Fernando |
Genetic Algorithm Based Design and Optimization of VLSI ASICs and Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2008 |
RDF |
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19 | Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier 0002 |
Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 47(7), pp. 1069-1073, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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19 | Ciaran J. Brennan, Shunhua Chang, Min Woo, Kiran V. Chatty, Robert Gauthier 0002 |
Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 47(7), pp. 1030-1035, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Don Bouldin, Pradeep Chimakurthy |
Experiences Teaching Physical Synthesis of FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE '07, San Diego, CA, USA, June 3-4, 2007, pp. 79-80, 2007, IEEE Computer Society, 0-7695-2849-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Peter C. Maxwell |
Principles and results of some test cost reduction methods for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, pp. 1-5, 2007, IEEE Computer Society, 1-4244-1128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
Zero Cost Test Point Insertion Technique for Structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 357-363, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Claudio Menezes, Cristina Meinhardt, Ricardo Reis 0001, Reginaldo Tavares |
A Regular Layout Approach for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 424-425, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Yair Linn |
An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 232-237, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 339-348, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Philip R. Troyk, David E. Detlefsen, Glenn A. DeMichele, Douglas A. Kerns |
NeuroTalktrade: an interface for multifunctional neural engineering ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMBC ![In: 28th International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2006, New York City, NY, USA, August 30 - September 3, 2006, Main Volume, pp. 2990-2993, 2006, IEEE, 1-4244-0032-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia |
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006, pp. 36-38, 2006, CSREA Press, 1-60132-009-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
19 | Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar |
A network-flow approach to timing-driven incremental placement for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 375-382, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Vikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor 0001, Raymond Farmer, Frank Woytowich, Bob Bassett |
Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, pp. 567-570, 2006, IEEE, 1-4244-0075-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jonathan Rose |
Invited Keynote 1: Closing the gap between FPGAs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006, 2006, IEEE, 0-7803-9728-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor 0001, Frank Woytowich |
At-Speed Structural Test For High-Performance ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-10, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | José M. de la Rosa 0001, Sara Escalera, Belén Pérez-Verdú, Fernando Medeiro, Oscar Guerra, Rocío del Río, Ángel Rodríguez-Vázquez |
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(11), pp. 2246-2264, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Atanu Chattopadhyay, Zeljko Zilic |
GALDS: a complete framework for designing multiclock ASICs and SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 641-654, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Adam Augustin, Bartosz Maj, Arno Kostka |
A structure oriented compact thermal model for multiple heat source ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 36(8), pp. 700-704, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard |
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 231-236, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high-level synthesis, memory synthesis |
19 | Ádám Monostori, Hans Holm Frühauf, Gabriella Kókai |
Quick Estimation of Resources of FPGAs and ASICs Using Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LWA ![In: Lernen, Wissensentdeckung und Adaptivität (LWA) 2005, GI Workshops, Saarbrücken, October 10th-12th, 2005, pp. 210-215, 2005, DFKI. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
19 | Chris Schuermyer, Kevin Cota, Robert Madge, Brady Benware |
Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 9, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo |
Probabilistic crosstalk delay estimation for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9), pp. 1377-1383, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Dietmar Fey, Daniel Schmidt 0003, Andreas Loos |
Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS Workshops ![In: ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany, pp. 297-304, 2004, GI, 3-88579-370-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | Stefan Höreth |
Debugging and Diagnosis in Equivalence Checking of ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, pp. 232-232, 2004, Shaker. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
19 | Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave |
High-level synthesis: an essential ingredient for designing complex ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 775-782, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Jim Brown, Reed Packer, Jagdish Prasad, Khris Kofford, Troy Dye, Bob Kirk |
Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004, pp. 427-429, 2004, IEEE, 0-7803-8495-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski |
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1285-1294, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Robert Madge, Brady Benware, W. Robert Daasch |
Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(5), pp. 46-53, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Jürgen Koehl, David E. Lackey, George W. Doerre |
IBM's 50 Million gate ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 628-634, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Leon Stok, John M. Cohn |
There is life left in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 48-50, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
design cost, ASIC, design tools |
19 | Raymond X. Nijssen, Ed P. Huijbregts |
A complete design for power methodology and flow for large ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 106-108, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya |
An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 9-11 June 2003, San Diego, CA, USA, pp. 56-63, 2003, IEEE Computer Society, 0-7695-1943-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Atanu Chattopadhyay, Zeljko Zilic |
A globally asynchronous locally dynamic system for ASICs and SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 176-181, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design |
19 | Brady Benware, Robert Madge, Cam Lu, W. Robert Daasch |
Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 39-46, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | David E. Lackey, Paul S. Zuchowski, Jürgen Koehl |
Designing mega-ASICs in nanogate technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 770-775, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
design productivity, system-on-chip, methodology, power management, signal integrity, time to market |
19 | Pasi Palojärvi, Kari Määttä, Juha Kostamovaara |
Pulsed time-of-flight laser radar module with millimeter-level accuracy using full custom receiver and TDC ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 51(5), pp. 1102-1108, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Thomas R. Bednar, Patrick H. Buffet, Randall J. Darden, Scott W. Gould, Paul S. Zuchowski |
Issues and strategies for the physical design of system-on-a-chip ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 46(6), pp. 661-674, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Burcin Aktan, Garrison W. Greenwood, Molly H. Shor |
Improving evolutionary algorithm performance on maximizing functional test coverage of ASICs using adaptation of the fitness criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the 2002 Congress on Evolutionary Computation, CEC 2002, Honolulu, HI, USA, May 12-17, 2002, pp. 1825-1829, 2002, IEEE, 0-7803-7282-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Werner Haas 0003, Stefan Gossens, Ulrich Heinkel |
Behavioural Specification for Advanced Design and Verification of ASICs (ADeVA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Tübingen, Germany, February 25-27, 2002, pp. 96-105, 2002, Shaker. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
19 | Bob Plunkett, David Chou |
Computational efficiency: adaptive computing vs. ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 819-822, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Larry Wissel, Scott Pheasant, Rory Loughran, Chris LeBlanc, Bill Klaasen |
Managing soft errors in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002, pp. 85-88, 2002, IEEE, 0-7803-7250-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee |
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 188-197, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization |
19 | Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen |
Closed-loop adaptive voltage scaling controller for standard-cell ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 103-107, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter |
19 | C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim |
Validation and Test of Network Processors and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 407-410, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Wolfgang Eberle, Veerle Derudder, Geert Vanwijnsberghe, Mario Vergara, Luc Deneire, Liesbet Van der Perre, Marc Engels, Ivo Bolsens, Hugo De Man |
80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(11), pp. 1829-1838, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine |
A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(10), pp. 1524-1537, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta |
Is marriage in the cards for programmable logic, microprocessors and ASICs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 111, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Burcin Aktan, Molly H. Shor, Garrison W. Greenwood, P. Doyle |
Maximizing functional test coverage in ASICs using evolutionary algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CEC ![In: Proceedings of the 2001 Congress on Evolutionary Computation, CEC 2001, COEX, Seoul, Korea, May 27-30, 2001, pp. 178-182, 2001, IEEE, 0-7803-6657-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm |
I/O buffer placement methodology for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 245-248, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 197-201, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen |
Panel: (When) Will FPGAs Kill ASICs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 321-322, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada |
1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(10), pp. 1396-1407, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Mehrdad Nourani, Christos A. Papachristou |
Stability-based algorithms for high-level synthesis of digital ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 431-435, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Ásgeir Th. Eiríksson |
The Formal Design of 1M-gate ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 16(1), pp. 7-22, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Yuan Xie 0001, Wayne H. Wolf |
Co-synthesis with custom ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 129-134, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Cristian Chitu |
Development of fast sampling transient recorders with custom ASICs. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2000 |
RDF |
|
19 | Badreddine Rejeb |
Real time implementation of image compression algorithms on ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2000 |
RDF |
|
19 | Miodrag Potkonjak, Wayne H. Wolf |
A methodology and algorithms for the design of hard real-time multitasking ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(4), pp. 430-459, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Shingo Kinoshita, Hiroyuki Yamashita, Toshihiko Suguri, Kouichi Nagami |
Hardware/software co-simulation focusing on functional verification of large-scale ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 30(1), pp. 43-59, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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19 | Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell |
BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 1377-1380, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Jeannie H. Panner, Thomas R. Bednar, Patrick H. Buffet, Douglas W. Kemerer, Douglas W. Stout, Paul S. Zuchowski |
The first copper ASICs: A 12M-gate technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 347-350, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Ahmed Hemani, Johnny Öberg, Abhijit K. Deb, Dan Lindqvist, Björn Fjellborg |
System Level Virtual Prototyping of DSP ASICs Using Grammar Based Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 166-171, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung |
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 766-771, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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