Search results for "ASICs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Arie Margulis, David Akselrod, Eric Rentschler, Mike Ricchetti	Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs.	IEEE Des. Test	2013	DBLP DOI BibTeX RDF
19	Peter De Dobbelaere	Silicon Photonics Technology Platform for integration of optical IOs with ASICs.	Hot Chips Symposium	2013	DBLP DOI BibTeX RDF
19	Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli	Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.	DATE	2013	DBLP DOI BibTeX RDF
19	Azalia Mirhoseini, Ebrahim M. Songhori, Farinaz Koushanfar	Idetic: A high-level synthesis approach for enabling long computations on transiently-powered ASICs.	PerCom	2013	DBLP DOI BibTeX RDF
19	Gangqiang Yang, Xinxin Fan, Mark D. Aagaard, Guang Gong	Design space exploration of the lightweight stream cipher WG-8 for FPGAs and ASICs.	WESS	2013	DBLP DOI BibTeX RDF
19	Colin Boyd, Cas Cremers, Michèle Feltz, Kenneth G. Paterson, Bertram Poettering, Douglas Stebila	ASICS: Authenticated Key Exchange Security Incorporating Certification Systems.	ESORICS	2013	DBLP DOI BibTeX RDF
19	Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli	Towards structured ASICs using polarity-tunable Si nanowire transistors.	DAC	2013	DBLP DOI BibTeX RDF
19	Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek	Exploring Many-Core Design Templates for FPGAs and ASICs.	Int. J. Reconfigurable Comput.	2012	DBLP DOI BibTeX RDF
19	Maurizio Costagliola, Davide De Caro, Antonio Girardi, Roberto Izzi, Niccolò Rinaldi, M. Spirito, P. Spirito	An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
19	Andreas Mauderer, Marvin Freier, Jan-Hendrik Oetjens, Wolfgang Rosenstiel	Efficient digital design for automotive mixed-signal ASICs using simulink.	DDECS	2012	DBLP DOI BibTeX RDF
19	Vladimir Petrovic, Marko Ilic, Günter Schoof, Zoran Stamenkovic	Design methodology for fault tolerant ASICs.	DDECS	2012	DBLP DOI BibTeX RDF
19	David Riddoch, Steve Pope	FPGA augmented ASICs: The time has come.	Hot Chips Symposium	2012	DBLP DOI BibTeX RDF
19	Bojan Jovanovic, Milun Jevtic	Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs.	SOFA	2012	DBLP DOI BibTeX RDF
19	Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai	Design and analysis of via-configurable routing fabrics for structured ASICs.	DATE	2012	DBLP DOI BibTeX RDF
19	Alejandro Cook, Dominik Ull, Melanie Elm, Hans-Joachim Wunderlich, Helmut Randoll, Stefan Dohren	Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs.	Asian Test Symposium	2012	DBLP DOI BibTeX RDF
19	Holger Flatt, Sebastian Schriegel, Jürgen Jasperneite, Frank Schewe	An FPGA based approach for the enhancement of COTS switch ASICs with real-time Ethernet functions.	ETFA	2012	DBLP DOI BibTeX RDF
19	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs).	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
19	Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi	On leakage power optimization in clock tree networks for ASICs and general-purpose processors.	Sustain. Comput. Informatics Syst.	2011	DBLP DOI BibTeX RDF
19	Andreas Mauderer, Jan-Hendrik Oetjens, Wolfgang Rosenstiel	System-Level Design for Automotive Mixed-Signal ASICs: An Industrial Point of View.	MBMV	2011	DBLP BibTeX RDF
19	Piotr Kmon, Miroslaw Zoladz, Pawel Grybos, Robert Szczygiel	Comparision of two different architectures of multichannel readout ASICs for neurobiological experiments.	EUROCON	2011	DBLP DOI BibTeX RDF
19	Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian	Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus.	ICCAD	2011	DBLP DOI BibTeX RDF
19	Dan Alexandrescu	A comprehensive soft error analysis methodology for SoCs/ASICs memory instances.	IOLTS	2011	DBLP DOI BibTeX RDF
19	Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin	Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
19	Nan Hua, Eric Norige, Sailesh Kumar, Bill Lynch	Non-crypto Hardware Hash Functions for High Performance Networking ASICs.	ANCS	2011	DBLP DOI BibTeX RDF	Networking ASIC, Evaluation, Hash Function
19	Ricardo P. Jasinski	Jari Nurmi: Processor Design - System-on-Chip Computing for ASICs and FPGAs. Springer (2007) ISBN 978-1-4020-5529-4.	Comput. J.	2010	DBLP DOI BibTeX RDF
19	Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin	Power gating design for standard-cell-like structured ASICs.	DATE	2010	DBLP DOI BibTeX RDF
19	Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge	Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.	FPL	2010	DBLP DOI BibTeX RDF
19	Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su	Via configurable three-input lookup-tables for structured ASICs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	via-configurable, layout, look-up-table, vlsi, structured ASIC
19	Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen	Clock routing for structured ASICs with via-configurable fabrics.	ISQED	2010	DBLP DOI BibTeX RDF
19	Yair Linn	A Carrier-Independent Non-Data-Aided Real-Time SNR Estimator for M-PSK and D-MPSK Suitable for FPGAs and ASICs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
19	Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Leonel Sousa	How GPUs can outperform ASICs for fast LDPC decoding.	ICS	2009	DBLP DOI BibTeX RDF	memory coalescence, parallel processing, graphics processing units, multithreading, low-density parity-check codes
19	Naveed A. Sherwani	Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs.	DFT	2009	DBLP DOI BibTeX RDF
19	V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani	Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.	VLSI Design	2009	DBLP DOI BibTeX RDF
19	Michael E. Auer, Danilo Garbi Zutin	A Hybrid Lab for Evaluation of Analog ASICs.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
19	Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin	Standard Cell Like Via-Configurable Logic Block for Structured ASICs.	ISVLSI	2008	DBLP DOI BibTeX RDF
19	Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan	RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.	ASAP	2008	DBLP DOI BibTeX RDF
19	Hariharan Sankaran	High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs.		2008	RDF
19	Pradeep R. Fernando	Genetic Algorithm Based Design and Optimization of VLSI ASICs and Reconfigurable Hardware.		2008	RDF
19	Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier 0002	Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
19	Ciaran J. Brennan, Shunhua Chang, Min Woo, Kiran V. Chatty, Robert Gauthier 0002	Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
19	Don Bouldin, Pradeep Chimakurthy	Experiences Teaching Physical Synthesis of FPGAs and ASICs.	MSE	2007	DBLP DOI BibTeX RDF
19	Peter C. Maxwell	Principles and results of some test cost reduction methods for ASICs.	ITC	2007	DBLP DOI BibTeX RDF
19	Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell	Zero Cost Test Point Insertion Technique for Structured ASICs.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Claudio Menezes, Cristina Meinhardt, Ricardo Reis 0001, Reginaldo Tavares	A Regular Layout Approach for ASICs.	ISVLSI	2006	DBLP DOI BibTeX RDF
19	Yair Linn	An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs.	SiPS	2006	DBLP DOI BibTeX RDF
19	Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell	Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs.	ATS	2006	DBLP DOI BibTeX RDF
19	Philip R. Troyk, David E. Detlefsen, Glenn A. DeMichele, Douglas A. Kerns	NeuroTalktrade: an interface for multifunctional neural engineering ASICs.	EMBC	2006	DBLP DOI BibTeX RDF
19	Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia	A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs.	CDES	2006	DBLP BibTeX RDF
19	Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar	A network-flow approach to timing-driven incremental placement for ASICs.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Vikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor 0001, Raymond Farmer, Frank Woytowich, Bob Bassett	Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs.	CICC	2006	DBLP DOI BibTeX RDF
19	Jonathan Rose	Invited Keynote 1: Closing the gap between FPGAs and ASICs.	FPT	2006	DBLP DOI BibTeX RDF
19	Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor 0001, Frank Woytowich	At-Speed Structural Test For High-Performance ASICs.	ITC	2006	DBLP DOI BibTeX RDF
19	José M. de la Rosa 0001, Sara Escalera, Belén Pérez-Verdú, Fernando Medeiro, Oscar Guerra, Rocío del Río, Ángel Rodríguez-Vázquez	A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
19	Atanu Chattopadhyay, Zeljko Zilic	GALDS: a complete framework for designing multiclock ASICs and SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Adam Augustin, Bartosz Maj, Arno Kostka	A structure oriented compact thermal model for multiple heat source ASICs.	Microelectron. J.	2005	DBLP DOI BibTeX RDF
19	Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard	SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	high-level synthesis, memory synthesis
19	Ádám Monostori, Hans Holm Frühauf, Gabriella Kókai	Quick Estimation of Resources of FPGAs and ASICs Using Neural Networks.	LWA	2005	DBLP BibTeX RDF
19	Chris Schuermyer, Kevin Cota, Robert Madge, Brady Benware	Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis.	ITC	2005	DBLP DOI BibTeX RDF
19	Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo	Probabilistic crosstalk delay estimation for ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Dietmar Fey, Daniel Schmidt 0003, Andreas Loos	Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras.	ARCS Workshops	2004	DBLP BibTeX RDF
19	Stefan Höreth	Debugging and Diagnosis in Equivalence Checking of ASICs.	MBMV	2004	DBLP BibTeX RDF
19	Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave	High-level synthesis: an essential ingredient for designing complex ASICs.	ICCAD	2004	DBLP DOI BibTeX RDF
19	Jim Brown, Reed Packer, Jagdish Prasad, Khris Kofford, Troy Dye, Bob Kirk	Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay.	CICC	2004	DBLP DOI BibTeX RDF
19	Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski	Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.	ITC	2004	DBLP DOI BibTeX RDF
19	Robert Madge, Brady Benware, W. Robert Daasch	Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
19	Jürgen Koehl, David E. Lackey, George W. Doerre	IBM's 50 Million gate ASICs.	ASP-DAC	2003	DBLP DOI BibTeX RDF
19	Leon Stok, John M. Cohn	There is life left in ASICs.	ISPD	2003	DBLP DOI BibTeX RDF	design cost, ASIC, design tools
19	Raymond X. Nijssen, Ed P. Huijbregts	A complete design for power methodology and flow for large ASICs.	ISPD	2003	DBLP DOI BibTeX RDF
19	Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya	An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
19	Atanu Chattopadhyay, Zeljko Zilic	A globally asynchronous locally dynamic system for ASICs and SoCs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design
19	Brady Benware, Robert Madge, Cam Lu, W. Robert Daasch	Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs.	VTS	2003	DBLP DOI BibTeX RDF
19	David E. Lackey, Paul S. Zuchowski, Jürgen Koehl	Designing mega-ASICs in nanogate technologies.	DAC	2003	DBLP DOI BibTeX RDF	design productivity, system-on-chip, methodology, power management, signal integrity, time to market
19	Pasi Palojärvi, Kari Määttä, Juha Kostamovaara	Pulsed time-of-flight laser radar module with millimeter-level accuracy using full custom receiver and TDC ASICs.	IEEE Trans. Instrum. Meas.	2002	DBLP DOI BibTeX RDF
19	Thomas R. Bednar, Patrick H. Buffet, Randall J. Darden, Scott W. Gould, Paul S. Zuchowski	Issues and strategies for the physical design of system-on-a-chip ASICs.	IBM J. Res. Dev.	2002	DBLP DOI BibTeX RDF
19	Burcin Aktan, Garrison W. Greenwood, Molly H. Shor	Improving evolutionary algorithm performance on maximizing functional test coverage of ASICs using adaptation of the fitness criteria.	IEEE Congress on Evolutionary Computation	2002	DBLP DOI BibTeX RDF
19	Werner Haas 0003, Stefan Gossens, Ulrich Heinkel	Behavioural Specification for Advanced Design and Verification of ASICs (ADeVA).	MBMV	2002	DBLP BibTeX RDF
19	Bob Plunkett, David Chou	Computational efficiency: adaptive computing vs. ASICs.	ICECS	2002	DBLP DOI BibTeX RDF
19	Larry Wissel, Scott Pheasant, Rory Loughran, Chris LeBlanc, Bill Klaasen	Managing soft errors in ASICs.	CICC	2002	DBLP DOI BibTeX RDF
19	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
19	Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen	Closed-loop adaptive voltage scaling controller for standard-cell ASICs.	ISLPED	2002	DBLP DOI BibTeX RDF	delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter
19	C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim	Validation and Test of Network Processors and ASICs.	VTS	2002	DBLP DOI BibTeX RDF
19	Wolfgang Eberle, Veerle Derudder, Geert Vanwijnsberghe, Mario Vergara, Luc Deneire, Liesbet Van der Perre, Marc Engels, Ivo Bolsens, Hugo De Man	80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
19	Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine	A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
19	Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta	Is marriage in the cards for programmable logic, microprocessors and ASICs?	FPGA	2001	DBLP DOI BibTeX RDF
19	Burcin Aktan, Molly H. Shor, Garrison W. Greenwood, P. Doyle	Maximizing functional test coverage in ASICs using evolutionary algorithms.	CEC	2001	DBLP DOI BibTeX RDF
19	Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm	I/O buffer placement methodology for ASICs.	ICECS	2001	DBLP DOI BibTeX RDF
19	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.	IOLTW	2001	DBLP DOI BibTeX RDF
19	Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen	Panel: (When) Will FPGAs Kill ASICs?	DAC	2001	DBLP DOI BibTeX RDF
19	Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada	1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
19	Mehrdad Nourani, Christos A. Papachristou	Stability-based algorithms for high-level synthesis of digital ASICs.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
19	Ásgeir Th. Eiríksson	The Formal Design of 1M-gate ASICs.	Formal Methods Syst. Des.	2000	DBLP DOI BibTeX RDF
19	Yuan Xie 0001, Wayne H. Wolf	Co-synthesis with custom ASICs.	ASP-DAC	2000	DBLP DOI BibTeX RDF
19	Cristian Chitu	Development of fast sampling transient recorders with custom ASICs. (PDF / PS)		2000	RDF
19	Badreddine Rejeb	Real time implementation of image compression algorithms on ASICs.		2000	RDF
19	Miodrag Potkonjak, Wayne H. Wolf	A methodology and algorithms for the design of hard real-time multitasking ASICs.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
19	Shingo Kinoshita, Hiroyuki Yamashita, Toshihiko Suguri, Kouichi Nagami	Hardware/software co-simulation focusing on functional verification of large-scale ASICs.	Syst. Comput. Jpn.	1999	DBLP DOI BibTeX RDF
19	Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell	BANDIT: embedding analog-to-digital converters on digital telecom ASICs.	ICECS	1999	DBLP DOI BibTeX RDF
19	Jeannie H. Panner, Thomas R. Bednar, Patrick H. Buffet, Douglas W. Kemerer, Douglas W. Stout, Paul S. Zuchowski	The first copper ASICs: A 12M-gate technology.	CICC	1999	DBLP DOI BibTeX RDF
19	Ahmed Hemani, Johnny Öberg, Abhijit K. Deb, Dan Lindqvist, Björn Fjellborg	System Level Virtual Prototyping of DSP ASICs Using Grammar Based Approach.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF
19	Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung	A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs.	DAC	1999	DBLP DOI BibTeX RDF