| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima |
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.  |
ATS  |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Ye 0001, Yu Hu 0001, Xiaowei Li 0001 |
Hardware Trojan in FPGA CNN Accelerator. |
ATS |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhao, Haihua Shen, Huawei Li 0001, Xiaowei Li 0001 |
Hardware Trojan Detection Based on Signal Correlation. |
ATS |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Peng Liu 0045, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai |
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. |
ATS |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Meng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu |
A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit. |
ATS |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sourav Ghosh, Hafizur Rahaman 0001, Chandan Giri |
Test Diagnosis of Digital Microfluidic Biochips Using Image Segmentation. |
ATS |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho |
Digital Rights Management for Paper-Based Microfluidic Biochips. |
ATS |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Ozawa, Takashi Ida, Richen Jiang, Shotaro Sakurai, Seiya Takigami, Nobukazu Tsukiji, Ryoji Shiota, Haruo Kobayashi 0001 |
SAR TDC Architecture with Self-Calibration Employing Trigger Circuit. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi Baradaran Tahoori, Masahiro Fujita |
Post Silicon Debugging of Electrical Bugs Using Trace Buffers. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian M. Fuchs, Todor P. Stefanov, Nadia Murillo, Aske Plaat |
Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhou, Aijiao Cui, Huawei Li 0001, Gang Qu 0001 |
How to Secure Scan Design Against Scan-Based Side-Channel Attacks? |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Amitava Majumdar 0002, Balakrishna Jayadev, Da Cheng, Albert Lin |
Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jack Tang, Mohamed Ibrahim 0002, Krishnendu Chakrabarty, Ramesh Karri |
Security Implications of Cyberphysical Flow-Based Microfluidic Biochips. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumya Mittal, R. D. (Shawn) Blanton |
PADLOC: Physically-Aware Defect Localization and Characterization. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kentaro Kato |
Deterministic Path Delay Measurement Using Short Cycle Test Pattern. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Chun Ko, Shih-Hsu Huang |
3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li |
Testing Clock Distribution Networks. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Ming Chang, Kai-Jie Yang, James Chien-Mo Li, Hung Chen |
Test Pattern Compression for Probabilistic Circuits. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora |
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Huina Chao, Huawei Li 0001, Xiaoyu Song, Tiancheng Wang, Xiaowei Li 0001 |
On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu |
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu |
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun-Han Tsai, Srinivasan Gopalakrishnan |
Test Coverage Analysis for Designs with Timing Exceptions. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | |
26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017 |
ATS |
2017 |
DBLP BibTeX RDF |
|
| 1 | Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong |
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi |
Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz |
Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh |
On Securing Scan Design from Scan-Based Side-Channel Attacks. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Surya Piplani, Humberto Fonseca, Vivek Mohan Sharma, Daniele Cervini, David Hardisty |
Test and Debug Strategy for High Speed JESD204B Rx PHY. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Songwei Pei, Alrashdi Ahmed Rabehb, Song Jin |
On-Chip Ring Oscillator Based Scheme for TSV Delay Measurement. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Aijiao Cui, Xuesen Qian, Gang Qu 0001, Huawei Li 0001 |
A New Active IC Metering Technique Based on Locking Scan Cells. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo |
Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui |
A Heuristic Algorithm for Automatic Generation of March Tests. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoichi Maeda, Jun Matsushima, Ron Press |
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Chih Chen |
Tree-Based Logic Encryption for Resisting SAT Attack. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger |
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian |
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang-Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee |
Test Compression with Single-Input Data Spreader and Multiple Test Sessions. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Huang 0005, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng |
Scan Chain Diagnosis Based on Unsupervised Machine Learning. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zih-Huan Gao, Hau Hsu, Ting-Shuo Hsu, Jing-Jia Liou |
Post-Silicon Test Flow for Aging Prediction. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong-Yu Hsieh, Tai-Ang Cheng, Chao-Ru Chen |
Error-Tolerability Evaluation and Test for Images in Face Detection Applications. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Said Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang 0001, Arijit Raychowdhury, Insik Yoon |
Test and Reliability of Emerging Non-volatile Memories. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler |
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Joyati Mondal, Debesh Kumar Das |
Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Si-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, Chien-Nan Jimmy Liu |
An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi |
Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Keitaro Koga, Hiromitsu Awano, Makoto Ikeda |
Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi |
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Huaxing Tang, Arvind Jain, Sanil Kumark Pillai, Dharmesh Joshi, Shamitha Rao |
Using Cell Aware Diagnostic Patterns to Improve Diagnosis Resolution for Cell Internal Defects. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Guan-Hao Lian, Shi-Yu Huang, Wei-yi Chen |
Cloud-Based PVT Monitoring System for IoT Devices. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dominik Ull, Michael A. Kochte, Hans-Joachim Wunderlich |
Structure-Oriented Test of Reconfigurable Scan Networks. |
ATS |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Baradaran Tahoori, Krishnendu Chakrabarty |
Test and Reliability Issues in 2.5D and 3D Integration. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume |
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehrdad Heydarzadeh, Hao Luo, Mehrdad Nourani |
Model-Free Testing of Analog Circuits. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu |
Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao Luo, Mehrdad Heydarzadeh, Mehrdad Nourani |
Aging-Leakage Tradeoffs Using Multi-Vth Cell Library. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayalaxmi Satishkumar, Nagesh Vaidya |
Achieving Acceptable Bit Error Rate for 40 Gbps Link Using Signal Conditioning Techniques. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Te-Hui Chen, David C. Keezer |
An Ultra-High-Speed Test Module and FPGA-Based Development Platform. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Takumi Uezono, Tadanobu Toba, Ken-ichi Shimbo, Fumihiko Nagasaki, Kenji Kawamura |
Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Siaw Chen Lee, Soon Ee Ong |
rosTest: Universal Test Framework for Real-Time Operating System. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Zhao, Hans G. Kerkhoff |
Highly Dependable Multi-processor SoCs Employing Lifetime Prediction Based on Health Monitors. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Lai Pheng Tan, Shen Shen Lee, Kian Hui Wong |
Design and Implementation of EMIB Testing on 2.5D FPGA Transceiver. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann |
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima |
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
On the Switching Activity in Faulty Circuits During Test Application. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki |
Critical-Area-Aware Test Pattern Generation and Reordering. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu |
Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Schneider, Hans-Joachim Wunderlich |
High-Throughput Transistor-Level Fault Simulation on GPUs. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen |
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte |
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng |
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Masayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi 0001 |
Rectangular Waveform Generation with Harmonics Suppression. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar |
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Khanh N. Dang, Michael Conrad Meyer, Yuichi Okuyama 0001, Abderazek Ben Abdallah |
Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroyuki Iwata, Jun Matsushima |
Multi-configuration Scan Structure for Various Purposes. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee |
Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Bian 0001, Michihiro Shintani, Zheng Wang 0020, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato |
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael A. Kochte, Rafal Baranowski, Marcel Schaal, Hans-Joachim Wunderlich |
Test Strategies for Reconfigurable Scan Networks. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Md. Nazmul Islam, Sandip Kundu |
Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Qingli Guo, Jing Ye 0001, Yue Gong, Yu Hu 0001, Xiaowei Li 0001 |
Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jasvir Singh, Anuj Grover, Mausumi Pohit, Anurag Singh Baghel, Gurjit Kaur, Shalini Pathak |
Scan Chain Adaptation through ECO. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsin Hu, Jacob A. Abraham |
Quality Aware Error Detection in 2-D Separable Linear Transformation. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich |
Autonomous Testing for 3D-ICs with IEEE Std. 1687. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Supriyo Srimani, Kasturi Ghosh, Hafizur Rahaman 0001 |
Parametric Fault Detection in Analog Circuits: A Statistical Approach. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang |
Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Takeshi Mizushima, Kazuki Shirahata, Tasuku Fujibe, Hidenobu Matsumura, Daisuke Watanabe, Hiroyuki Mineo, Shin Masuda |
An Optical/Electrical Test System for 100-Gb/s Optical Interconnection Devices for High Volume Production. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shengcheng Wang, Ran Wang 0002, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori |
Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Atefe Dalirsani, Hans-Joachim Wunderlich |
Functional Diagnosis for Graceful Degradation of NoC Switches. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao-Chiao Hong, Long-Yi Lin |
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthias Sauer 0002, Jie Jiang 0018, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker 0001, Ilia Polian |
On Optimal Power-Aware Path Sensitization. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ran Wang 0002, Krishnendu Chakrabarty |
Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
On Test Points Enhancing Hardware Security. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Yingxin Qiu, Huawei Li 0001, Tiancheng Wang, Bo Liu 0018, Yingke Gao, Xiaowei Li 0001 |
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shi-Yu Huang, Chih-Chieh Zheng |
Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Shi-Yu Huang |
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Parameswaran Ramanathan, Kewal K. Saluja |
Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen |
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Sying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li |
Side-Channel Attack on Flipped Scan Chains. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. |
ATS |
2016 |
DBLP DOI BibTeX RDF |
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