Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Michael Theobald, Steven M. Nowick |
An Implicit Method for Hazard-Free Two-Level Logic Minimization. |
ASYNC |
1998 |
DBLP DOI BibTeX RDF |
hazard-free, two-level, dynamic-hazard-free prime implicants, asynchronous, BDD, logic minimization, implicit |
18 | Kazuhiro Nakamura, Satoshi Yamane |
Formal Verification of Real-Time Software by Symbolic Model-Checker. |
ACSD |
1998 |
DBLP DOI BibTeX RDF |
temporal logic, approximations, BDD, symbolic model-checking, real-time software |
18 | Steve Haynal, Forrest Brewer |
Efficient encoding for exact symbolic automata-based scheduling. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, automata, BDD |
18 | Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III |
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. |
IEEE Trans. Computers |
1997 |
DBLP DOI BibTeX RDF |
average case, complexity, BDD, Decision diagrams, multiple-valued functions, symmetric functions, asymptotic approximation |
18 | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
On Decomposition of Kleene TDDs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
decomposition, TDD, BDD, logic simulation |
18 | Yirng-An Chen, Randal E. Bryant |
PHDD: an efficient graph representation for floating point circuit verification. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
KFDD, *BMD, HDD, K*BMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD |
18 | Luc Robert, Grégoire Malandain |
Fast Binary Image Processing Using Binary Decision Diagrams. |
CVPR |
1997 |
DBLP DOI BibTeX RDF |
binary image processing, mathematical morphology, BDD, digital topology |
18 | Shin-ichi Minato |
Generation of BDDs from hardware algorithm descriptions. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
LSI CAD, logic synthesis, BDD, design verification, hardware algorithm |
18 | Daniel Král |
Polynomial-Size Binary Decision Diagrams for the Exactly Half-d-Hyperclique Problem Reading Each Input Bit Twice. |
Theory Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Free binary decision diagrams, Binary decision diagrams |
18 | Wenhui Zhang |
Bounded Semantics of CTL and SAT-Based Verification. |
ICFEM |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Sathiamoorthy Subbarayan |
Efficient Reasoning for Nogoods in Constraint Solvers with BDDs. |
PADL |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Gianpiero Cabodi, Paolo Camurati, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer |
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. |
FMCAD |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Chao Wang 0001, Zijiang Yang 0006, Franjo Ivancic, Aarti Gupta |
Disjunctive image computation for software verification. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Model checking, formal verification, binary decision diagram, reachability analysis, image computation |
18 | Vaclav Dvorak |
Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software. |
ECBS |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Wassim Ayadi, Khedija Arour |
A Novel Parallel Boolean Approach for Discovering Frequent Itemsets. |
ICDM Workshops |
2007 |
DBLP DOI BibTeX RDF |
Data mining, Association rules, Binary decision diagram, Frequent itemsets, Parallel data mining |
18 | Kevin Oo Tinmaung, David Howland, Russell Tessier |
Power-aware FPGA logic synthesis using binary decision diagrams. |
FPGA |
2007 |
DBLP DOI BibTeX RDF |
FPGA, binary decision diagram, dynamic power |
18 | David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
Symbolic Model Checking of Analog/Mixed-Signal Circuits. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language |
18 | Ben Hardekopf, Calvin Lin |
The ant and the grasshopper: fast and accurate pointer analysis for millions of lines of code. |
PLDI |
2007 |
DBLP DOI BibTeX RDF |
pointer analysis |
18 | Wassim Ayadi, Khedija Arour |
A Binary Decision Diagram to discover low threshold support frequent itemsets. |
DEXA Workshops |
2007 |
DBLP DOI BibTeX RDF |
data mining, association rules, binary decision diagram, frequent item sets |
18 | Ondrej Lhoták, Stephen Curial, José Nelson Amaral |
Using ZBDDs in Points-to Analysis. |
LCPC |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Akashi Satoh |
High-Speed Parallel Hardware Architecture for Galois Counter Mode. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers |
Synthesis of irregular combinational functions with large don't care sets. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
logic synthesis, incompletely specified functions |
18 | Markus Behle |
On Threshold BDDs and the Optimal Variable Ordering Problem. |
COCOA |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich |
Symbolic Archive Representation for a Fast Nondominance Test. |
EMO |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Martin Hell, Thomas Johansson 0001 |
Two New Attacks on the Self-Shrinking Generator. |
IEEE Trans. Inf. Theory |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Ming-Hong Su, Chun-Yao Wang |
High level equivalence symmetric input identification. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Shin-ichi Minato, Hiroki Arimura |
Frequent Pattern Mining and Knowledge Indexing Based on Zero-Suppressed BDDs. |
KDID |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Koen Claessen, Jan-Willem Roorda |
An Introduction to Symbolic Trajectory Evaluation. |
SFM |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Toni Jussila, Carsten Sinz, Armin Biere |
Extended Resolution Proofs for Symbolic SAT Solving with Quantification. |
SAT |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Farn Wang |
Symbolic Verification of Distributed Real-Time Systems with Complex Synchronizations. |
ICFEM |
2005 |
DBLP DOI BibTeX RDF |
model-checking, verification, real-time, synchronization, distributed |
18 | François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat |
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
Differential Pull Down Networks, Side-channel attack, Differential Power Analysis, Binary Decision Diagrams |
18 | John Whaley, Dzintars Avots, Michael Carbin, Monica S. Lam |
Using Datalog with Binary Decision Diagrams for Program Analysis. |
APLAS |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Andrea Bobbio, Daniele Codetta Raiteri, Massimiliano De Pierro, Giuliana Franceschinis |
Efficient Analysis Algorithms for Parametric Fault Trees. |
FIRB-Perf |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P. Kurshan, Kenneth L. McMillan |
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster |
Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Gilles Audemard, Lakhdar Sais |
A Symbolic Search Based Approach for Quantified Boolean Formulas. |
SAT |
2005 |
DBLP DOI BibTeX RDF |
Satisfiability, Binary decision diagram, Quantified boolean formula |
18 | Tarik Hadzic, Henrik Reif Andersen |
Interactive Reconfiguration in Power Supply Restoration. |
CP |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson |
Multi-threaded reachability. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
parallel, multi-threaded, reachability analysis |
18 | Yong Ou, Joanne Bechta Dugan |
Modular solution of dynamic multi-phase systems. |
IEEE Trans. Reliab. |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Ofer Strichman |
Accelerating Bounded Model Checking of Safety Properties. |
Formal Methods Syst. Des. |
2004 |
DBLP DOI BibTeX RDF |
SAT, Bounded Model Checking |
18 | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang |
Safety Property Verification Using Sequential SAT and Bounded Model Checking. |
IEEE Des. Test Comput. |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Andrés Martinelli, René Krenz, Elena Dubrova |
Disjoint-support Boolean decomposition combining functional and structural methods. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Guanghui Li 0001, Xiaowei Li 0001 |
Circuit-Width Based Heuristic for Boolean Reasoning. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Fang Yu 0001, Bow-Yaw Wang |
Toward Unbounded Model Checking for Region Automata. |
ATVA |
2004 |
DBLP DOI BibTeX RDF |
Region automata, Real-time systems, Model checking, Verification, Induction, BMC |
18 | Bijan Alizadeh, Zainalabedin Navabi |
Property Checking based on Hierarchical Integer Equations. |
ACSD |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Sharon Shoham, Orna Grumberg |
Monotonic Abstraction-Refinement for CTL. |
TACAS |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Zijiang Yang 0006, Rajeev Alur |
Variable Reuse for Efficient Image Computation. |
FMCAD |
2004 |
DBLP DOI BibTeX RDF |
|
18 | In-Ho Moon, Carl Pixley |
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. |
FMCAD |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Bijan Alizadeh, Zainalabedin Navabi |
Using Integer Equations to Check PSL Properties in RT Level Design. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening |
A SAT-based algorithm for reparameterization in symbolic simulation. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
SAT checkers, safety property checking, bounded model checking, symbolic simulation, parametric representation |
18 | Rachel Tzoref, Mark Matusevich, Eli Berger, Ilan Beer |
An Optimized Symbolic Bounded Model Checking Engine. |
CHARME |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Marcelo Glusman, Gila Kamhi, Sela Mador-Haim, Ranan Fraer, Moshe Y. Vardi |
Multiple-Counterexample Guided Iterative Abstraction Refinement: An Industrial Evaluation. |
TACAS |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Dirk Beyer 0001, Andreas Noack |
Can Decision Diagrams Overcome State Space Explosion in Real-Time Verification? |
FORTE |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Kenneth L. McMillan |
Applying SAT Methods in Unbounded Symbolic Model Checking. |
CAV |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Michael J. C. Gordon |
PuzzleTool : An Example of Programming Computation and Deduction. |
TPHOLs |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Sherief Reda, Rolf Drechsler, Alex Orailoglu |
On the Relation between SAT and BDDs for Equivalence Checking. |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Rupesh S. Shelar, Sachin S. Sapatnekar |
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Low Power, Logic Synthesis, Pass Transistor Logic |
18 | Fady Copty, Limor Fix, Ranan Fraer, Enrico Giunchiglia, Gila Kamhi, Armando Tacchella, Moshe Y. Vardi |
Benefits of Bounded Model Checking at an Industrial Setting. |
CAV |
2001 |
DBLP DOI BibTeX RDF |
|
18 | John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss |
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. |
CAV |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Henrik Brosenne, Matthias Homeister, Stephan Waack |
Graph-Driven Free Parity BDDs: Algorithms and Lower Bounds. |
MFCS |
2001 |
DBLP DOI BibTeX RDF |
|
18 | S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti 0001 |
Symbolic verification of Boolean constraints over partially specified functions. |
ISCAS (5) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer |
AQUILA: An Equivalence Checking System for Large Sequential Designs. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
state exploration, formal verification, Design verification, equivalence checking |
18 | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto |
Symbolic optimization of interacting controllers based onredundancy identification and removal. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jan Friso Groote, Jaco van de Pol |
Equational Binary Decision Diagrams. |
LPAR |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jae-Young Jang, In-Ho Moon, Gary D. Hachtel |
Iterative Abstraction-Based CTL Model Checking. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jaco van de Pol, Hans Zantema |
Binary Decision Diagrams by Shard Rewriting. |
MFCS |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Farn Wang |
Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems. |
COMPSAC |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Kumar Neeraj Verma, Jean Goubault-Larrecq, Sanjiva Prasad, S. Arun-Kumar |
Reflecting BDDs in Coq. |
ASIAN |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Parosh Aziz Abdulla, Per Bjesse, Niklas Eén |
Symbolic Reachability Analysis Based on SAT-Solvers. |
TACAS |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Chris Wilson, David L. Dill, Randal E. Bryant |
Symbolic Simulation with Approximate Values. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Beate Bollig, Ingo Wegener |
Complexity Theoretical Results on Partitioned (Nondeterministic) Binary Decision Diagrams. |
Theory Comput. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Enric Pastor, Jordi Cortadella, Marco A. Peña |
Structural Methods to Improve the Symbolic Analysis of Petri Nets. |
ICATPN |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Wolfgang Günther 0001, Rolf Drechsler |
Minimization of BDDs using linear transformations based on evolutionary techniques. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | R. Glenn Wood, Rob A. Rutenbar |
FPGA routing and routability estimation via Boolean satisfiability. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Rajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani |
Symbolic Exploration of transition Hierarchies. |
TACAS |
1998 |
DBLP DOI BibTeX RDF |
|
18 | James H. Kukula, Thomas R. Shiple, Adnan Aziz |
Techniques for Implicit State Enumeration of EFSMs. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
18 | William Chan 0001, Richard J. Anderson, Paul Beame, David Notkin |
Combining Constraint Solving and Symbolic Model Checking for a Class of a Systems with Non-linear Constraints. |
CAV |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Beate Bollig, Ingo Wegener |
Complexity Theoretical Results on Partitioned (Nondeterministic) Binary Decision Diagrams. |
MFCS |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Valeria Bertacco, Maurizio Damiani |
The disjunctive decomposition of logic functions. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
disjunctive decomposition, combinational logic optimization |
18 | Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer |
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Craig Damon, Daniel Jackson 0001, Somesh Jha |
Checking Relational Specifications With Binary Decision Diagrams. |
SIGSOFT FSE |
1996 |
DBLP DOI BibTeX RDF |
Z |
18 | Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton |
Early Quantification and Partitioned Transition Relations. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Huey-Ling Chen, Chung-Ta King |
A New Model for Dynamic Processor Allocation in Multicomputer Systems. |
HICSS (1) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Ted Stanion, Debashis Bhattacharya, Carl Sechen |
An efficient method for generating exhaustive test sets. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Timothy Kam, P. A. Subrahmanyam |
Comparing layouts with HDL models: a formal verification technique. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima |
Efficient construction of binary moment diagrams for verifying arithmetic circuits. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
word-level verification, binary moment diagram, arithmetic circuit, design verification |
18 | Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton |
Improving Language Containment Using Fairness Graphs. |
CAV |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Bernard Boigelot, Pierre Wolper |
Symbolic Verification with Periodic Sets. |
CAV |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Enric Pastor, Oriol Roig, Jordi Cortadella, Rosa M. Badia |
Petri Net Analysis Using Boolean Manipulation. |
Application and Theory of Petri Nets |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Alan J. Hu, David L. Dill |
Efficient Verification with BDDs using Implicitly Conjoined Invariants. |
CAV |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Alan J. Hu, David L. Dill, Andreas J. Drexler, C. Han Yang |
Higher-Level Specification and Verification with BDDs. |
CAV |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Bernd Becker 0001 |
Synthesis for Testability: Binary Decision Diagrams. |
STACS |
1992 |
DBLP DOI BibTeX RDF |
VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures |
18 | Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima |
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Mehdi Mohammadi, Hossein Pazhoumand-dar, Mohsen Soryani, Hossein Moeinzadeh |
HS-ROBDD: an efficient variable order binary decision diagram. |
GECCO (Companion) |
2009 |
DBLP DOI BibTeX RDF |
binary decision diagram (bdd) |
17 | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
multiterminal BDD, numerical function generators, edge-valued binary decision diagrams, segment index encoder |
17 | Yi Fang 0001, Nir Piterman, Amir Pnueli, Lenore D. Zuck |
Liveness with invisible ranking. |
Int. J. Softw. Tools Technol. Transf. |
2006 |
DBLP DOI BibTeX RDF |
Parametrized systems, Deductive verification, BDD techniques, Liveness, Automatic verification |
17 | Aarti Gupta, Malay K. Ganai, Chao Wang 0001, Zijiang Yang 0006, Pranav Ashar |
Learning from BDDs in SAT-based bounded model checking. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
BDD learning, learning, SAT, BDDs, bounded model checking, boolean satisfiability, SAT solvers, property checking |
17 | Kanna Shimizu, David L. Dill |
Deriving a simulation input generator and a coverage metric from a formal specification. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
BDD minimization, input generation, coverage, testbench |
17 | Hafiz Md. Hasan Babu, Tsutomu Sasao |
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
Binary decision diagram (BDD), multiple-valued decision diagram (MDD), multi-level logic synthesis, look-up table type FPGA design, multiple-valued logic, multiple-output function |
17 | Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich |
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. |
ACM Trans. Design Autom. Electr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
FPGA technology, TOS, assignable functions, implicit BDD-based methods, mapping synthesis, multiple-output decomposition, preferable functions, subfunction sharing gain, subfunction sharing potential, variable partitioning for decomposition, Boolean functions, decomposition, computer-aided design of VLSI |