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Publication years (Num. hits)
1990-1993 (26) 1994 (23) 1995 (26) 1996 (22) 1997 (37) 1998 (39) 1999 (45) 2000 (50) 2001 (45) 2002 (47) 2003 (59) 2004 (66) 2005 (63) 2006 (61) 2007 (48) 2008 (51) 2009 (36) 2010 (17) 2011-2012 (29) 2013 (16) 2014 (19) 2015 (17) 2016 (16) 2017 (20) 2018 (16) 2019 (16) 2020-2021 (29) 2022 (16) 2023 (28) 2024 (2)
Publication types (Num. hits)
article(233) book(1) data(1) incollection(2) inproceedings(744) phdthesis(4)
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Found 985 publication records. Showing 985 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
18Michael Theobald, Steven M. Nowick An Implicit Method for Hazard-Free Two-Level Logic Minimization. Search on Bibsonomy ASYNC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF hazard-free, two-level, dynamic-hazard-free prime implicants, asynchronous, BDD, logic minimization, implicit
18Kazuhiro Nakamura, Satoshi Yamane Formal Verification of Real-Time Software by Symbolic Model-Checker. Search on Bibsonomy ACSD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF temporal logic, approximations, BDD, symbolic model-checking, real-time software
18Steve Haynal, Forrest Brewer Efficient encoding for exact symbolic automata-based scheduling. Search on Bibsonomy ICCAD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF scheduling, high-level synthesis, automata, BDD
18Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1997 DBLP  DOI  BibTeX  RDF average case, complexity, BDD, Decision diagrams, multiple-valued functions, symmetric functions, asymptotic approximation
18Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura On Decomposition of Kleene TDDs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF decomposition, TDD, BDD, logic simulation
18Yirng-An Chen, Randal E. Bryant PHDD: an efficient graph representation for floating point circuit verification. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF KFDD, *BMD, HDD, K*BMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD
18Luc Robert, Grégoire Malandain Fast Binary Image Processing Using Binary Decision Diagrams. Search on Bibsonomy CVPR The full citation details ... 1997 DBLP  DOI  BibTeX  RDF binary image processing, mathematical morphology, BDD, digital topology
18Shin-ichi Minato Generation of BDDs from hardware algorithm descriptions. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF LSI CAD, logic synthesis, BDD, design verification, hardware algorithm
18Daniel Král Polynomial-Size Binary Decision Diagrams for the Exactly Half-d-Hyperclique Problem Reading Each Input Bit Twice. Search on Bibsonomy Theory Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Free binary decision diagrams, Binary decision diagrams
18Wenhui Zhang Bounded Semantics of CTL and SAT-Based Verification. Search on Bibsonomy ICFEM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
18Sathiamoorthy Subbarayan Efficient Reasoning for Nogoods in Constraint Solvers with BDDs. Search on Bibsonomy PADL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Gianpiero Cabodi, Paolo Camurati, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. Search on Bibsonomy FMCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Chao Wang 0001, Zijiang Yang 0006, Franjo Ivancic, Aarti Gupta Disjunctive image computation for software verification. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Model checking, formal verification, binary decision diagram, reachability analysis, image computation
18Vaclav Dvorak Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software. Search on Bibsonomy ECBS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Wassim Ayadi, Khedija Arour A Novel Parallel Boolean Approach for Discovering Frequent Itemsets. Search on Bibsonomy ICDM Workshops The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Data mining, Association rules, Binary decision diagram, Frequent itemsets, Parallel data mining
18Kevin Oo Tinmaung, David Howland, Russell Tessier Power-aware FPGA logic synthesis using binary decision diagrams. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA, binary decision diagram, dynamic power
18David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda Symbolic Model Checking of Analog/Mixed-Signal Circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language
18Ben Hardekopf, Calvin Lin The ant and the grasshopper: fast and accurate pointer analysis for millions of lines of code. Search on Bibsonomy PLDI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF pointer analysis
18Wassim Ayadi, Khedija Arour A Binary Decision Diagram to discover low threshold support frequent itemsets. Search on Bibsonomy DEXA Workshops The full citation details ... 2007 DBLP  DOI  BibTeX  RDF data mining, association rules, binary decision diagram, frequent item sets
18Ondrej Lhoták, Stephen Curial, José Nelson Amaral Using ZBDDs in Points-to Analysis. Search on Bibsonomy LCPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Akashi Satoh High-Speed Parallel Hardware Architecture for Galois Counter Mode. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers Synthesis of irregular combinational functions with large don't care sets. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF logic synthesis, incompletely specified functions
18Markus Behle On Threshold BDDs and the Optimal Variable Ordering Problem. Search on Bibsonomy COCOA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich Symbolic Archive Representation for a Fast Nondominance Test. Search on Bibsonomy EMO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Martin Hell, Thomas Johansson 0001 Two New Attacks on the Self-Shrinking Generator. Search on Bibsonomy IEEE Trans. Inf. Theory The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Ming-Hong Su, Chun-Yao Wang High level equivalence symmetric input identification. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Shin-ichi Minato, Hiroki Arimura Frequent Pattern Mining and Knowledge Indexing Based on Zero-Suppressed BDDs. Search on Bibsonomy KDID The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Koen Claessen, Jan-Willem Roorda An Introduction to Symbolic Trajectory Evaluation. Search on Bibsonomy SFM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Toni Jussila, Carsten Sinz, Armin Biere Extended Resolution Proofs for Symbolic SAT Solving with Quantification. Search on Bibsonomy SAT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Farn Wang Symbolic Verification of Distributed Real-Time Systems with Complex Synchronizations. Search on Bibsonomy ICFEM The full citation details ... 2005 DBLP  DOI  BibTeX  RDF model-checking, verification, real-time, synchronization, distributed
18François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Differential Pull Down Networks, Side-channel attack, Differential Power Analysis, Binary Decision Diagrams
18John Whaley, Dzintars Avots, Michael Carbin, Monica S. Lam Using Datalog with Binary Decision Diagrams for Program Analysis. Search on Bibsonomy APLAS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Andrea Bobbio, Daniele Codetta Raiteri, Massimiliano De Pierro, Giuliana Franceschinis Efficient Analysis Algorithms for Parametric Fault Trees. Search on Bibsonomy FIRB-Perf The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P. Kurshan, Kenneth L. McMillan An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment. Search on Bibsonomy CHARME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation. Search on Bibsonomy CHARME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Gilles Audemard, Lakhdar Sais A Symbolic Search Based Approach for Quantified Boolean Formulas. Search on Bibsonomy SAT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Satisfiability, Binary decision diagram, Quantified boolean formula
18Tarik Hadzic, Henrik Reif Andersen Interactive Reconfiguration in Power Supply Restoration. Search on Bibsonomy CP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
18Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson Multi-threaded reachability. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF parallel, multi-threaded, reachability analysis
18Yong Ou, Joanne Bechta Dugan Modular solution of dynamic multi-phase systems. Search on Bibsonomy IEEE Trans. Reliab. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Ofer Strichman Accelerating Bounded Model Checking of Safety Properties. Search on Bibsonomy Formal Methods Syst. Des. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF SAT, Bounded Model Checking
18Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang Safety Property Verification Using Sequential SAT and Bounded Model Checking. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Andrés Martinelli, René Krenz, Elena Dubrova Disjoint-support Boolean decomposition combining functional and structural methods. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Guanghui Li 0001, Xiaowei Li 0001 Circuit-Width Based Heuristic for Boolean Reasoning. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Fang Yu 0001, Bow-Yaw Wang Toward Unbounded Model Checking for Region Automata. Search on Bibsonomy ATVA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Region automata, Real-time systems, Model checking, Verification, Induction, BMC
18Bijan Alizadeh, Zainalabedin Navabi Property Checking based on Hierarchical Integer Equations. Search on Bibsonomy ACSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Sharon Shoham, Orna Grumberg Monotonic Abstraction-Refinement for CTL. Search on Bibsonomy TACAS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Zijiang Yang 0006, Rajeev Alur Variable Reuse for Efficient Image Computation. Search on Bibsonomy FMCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18In-Ho Moon, Carl Pixley Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. Search on Bibsonomy FMCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Bijan Alizadeh, Zainalabedin Navabi Using Integer Equations to Check PSL Properties in RT Level Design. Search on Bibsonomy IWSOC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
18Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening A SAT-based algorithm for reparameterization in symbolic simulation. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF SAT checkers, safety property checking, bounded model checking, symbolic simulation, parametric representation
18Rachel Tzoref, Mark Matusevich, Eli Berger, Ilan Beer An Optimized Symbolic Bounded Model Checking Engine. Search on Bibsonomy CHARME The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
18Marcelo Glusman, Gila Kamhi, Sela Mador-Haim, Ranan Fraer, Moshe Y. Vardi Multiple-Counterexample Guided Iterative Abstraction Refinement: An Industrial Evaluation. Search on Bibsonomy TACAS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
18Dirk Beyer 0001, Andreas Noack Can Decision Diagrams Overcome State Space Explosion in Real-Time Verification? Search on Bibsonomy FORTE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
18Kenneth L. McMillan Applying SAT Methods in Unbounded Symbolic Model Checking. Search on Bibsonomy CAV The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
18Michael J. C. Gordon PuzzleTool : An Example of Programming Computation and Deduction. Search on Bibsonomy TPHOLs The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
18Sherief Reda, Rolf Drechsler, Alex Orailoglu On the Relation between SAT and BDDs for Equivalence Checking. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
18Rupesh S. Shelar, Sachin S. Sapatnekar An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Low Power, Logic Synthesis, Pass Transistor Logic
18Fady Copty, Limor Fix, Ranan Fraer, Enrico Giunchiglia, Gila Kamhi, Armando Tacchella, Moshe Y. Vardi Benefits of Bounded Model Checking at an Industrial Setting. Search on Bibsonomy CAV The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
18John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. Search on Bibsonomy CAV The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
18Henrik Brosenne, Matthias Homeister, Stephan Waack Graph-Driven Free Parity BDDs: Algorithms and Lower Bounds. Search on Bibsonomy MFCS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
18S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti 0001 Symbolic verification of Boolean constraints over partially specified functions. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
18Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer AQUILA: An Equivalence Checking System for Large Sequential Designs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF state exploration, formal verification, Design verification, equivalence checking
18Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto Symbolic optimization of interacting controllers based onredundancy identification and removal. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Jan Friso Groote, Jaco van de Pol Equational Binary Decision Diagrams. Search on Bibsonomy LPAR The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Jae-Young Jang, In-Ho Moon, Gary D. Hachtel Iterative Abstraction-Based CTL Model Checking. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Jaco van de Pol, Hans Zantema Binary Decision Diagrams by Shard Rewriting. Search on Bibsonomy MFCS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Farn Wang Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems. Search on Bibsonomy COMPSAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Kumar Neeraj Verma, Jean Goubault-Larrecq, Sanjiva Prasad, S. Arun-Kumar Reflecting BDDs in Coq. Search on Bibsonomy ASIAN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Parosh Aziz Abdulla, Per Bjesse, Niklas Eén Symbolic Reachability Analysis Based on SAT-Solvers. Search on Bibsonomy TACAS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Chris Wilson, David L. Dill, Randal E. Bryant Symbolic Simulation with Approximate Values. Search on Bibsonomy FMCAD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Beate Bollig, Ingo Wegener Complexity Theoretical Results on Partitioned (Nondeterministic) Binary Decision Diagrams. Search on Bibsonomy Theory Comput. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
18Enric Pastor, Jordi Cortadella, Marco A. Peña Structural Methods to Improve the Symbolic Analysis of Petri Nets. Search on Bibsonomy ICATPN The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
18Wolfgang Günther 0001, Rolf Drechsler Minimization of BDDs using linear transformations based on evolutionary techniques. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
18R. Glenn Wood, Rob A. Rutenbar FPGA routing and routability estimation via Boolean satisfiability. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
18Rajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani Symbolic Exploration of transition Hierarchies. Search on Bibsonomy TACAS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
18James H. Kukula, Thomas R. Shiple, Adnan Aziz Techniques for Implicit State Enumeration of EFSMs. Search on Bibsonomy FMCAD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
18William Chan 0001, Richard J. Anderson, Paul Beame, David Notkin Combining Constraint Solving and Symbolic Model Checking for a Class of a Systems with Non-linear Constraints. Search on Bibsonomy CAV The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
18Beate Bollig, Ingo Wegener Complexity Theoretical Results on Partitioned (Nondeterministic) Binary Decision Diagrams. Search on Bibsonomy MFCS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
18Valeria Bertacco, Maurizio Damiani The disjunctive decomposition of logic functions. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF disjunctive decomposition, combinational logic optimization
18Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
18Craig Damon, Daniel Jackson 0001, Somesh Jha Checking Relational Specifications With Binary Decision Diagrams. Search on Bibsonomy SIGSOFT FSE The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Z
18Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton Early Quantification and Partitioned Transition Relations. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
18Huey-Ling Chen, Chung-Ta King A New Model for Dynamic Processor Allocation in Multicomputer Systems. Search on Bibsonomy HICSS (1) The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
18Ted Stanion, Debashis Bhattacharya, Carl Sechen An efficient method for generating exhaustive test sets. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
18Timothy Kam, P. A. Subrahmanyam Comparing layouts with HDL models: a formal verification technique. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
18Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima Efficient construction of binary moment diagrams for verifying arithmetic circuits. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF word-level verification, binary moment diagram, arithmetic circuit, design verification
18Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton Improving Language Containment Using Fairness Graphs. Search on Bibsonomy CAV The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
18Bernard Boigelot, Pierre Wolper Symbolic Verification with Periodic Sets. Search on Bibsonomy CAV The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
18Enric Pastor, Oriol Roig, Jordi Cortadella, Rosa M. Badia Petri Net Analysis Using Boolean Manipulation. Search on Bibsonomy Application and Theory of Petri Nets The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
18Alan J. Hu, David L. Dill Efficient Verification with BDDs using Implicitly Conjoined Invariants. Search on Bibsonomy CAV The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
18Alan J. Hu, David L. Dill, Andreas J. Drexler, C. Han Yang Higher-Level Specification and Verification with BDDs. Search on Bibsonomy CAV The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
18Bernd Becker 0001 Synthesis for Testability: Binary Decision Diagrams. Search on Bibsonomy STACS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures
18Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
17Mehdi Mohammadi, Hossein Pazhoumand-dar, Mohsen Soryani, Hossein Moeinzadeh HS-ROBDD: an efficient variable order binary decision diagram. Search on Bibsonomy GECCO (Companion) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF binary decision diagram (bdd)
17Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiterminal BDD, numerical function generators, edge-valued binary decision diagrams, segment index encoder
17Yi Fang 0001, Nir Piterman, Amir Pnueli, Lenore D. Zuck Liveness with invisible ranking. Search on Bibsonomy Int. J. Softw. Tools Technol. Transf. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Parametrized systems, Deductive verification, BDD techniques, Liveness, Automatic verification
17Aarti Gupta, Malay K. Ganai, Chao Wang 0001, Zijiang Yang 0006, Pranav Ashar Learning from BDDs in SAT-based bounded model checking. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF BDD learning, learning, SAT, BDDs, bounded model checking, boolean satisfiability, SAT solvers, property checking
17Kanna Shimizu, David L. Dill Deriving a simulation input generator and a coverage metric from a formal specification. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF BDD minimization, input generation, coverage, testbench
17Hafiz Md. Hasan Babu, Tsutomu Sasao Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Binary decision diagram (BDD), multiple-valued decision diagram (MDD), multi-level logic synthesis, look-up table type FPGA design, multiple-valued logic, multiple-output function
17Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF FPGA technology, TOS, assignable functions, implicit BDD-based methods, mapping synthesis, multiple-output decomposition, preferable functions, subfunction sharing gain, subfunction sharing potential, variable partitioning for decomposition, Boolean functions, decomposition, computer-aided design of VLSI
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