Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Michael Theobald, Steven M. Nowick |
An Implicit Method for Hazard-Free Two-Level Logic Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 58-69, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hazard-free, two-level, dynamic-hazard-free prime implicants, asynchronous, BDD, logic minimization, implicit |
18 | Kazuhiro Nakamura, Satoshi Yamane |
Formal Verification of Real-Time Software by Symbolic Model-Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 99-108, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
temporal logic, approximations, BDD, symbolic model-checking, real-time software |
18 | Steve Haynal, Forrest Brewer |
Efficient encoding for exact symbolic automata-based scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 477-481, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, automata, BDD |
18 | Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III |
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 46(4), pp. 491-494, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
average case, complexity, BDD, Decision diagrams, multiple-valued functions, symmetric functions, asymptotic approximation |
18 | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
On Decomposition of Kleene TDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 234-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
decomposition, TDD, BDD, logic simulation |
18 | Yirng-An Chen, Randal E. Bryant |
PHDD: an efficient graph representation for floating point circuit verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 2-7, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
KFDD, *BMD, HDD, K*BMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD |
18 | Luc Robert, Grégoire Malandain |
Fast Binary Image Processing Using Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 1997 Conference on Computer Vision and Pattern Recognition (CVPR '97), June 17-19, 1997, San Juan, Puerto Rico, pp. 97-102, 1997, IEEE Computer Society, 0-8186-7822-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
binary image processing, mathematical morphology, BDD, digital topology |
18 | Shin-ichi Minato |
Generation of BDDs from hardware algorithm descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 644-649, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LSI CAD, logic synthesis, BDD, design verification, hardware algorithm |
18 | Daniel Král |
Polynomial-Size Binary Decision Diagrams for the Exactly Half-d-Hyperclique Problem Reading Each Input Bit Twice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 45(1), pp. 27-42, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Free binary decision diagrams, Binary decision diagrams |
18 | Wenhui Zhang |
Bounded Semantics of CTL and SAT-Based Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 11th International Conference on Formal Engineering Methods, ICFEM 2009, Rio de Janeiro, Brazil, December 9-12, 2009. Proceedings, pp. 286-305, 2009, Springer, 978-3-642-10372-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Sathiamoorthy Subbarayan |
Efficient Reasoning for Nogoods in Constraint Solvers with BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADL ![In: Practical Aspects of Declarative Languages, 10th International Symposium, PADL 2008, San Francisco, CA, USA, January 7-8, 2008., pp. 53-67, 2008, Springer, 978-3-540-77441-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Gianpiero Cabodi, Paolo Camurati, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer |
Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, FMCAD 2008, Portland, Oregon, USA, 17-20 November 2008, pp. 1-8, 2008, IEEE, 978-1-4244-2735-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Chao Wang 0001, Zijiang Yang 0006, Franjo Ivancic, Aarti Gupta |
Disjunctive image computation for software verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(2), pp. 10, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Model checking, formal verification, binary decision diagram, reachability analysis, image computation |
18 | Vaclav Dvorak |
Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 14th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2007), 26-29 March 2007, Tucson, Arizona, USA, pp. 178-185, 2007, IEEE Computer Society, 0-7695-2772-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Wassim Ayadi, Khedija Arour |
A Novel Parallel Boolean Approach for Discovering Frequent Itemsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM Workshops ![In: Workshops Proceedings of the 7th IEEE International Conference on Data Mining (ICDM 2007), October 28-31, 2007, Omaha, Nebraska, USA, pp. 297-302, 2007, IEEE Computer Society, 0-7695-3033-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Data mining, Association rules, Binary decision diagram, Frequent itemsets, Parallel data mining |
18 | Kevin Oo Tinmaung, David Howland, Russell Tessier |
Power-aware FPGA logic synthesis using binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 148-155, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, binary decision diagram, dynamic power |
18 | David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
Symbolic Model Checking of Analog/Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 316-323, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language |
18 | Ben Hardekopf, Calvin Lin |
The ant and the grasshopper: fast and accurate pointer analysis for millions of lines of code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, San Diego, California, USA, June 10-13, 2007, pp. 290-299, 2007, ACM, 978-1-59593-633-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
pointer analysis |
18 | Wassim Ayadi, Khedija Arour |
A Binary Decision Diagram to discover low threshold support frequent itemsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA Workshops ![In: 18th International Workshop on Database and Expert Systems Applications (DEXA 2007), 3-7 September 2007, Regensburg, Germany, pp. 509-513, 2007, IEEE Computer Society, 0-7695-2932-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
data mining, association rules, binary decision diagram, frequent item sets |
18 | Ondrej Lhoták, Stephen Curial, José Nelson Amaral |
Using ZBDDs in Points-to Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers, pp. 338-352, 2007, Springer, 978-3-540-85260-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Akashi Satoh |
High-Speed Parallel Hardware Architecture for Galois Counter Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1863-1866, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers |
Synthesis of irregular combinational functions with large don't care sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 287-292, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
logic synthesis, incompletely specified functions |
18 | Markus Behle |
On Threshold BDDs and the Optimal Variable Ordering Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOA ![In: Combinatorial Optimization and Applications, First International Conference, COCOA 2007, Xi'an, China, August 14-16, 2007, Proceedings, pp. 124-135, 2007, Springer, 978-3-540-73555-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich |
Symbolic Archive Representation for a Fast Nondominance Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMO ![In: Evolutionary Multi-Criterion Optimization, 4th International Conference, EMO 2007, Matsushima, Japan, March 5-8, 2007, Proceedings, pp. 111-125, 2007, Springer, 3-540-70927-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Martin Hell, Thomas Johansson 0001 |
Two New Attacks on the Self-Shrinking Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(8), pp. 3837-3843, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Ming-Hong Su, Chun-Yao Wang |
High level equivalence symmetric input identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 249-253, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Shin-ichi Minato, Hiroki Arimura |
Frequent Pattern Mining and Knowledge Indexing Based on Zero-Suppressed BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KDID ![In: Knowledge Discovery in Inductive Databases, 5th International Workshop, KDID 2006, Berlin, Germany, September 18, 2006, Revised Selected and Invited Papers, pp. 152-169, 2006, Springer, 978-3-540-75548-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Koen Claessen, Jan-Willem Roorda |
An Introduction to Symbolic Trajectory Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SFM ![In: Formal Methods for Hardware Verification, 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advanced Lectures, pp. 56-77, 2006, Springer, 978-3-540-34304-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Toni Jussila, Carsten Sinz, Armin Biere |
Extended Resolution Proofs for Symbolic SAT Solving with Quantification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing - SAT 2006, 9th International Conference, Seattle, WA, USA, August 12-15, 2006, Proceedings, pp. 54-60, 2006, Springer, 3-540-37206-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Farn Wang |
Symbolic Verification of Distributed Real-Time Systems with Complex Synchronizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 7th International Conference on Formal Engineering Methods, ICFEM 2005, Manchester, UK, November 1-4, 2005, Proceedings, pp. 300-314, 2005, Springer, 3-540-29797-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
model-checking, verification, real-time, synchronization, distributed |
18 | François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat |
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 550-560, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Differential Pull Down Networks, Side-channel attack, Differential Power Analysis, Binary Decision Diagrams |
18 | John Whaley, Dzintars Avots, Michael Carbin, Monica S. Lam |
Using Datalog with Binary Decision Diagrams for Program Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APLAS ![In: Programming Languages and Systems, Third Asian Symposium, APLAS 2005, Tsukuba, Japan, November 2-5, 2005, Proceedings, pp. 97-118, 2005, Springer, 3-540-29735-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Andrea Bobbio, Daniele Codetta Raiteri, Massimiliano De Pierro, Giuliana Franceschinis |
Efficient Analysis Algorithms for Parametric Fault Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FIRB-Perf ![In: FIRB-Perf Workshop on Techniques, Methodologies and Tools for Performance Evaluation of Complex Systems (FIRB-Perf 2005), 19 September 2005, Torino, Italy, pp. 91-105, 2005, IEEE Computer Society, 0-7695-2447-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P. Kurshan, Kenneth L. McMillan |
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 254-268, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster |
Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 129-145, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Gilles Audemard, Lakhdar Sais |
A Symbolic Search Based Approach for Quantified Boolean Formulas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 8th International Conference, SAT 2005, St. Andrews, UK, June 19-23, 2005, Proceedings, pp. 16-30, 2005, Springer, 3-540-26276-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Satisfiability, Binary decision diagram, Quantified boolean formula |
18 | Tarik Hadzic, Henrik Reif Andersen |
Interactive Reconfiguration in Power Supply Restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CP ![In: Principles and Practice of Constraint Programming - CP 2005, 11th International Conference, CP 2005, Sitges, Spain, October 1-5, 2005, Proceedings, pp. 767-771, 2005, Springer, 3-540-29238-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson |
Multi-threaded reachability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 467-470, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parallel, multi-threaded, reachability analysis |
18 | Yong Ou, Joanne Bechta Dugan |
Modular solution of dynamic multi-phase systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 53(4), pp. 499-508, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Ofer Strichman |
Accelerating Bounded Model Checking of Safety Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 24(1), pp. 5-24, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SAT, Bounded Model Checking |
18 | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang |
Safety Property Verification Using Sequential SAT and Bounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(2), pp. 132-143, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Andrés Martinelli, René Krenz, Elena Dubrova |
Disjoint-support Boolean decomposition combining functional and structural methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 597-599, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Guanghui Li 0001, Xiaowei Li 0001 |
Circuit-Width Based Heuristic for Boolean Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 336-341, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Fang Yu 0001, Bow-Yaw Wang |
Toward Unbounded Model Checking for Region Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 20-33, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Region automata, Real-time systems, Model checking, Verification, Induction, BMC |
18 | Bijan Alizadeh, Zainalabedin Navabi |
Property Checking based on Hierarchical Integer Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 16-18 June 2004, Hamilton, Canada, pp. 26-35, 2004, IEEE Computer Society, 0-7695-2077-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Sharon Shoham, Orna Grumberg |
Monotonic Abstraction-Refinement for CTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 10th International Conference, TACAS 2004, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2004, Barcelona, Spain, March 29 - April 2, 2004, Proceedings, pp. 546-560, 2004, Springer, 3-540-21299-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Zijiang Yang 0006, Rajeev Alur |
Variable Reuse for Efficient Image Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004, Proceedings, pp. 430-444, 2004, Springer, 3-540-23738-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | In-Ho Moon, Carl Pixley |
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004, Proceedings, pp. 144-158, 2004, Springer, 3-540-23738-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Bijan Alizadeh, Zainalabedin Navabi |
Using Integer Equations to Check PSL Properties in RT Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 83-86, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening |
A SAT-based algorithm for reparameterization in symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 524-529, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SAT checkers, safety property checking, bounded model checking, symbolic simulation, parametric representation |
18 | Rachel Tzoref, Mark Matusevich, Eli Berger, Ilan Beer |
An Optimized Symbolic Bounded Model Checking Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 141-149, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Marcelo Glusman, Gila Kamhi, Sela Mador-Haim, Ranan Fraer, Moshe Y. Vardi |
Multiple-Counterexample Guided Iterative Abstraction Refinement: An Industrial Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 9th International Conference, TACAS 2003, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003, Proceedings, pp. 176-191, 2003, Springer, 3-540-00898-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Dirk Beyer 0001, Andreas Noack |
Can Decision Diagrams Overcome State Space Explosion in Real-Time Verification? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2003, 23rd IFIP WG 6.1 International Conference, Berlin, Germany, September 29 - October 2, 2003, Proceedings, pp. 193-208, 2003, Springer, 3-540-20175-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Kenneth L. McMillan |
Applying SAT Methods in Unbounded Symbolic Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 14th International Conference, CAV 2002,Copenhagen, Denmark, July 27-31, 2002, Proceedings, pp. 250-264, 2002, Springer, 3-540-43997-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Michael J. C. Gordon |
PuzzleTool : An Example of Programming Computation and Deduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 15th International Conference, TPHOLs 2002, Hampton, VA, USA, August 20-23, 2002, Proceedings, pp. 214-229, 2002, Springer, 3-540-44039-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Sherief Reda, Rolf Drechsler, Alex Orailoglu |
On the Relation between SAT and BDDs for Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 394-399, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Rupesh S. Shelar, Sachin S. Sapatnekar |
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 87-92, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Low Power, Logic Synthesis, Pass Transistor Logic |
18 | Fady Copty, Limor Fix, Ranan Fraer, Enrico Giunchiglia, Gila Kamhi, Armando Tacchella, Moshe Y. Vardi |
Benefits of Bounded Model Checking at an Industrial Setting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings, pp. 436-453, 2001, Springer, 3-540-42345-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss |
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings, pp. 131-143, 2001, Springer, 3-540-42345-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Henrik Brosenne, Matthias Homeister, Stephan Waack |
Graph-Driven Free Parity BDDs: Algorithms and Lower Bounds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2001, 26th International Symposium, MFCS 2001 Marianske Lazne, Czech Republic, August 27-31, 2001, Proceedings, pp. 212-223, 2001, Springer, 3-540-42496-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti 0001 |
Symbolic verification of Boolean constraints over partially specified functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 113-116, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer |
AQUILA: An Equivalence Checking System for Large Sequential Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(5), pp. 443-464, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
state exploration, formal verification, Design verification, equivalence checking |
18 | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto |
Symbolic optimization of interacting controllers based onredundancy identification and removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7), pp. 760-772, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jan Friso Groote, Jaco van de Pol |
Equational Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LPAR ![In: Logic for Programming and Automated Reasoning, 7th International Conference, LPAR 2000, Reunion Island, France, November 11-12, 2000, Proceedings, pp. 161-178, 2000, Springer. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jae-Young Jang, In-Ho Moon, Gary D. Hachtel |
Iterative Abstraction-Based CTL Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 502-507, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Jaco van de Pol, Hans Zantema |
Binary Decision Diagrams by Shard Rewriting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2000, 25th International Symposium, MFCS 2000, Bratislava, Slovakia, August 28 - September 1, 2000, Proceedings, pp. 609-618, 2000, Springer, 3-540-67901-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Farn Wang |
Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 24th International Computer Software and Applications Conference (COMPSAC 2000), 25-28 October 2000, Taipei, Taiwan, pp. 509-515, 2000, IEEE Computer Society, 0-7695-0792-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Kumar Neeraj Verma, Jean Goubault-Larrecq, Sanjiva Prasad, S. Arun-Kumar |
Reflecting BDDs in Coq. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIAN ![In: Advances in Computing Science - ASIAN 2000, 6th Asian Computing Science Conference, Penang, Malaysia, November 25-27, 2000, Proceedings, pp. 162-181, 2000, Springer, 3-540-41428-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Parosh Aziz Abdulla, Per Bjesse, Niklas Eén |
Symbolic Reachability Analysis Based on SAT-Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for Construction and Analysis of Systems, 6th International Conference, TACAS 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 411-425, 2000, Springer, 3-540-67282-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Chris Wilson, David L. Dill, Randal E. Bryant |
Symbolic Simulation with Approximate Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 470-485, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Beate Bollig, Ingo Wegener |
Complexity Theoretical Results on Partitioned (Nondeterministic) Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 32(4), pp. 487-503, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Enric Pastor, Jordi Cortadella, Marco A. Peña |
Structural Methods to Improve the Symbolic Analysis of Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICATPN ![In: Application and Theory of Petri Nets 1999, 20th International Conference, ICATPN '99, Williamsburg, Virginia, USA, June 21-25, 1999, Proceedings, pp. 26-45, 1999, Springer, 3-540-66132-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Wolfgang Günther 0001, Rolf Drechsler |
Minimization of BDDs using linear transformations based on evolutionary techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 387-390, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | R. Glenn Wood, Rob A. Rutenbar |
FPGA routing and routability estimation via Boolean satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(2), pp. 222-231, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Rajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani |
Symbolic Exploration of transition Hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for Construction and Analysis of Systems, 4th International Conference, TACAS '98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 330-344, 1998, Springer, 3-540-64356-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | James H. Kukula, Thomas R. Shiple, Adnan Aziz |
Techniques for Implicit State Enumeration of EFSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Second International Conference, FMCAD '98, Palo Alto, California, USA, November 4-6, 1998, Proceedings, pp. 469-482, 1998, Springer, 3-540-65191-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | William Chan 0001, Richard J. Anderson, Paul Beame, David Notkin |
Combining Constraint Solving and Symbolic Model Checking for a Class of a Systems with Non-linear Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 316-327, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Beate Bollig, Ingo Wegener |
Complexity Theoretical Results on Partitioned (Nondeterministic) Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1997, 22nd International Symposium, MFCS'97, Bratislava, Slovakia, August 25-29, 1997, Proceedings, pp. 159-168, 1997, Springer, 3-540-63437-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Valeria Bertacco, Maurizio Damiani |
The disjunctive decomposition of logic functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 78-82, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
disjunctive decomposition, combinational logic optimization |
18 | Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer |
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 728-733, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Craig Damon, Daniel Jackson 0001, Somesh Jha |
Checking Relational Specifications With Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGSOFT FSE ![In: Proceedings of the Fourth ACM SIGSOFT Symposium on Foundations of Software Engineering, SIGSOFT1996, San Francisco, California, USA, October 16-18, 1996, pp. 70-80, 1996, ACM, 978-0-89791-797-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Z |
18 | Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton |
Early Quantification and Partitioned Transition Relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 12-19, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Huey-Ling Chen, Chung-Ta King |
A New Model for Dynamic Processor Allocation in Multicomputer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 29th Annual Hawaii International Conference on System Sciences (HICSS-29), January 3-6, 1996, Maui, Hawaii, USA, pp. 626-635, 1996, IEEE Computer Society, 0-8186-7324-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Ted Stanion, Debashis Bhattacharya, Carl Sechen |
An efficient method for generating exhaustive test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1516-1525, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Timothy Kam, P. A. Subrahmanyam |
Comparing layouts with HDL models: a formal verification technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4), pp. 503-509, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima |
Efficient construction of binary moment diagrams for verifying arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 78-82, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
word-level verification, binary moment diagram, arithmetic circuit, design verification |
18 | Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton |
Improving Language Containment Using Fairness Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 6th International Conference, CAV '94, Stanford, California, USA, June 21-23, 1994, Proceedings, pp. 391-403, 1994, Springer, 3-540-58179-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Bernard Boigelot, Pierre Wolper |
Symbolic Verification with Periodic Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 6th International Conference, CAV '94, Stanford, California, USA, June 21-23, 1994, Proceedings, pp. 55-67, 1994, Springer, 3-540-58179-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Enric Pastor, Oriol Roig, Jordi Cortadella, Rosa M. Badia |
Petri Net Analysis Using Boolean Manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Application and Theory of Petri Nets ![In: Application and Theory of Petri Nets 1994, 15th International Conference, Zaragoza, Spain, June 20-24, 1994, Proceedings, pp. 416-435, 1994, Springer, 3-540-58152-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Alan J. Hu, David L. Dill |
Efficient Verification with BDDs using Implicitly Conjoined Invariants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 3-14, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Alan J. Hu, David L. Dill, Andreas J. Drexler, C. Han Yang |
Higher-Level Specification and Verification with BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, Fourth International Workshop, CAV '92, Montreal, Canada, June 29 - July 1, 1992, Proceedings, pp. 82-95, 1992, Springer, 3-540-56496-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Bernd Becker 0001 |
Synthesis for Testability: Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 92, 9th Annual Symposium on Theoretical Aspects of Computer Science, Cachan, France, February 13-15, 1992, Proceedings, pp. 501-512, 1992, Springer, 3-540-55210-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures |
18 | Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima |
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 52-57, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Mehdi Mohammadi, Hossein Pazhoumand-dar, Mohsen Soryani, Hossein Moeinzadeh |
HS-ROBDD: an efficient variable order binary decision diagram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, Companion Material, pp. 2115-2118, 2009, ACM, 978-1-60558-505-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
binary decision diagram (bdd) |
17 | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 535-540, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiterminal BDD, numerical function generators, edge-valued binary decision diagrams, segment index encoder |
17 | Yi Fang 0001, Nir Piterman, Amir Pnueli, Lenore D. Zuck |
Liveness with invisible ranking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 8(3), pp. 261-279, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Parametrized systems, Deductive verification, BDD techniques, Liveness, Automatic verification |
17 | Aarti Gupta, Malay K. Ganai, Chao Wang 0001, Zijiang Yang 0006, Pranav Ashar |
Learning from BDDs in SAT-based bounded model checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 824-829, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
BDD learning, learning, SAT, BDDs, bounded model checking, boolean satisfiability, SAT solvers, property checking |
17 | Kanna Shimizu, David L. Dill |
Deriving a simulation input generator and a coverage metric from a formal specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 801-806, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
BDD minimization, input generation, coverage, testbench |
17 | Hafiz Md. Hasan Babu, Tsutomu Sasao |
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 147-152, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Binary decision diagram (BDD), multiple-valued decision diagram (MDD), multi-level logic synthesis, look-up table type FPGA design, multiple-valued logic, multiple-output function |
17 | Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich |
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(3), pp. 313-350, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA technology, TOS, assignable functions, implicit BDD-based methods, mapping synthesis, multiple-output decomposition, preferable functions, subfunction sharing gain, subfunction sharing potential, variable partitioning for decomposition, Boolean functions, decomposition, computer-aided design of VLSI |