Search results for "CASES"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Narasinga Rao Miniskar, Pankaj Shailendra Gode, Soma Kohli, Donghoon Yoo	Function inlining and loop unrolling for loop acceleration in reconfigurable processors.	CASES	2012	DBLP DOI BibTeX RDF
1	Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele	Power agnostic technique for efficient temperature estimation of multicore embedded systems.	CASES	2012	DBLP DOI BibTeX RDF
1	Gaurav Chadha, Scott A. Mahlke, Satish Narayanasamy	When less is more (LIMO): controlled parallelism forimproved efficiency.	CASES	2012	DBLP DOI BibTeX RDF
1	Xuemeng Zhang, Hui Wu 0001, Jingling Xue	An efficient heuristic for instruction scheduling on clustered vliw processors.	CASES	2011	DBLP DOI BibTeX RDF
1	Sang Lyul Min, Eyee Hyun Nam	Hardware/software architecture for flash memory storage systems.	CASES	2011	DBLP DOI BibTeX RDF
1	Rajesh K. Gupta 0001, Vincent John Mooney (eds.)	Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2011, part of the Seventh Embedded Systems Week, ESWeek 2011, Taipei, Taiwan, October 9-14, 2011	CASES	2011	DBLP BibTeX RDF
1	Adam R. Smith, Prasad A. Kulkarni	Localizing globals and statics to make C programs thread-safe.	CASES	2011	DBLP DOI BibTeX RDF
1	Abbas BanaiyanMofrad, Houman Homayoun, Nikil D. Dutt	FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.	CASES	2011	DBLP DOI BibTeX RDF
1	Viswanath Krishnamurthy, Swamy D. Ponpandi, Akhilesh Tyagi	A novel thread scheduler design for polymorphic embedded systems.	CASES	2011	DBLP DOI BibTeX RDF
1	Ricardo S. Ferreira 0001, Julio C. Goldner Vendramini, Lucas Mucida, Monica Magalhães Pereira, Luigi Carro	An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture.	CASES	2011	DBLP DOI BibTeX RDF
1	Arvind	Automatic generation of hardware/software interfaces.	CASES	2011	DBLP DOI BibTeX RDF
1	John Sartori, Joseph Sloan, Rakesh Kumar 0002	Stochastic computing: embracing errors in architectureand design of processors and applications.	CASES	2011	DBLP DOI BibTeX RDF
1	Chih-Sheng Wang, Guillermo A. Pérez 0001, Yeh-Ching Chung, Wei-Chung Hsu, Wei-Kuan Shih, Hong-Rong Hsu	A method-based ahead-of-time compiler for android applications.	CASES	2011	DBLP DOI BibTeX RDF
1	Brett H. Meyer, Benton H. Calhoun, John C. Lach, Kevin Skadron	Cost-effective safety and fault localization using distributed temporal redundancy.	CASES	2011	DBLP DOI BibTeX RDF
1	Eunjung Park, Sameer Kulkarni, John Cavazos	An evaluation of different modeling techniques for iterative compilation.	CASES	2011	DBLP DOI BibTeX RDF
1	Quentin Colombet, Florian Brandner, Alain Darte	Studying optimal spilling in the light of SSA.	CASES	2011	DBLP DOI BibTeX RDF
1	Ke Bai 0002, Di Lu, Aviral Shrivastava	Vector class on limited local memory (LLM) multi-core processors.	CASES	2011	DBLP DOI BibTeX RDF
1	Heiko Falk, Helena Kotthaus	WCET-driven cache-aware code positioning.	CASES	2011	DBLP DOI BibTeX RDF
1	Amit Kumar Singh 0002, Akash Kumar 0001, Thambipillai Srikanthan	A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs.	CASES	2011	DBLP DOI BibTeX RDF
1	Gernot Heiser	Low-overhead virtualization of mobile platforms.	CASES	2011	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Aviral Shrivastava	Smart cache cleaning: energy efficient vulnerability reduction in embedded processors.	CASES	2011	DBLP DOI BibTeX RDF
1	Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello	Graph-coloring and treescan register allocation using repairing.	CASES	2011	DBLP DOI BibTeX RDF
1	Mafijul Md. Islam, Per Stenström	A unified approach to eliminate memory accesses early.	CASES	2011	DBLP DOI BibTeX RDF
1	Sascha Plazar, Jan C. Kleinsorge, Heiko Falk, Peter Marwedel	WCET-driven branch prediction aware code positioning.	CASES	2011	DBLP DOI BibTeX RDF
1	John Sartori, Rakesh Kumar 0002	Architecting processors to allow voltage/reliability tradeoffs.	CASES	2011	DBLP DOI BibTeX RDF
1	Wajid Hassan Minhass, Paul Pop, Jan Madsen	System-level modeling and synthesis of flow-based microfluidic biochips.	CASES	2011	DBLP DOI BibTeX RDF
1	Siddharth Nilakantan, Srikanth Annangi, Nikhil Gulati, Karthik Sangaiah, Mark Hempstead	Evaluation of an accelerator architecture for speckle reducing anisotropic diffusion.	CASES	2011	DBLP DOI BibTeX RDF
1	Tayyeb Mahmood, Soontae Kim	Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers.	CASES	2011	DBLP DOI BibTeX RDF
1	Seong-Won Lee, Soo-Mook Moon	Selective just-in-time compilation for client-side mobile javascript engine.	CASES	2011	DBLP DOI BibTeX RDF
1	Linh T. X. Phan, Insup Lee 0001, Oleg Sokolsky	Compositional analysis of real-time embedded systems.	CASES	2011	DBLP DOI BibTeX RDF
1	Alena Simalatsar, Yusi Ramadian, Kai Lampka, Simon Perathoner, Roberto Passerone, Lothar Thiele	Enabling parametric feasibility analysis in real-time calculus driven performance evaluation.	CASES	2011	DBLP DOI BibTeX RDF
1	Krishna V. Palem	Compilers, architectures and synthesis for embedded computing: retrospect and prospect.	CASES	2010	DBLP DOI BibTeX RDF
1	Elena Maftei, Paul Pop, Jan Madsen	Routing-based synthesis of digital microfluidic biochips.	CASES	2010	DBLP DOI BibTeX RDF
1	Zhimin Chen 0002, Ambuj Sinha, Patrick Schaumont	Implementing virtual secure circuit using a custom-instruction approach.	CASES	2010	DBLP DOI BibTeX RDF
1	Vladimir Uzelac, Aleksandar Milenkovic	Hardware-based data value and address trace filtering techniques.	CASES	2010	DBLP DOI BibTeX RDF
1	Sebastian Buchwald, Andreas Zwinkau	Instruction selection by graph transformation.	CASES	2010	DBLP DOI BibTeX RDF
1	Ganesh S. Dasika, Mark Woh, Sangwon Seo, Nathan Clark, Trevor N. Mudge, Scott A. Mahlke	Mighty-morphing power-SIMD.	CASES	2010	DBLP DOI BibTeX RDF
1	JongSoo Park, James D. Balfour, William J. Dally	Fine-grain dynamic instruction placement for L0 scratch-pad memory.	CASES	2010	DBLP DOI BibTeX RDF
1	Luigi Carro, Georgi Gaydadjiev	Challenges for embedded multicore architecture.	CASES	2010	DBLP DOI BibTeX RDF
1	Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongwung Kim, Jeonghun Cho	Implementing dynamic implied addressing mode for multi-output instructions.	CASES	2010	DBLP DOI BibTeX RDF
1	Ji Gu, Hui Guo 0001	Enabling large decoded instruction loop caching for energy-aware embedded processors.	CASES	2010	DBLP DOI BibTeX RDF
1	Yun Liang 0001, Tulika Mitra	Improved procedure placement for set associative caches.	CASES	2010	DBLP DOI BibTeX RDF
1	Cupertino Miranda, Antoniu Pop, Philippe Dumont, Albert Cohen 0001, Marc Duranton	Erbium: a deterministic, concurrent intermediate representation to map data-flow tasks to scalable, persistent streaming processes.	CASES	2010	DBLP DOI BibTeX RDF
1	Sylvain Girbal, Olivier Temam, Sami Yehia, Hugues Berry, Zheng Li	A memory interface for multi-purpose multi-stream accelerators.	CASES	2010	DBLP DOI BibTeX RDF
1	Andrea Marongiu, Paolo Burgio, Luca Benini	Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs.	CASES	2010	DBLP DOI BibTeX RDF
1	Mafijul Md. Islam, Per Stenström	Characterization and exploitation of narrow-width loads: the narrow-width cache approach.	CASES	2010	DBLP DOI BibTeX RDF
1	Danny Petrasek, Alan Barr, Krishna V. Palem	The virtual hospital: the emergence of telemedicine.	CASES	2010	DBLP DOI BibTeX RDF
1	Arindam Mallik, Peter Marwedel, Dimitrios Soudris, Sander Stuijk	MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs.	CASES	2010	DBLP DOI BibTeX RDF
1	Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil D. Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi	E < MC2: less energy through multi-copy cache.	CASES	2010	DBLP DOI BibTeX RDF
1	Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada	Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems.	CASES	2010	DBLP DOI BibTeX RDF
1	Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan, Masahiro Fujita	Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.	CASES	2010	DBLP DOI BibTeX RDF
1	Xuejun Yang, Li Wang 0027, Jingling Xue, Tao Tang 0001, Xiaoguang Ren, Sen Ye	Improving scratchpad allocation with demand-driven data tiling.	CASES	2010	DBLP DOI BibTeX RDF
1	Vladimir Uzelac, Aleksandar Milenkovic, Martin Burtscher, Milena Milenkovic	Real-time unobtrusive program execution trace compression using branch predictor events.	CASES	2010	DBLP DOI BibTeX RDF
1	Mircea Namolaru, Albert Cohen 0001, Grigori Fursin, Ayal Zaks, Ari Freund 0001	Practical aggregation of semantical program properties for machine learning based optimization.	CASES	2010	DBLP DOI BibTeX RDF
1	Dongwon Lee 0003, Marilyn Wolf, Hyesoon Kim	Design space exploration of the turbo decoding algorithm on GPUs.	CASES	2010	DBLP DOI BibTeX RDF
1	Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem, Avani Devarasetty, Phani Deepak Parasuramuni	Optimizing energy to minimize errors in dataflow graphs using approximate adders.	CASES	2010	DBLP DOI BibTeX RDF
1	Alan H. Barr	Parsimonious information technologies for pixels, perception, wetware and simulation: issues for Petrasek's global virtual hospital system.	CASES	2010	DBLP DOI BibTeX RDF
1	Apala Guha, Kim M. Hazelwood, Mary Lou Soffa	Balancing memory and performance through selective flushing of software code caches.	CASES	2010	DBLP DOI BibTeX RDF
1	Michael R. Jantz, Prasad A. Kulkarni	Eliminating false phase interactions to reduce optimization phase order search space.	CASES	2010	DBLP DOI BibTeX RDF
1	Rajeswari Pingali, P. Niranjana	Mosaic of organic development through technology intervention in the rural indian context.	CASES	2010	DBLP DOI BibTeX RDF
1	Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke, Sukjin Kim	Resource recycling: putting idle resources to work on a composable accelerator.	CASES	2010	DBLP DOI BibTeX RDF
1	Vinod Kathail, Reid Tatge, Rajeev Barua (eds.)	Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010	CASES	2010	DBLP BibTeX RDF
1	Kapil Anand, Rajeev Barua	Instruction cache locking inside a binary rewriter.	CASES	2009	DBLP DOI BibTeX RDF	cache locking, embedded systems, caches, binary rewriting
1	Duo Liu, Zili Shao, Meng Wang 0005, Minyi Guo, Jingling Xue	Optimal loop parallelization for maximizing iteration-level parallelism.	CASES	2009	DBLP DOI BibTeX RDF	iteration-level parallelism, retiming, loop transformation, loop parallelization, data dependence graph
1	Dan Fay, Li Shang, Dirk Grunwald	A platform for developing adaptable multicore applications.	CASES	2009	DBLP DOI BibTeX RDF	parallelization, multicore, run-time systems, frequency scaling, application adaptation
1	Yu Wang 0002, Jiang Xu 0001, Shengxi Huang, Weichen Liu, Huazhong Yang	A case study of on-chip sensor network in multiprocessor system-on-chip.	CASES	2009	DBLP DOI BibTeX RDF	sensor network, reliability, low-power, system on chip, dynamic control, power grid noise
1	M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli	Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.	CASES	2009	DBLP DOI BibTeX RDF	MSPT, spacer technique, decoder, emerging technologies, gray code, crossbars, nanowires
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Fine-grain performance scaling of soft vector processors.	CASES	2009	DBLP DOI BibTeX RDF	VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	Priya Narasimhan, Rajeev Gandhi, Dan Rossi	Smartphone-based assistive technologies for the blind.	CASES	2009	DBLP DOI BibTeX RDF	assistive technonologies, currency identification, visual impairment, blind, transportation, smartphones, retail
1	Mahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk 0001, Sri Hari Krishna Narayanan	Slicing based code parallelization for minimizing inter-processor communication.	CASES	2009	DBLP DOI BibTeX RDF	automatic code parallelization, code analysis and optimization, iteration space slicing, parallelizing compilers
1	Partha S. Roop, Sidharta Andalam, Reinhard von Hanxleden, Simon Yuan, Claus Traulsen	Tight WCRT analysis of synchronous C programs.	CASES	2009	DBLP DOI BibTeX RDF	precision timed machines, model checking, synchronous languages, static timing analysis
1	Mouad Bahi, Christine Eisenbeis	Spatial complexity of reversibly computable DAG.	CASES	2009	DBLP DOI BibTeX RDF	garbage minimization, spatial complexity, reversible computing
1	Ian Gray, Neil C. Audsley	Exposing non-standard architectures to embedded software using compile-time virtualisation.	CASES	2009	DBLP DOI BibTeX RDF	architectures, virtualization, embedded, application-specific, compile-time
1	Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang 0032, Yuan Xie 0001, Frank Mueller 0001	CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.	CASES	2009	DBLP DOI BibTeX RDF	LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC
1	Elena Maftei, Paul Pop, Jan Madsen	Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips.	CASES	2009	DBLP DOI BibTeX RDF	reconfigurability, microfluidics, biochips
1	Jinho Seol, Hyotaek Shim, Jaegeuk Kim, Seungryoul Maeng	A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks.	CASES	2009	DBLP DOI BibTeX RDF	buffer replacement algorithm, nand flash memory, solid state disk (SSD)
1	Fabian Scheler, Wanja Hofer, Benjamin Oechslein, Rudi Pfister, Wolfgang Schröder-Preikschat, Daniel Lohmann	Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system.	CASES	2009	DBLP DOI BibTeX RDF	ciao, priority-driven, rate-monotonic priority inversion, tricore, real-time systems, interrupt handling
1	Mark Hempstead, Gu-Yeon Wei, David M. Brooks	An accelerator-based wireless sensor network processor in 130nm CMOS.	CASES	2009	DBLP DOI BibTeX RDF	accelerator-based, wireless sensor networks, ultra-low power
1	Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy 0001, Ranjani Narayan	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.	CASES	2009	DBLP DOI BibTeX RDF	application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
1	Yuexuan Wang, Yongcai Wang, Xiao Qi, Liwen Xu	OPAIMS: open architecture precision agriculture information monitoring system.	CASES	2009	DBLP DOI BibTeX RDF	information monitoring, wireless sensor networks, agriculture
1	Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu	Energy-aware probabilistic multiplier: design and analysis.	CASES	2009	DBLP DOI BibTeX RDF	optimization, multiplier, voltage scaling, probabilistic computation
1	Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke	CGRA express: accelerating execution using dynamic operation fusion.	CASES	2009	DBLP DOI BibTeX RDF	latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture
1	Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak	Exploiting residue number system for power-efficient digital signal processing in embedded processors.	CASES	2009	DBLP DOI BibTeX RDF	compiler, power, processor, residue number system, per-
1	Jörg Henkel, Sri Parameswaran (eds.)	Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009	CASES	2009	DBLP BibTeX RDF
1	Yong Dou, Fei Xia, Jingfei Jiang	Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA.	CASES	2009	DBLP DOI BibTeX RDF	SCFGS, reconfigurable algorithm accelerator, secondary structure prediction, FPGA, RNA
1	Tao Li 0008, Zhigang Sun, Wu Jigang, Xicheng Lu	Fast enumeration of maximal valid subgraphs for custom-instruction identification.	CASES	2009	DBLP DOI BibTeX RDF	ISE identification, custom processors, maximal subgraph
1	Garo Bournoutian, Alex Orailoglu	Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.	CASES	2009	DBLP DOI BibTeX RDF	compiler assisted hardware, pipeline stalls, embedded processors, data cache
1	Soon Fatt Yoon	III-V/Si integration: potential and outlook for integrated low power micro and nanosystems.	CASES	2009	DBLP DOI BibTeX RDF	heterogeneous integration
1	Krishna V. Palem, Lakshmi N. Chakrapani, Zvi M. Kedem, Lingamneni Avinash, Kirthi Krishna Muntimadugu	Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects.	CASES	2009	DBLP DOI BibTeX RDF	approximate arithmetic, approximate design, probabilistic CMOS, probabilistic arithmetic, probabilistic design, digital signal processing
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	Mapping stream programs onto heterogeneous multiprocessor systems.	CASES	2009	DBLP DOI BibTeX RDF	partitioning, multicore, convexity, stream programming
1	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Hybrid multithreading for VLIW processors.	CASES	2009	DBLP DOI BibTeX RDF	multithreading, clustered VLIW processors
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
1	Dietmar Ebner, Bernhard Scholz, Andreas Krall	Progressive spill code placement.	CASES	2009	DBLP DOI BibTeX RDF	constrained min-cut, spilling, register allocation, SSA form
1	Joseph Sloan, Rakesh Kumar 0002	Towards scalable reliability frameworks for error prone CMPs.	CASES	2009	DBLP DOI BibTeX RDF	dynamic constitution, in-network fault tolerance
1	Margaret Martonosi	ZebraNet and beyond: applications and systems support for mobile, dynamic networks.	CASES	2008	DBLP DOI BibTeX RDF
1	Hoseok Chang, Wonyong Sung	Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware.	CASES	2008	DBLP DOI BibTeX RDF	irregular access, non-aligned access, packing buffer, split line buffer, compiler, SIMD, vectorization
1	Chengmo Yang, Alex Orailoglu	A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization.	CASES	2008	DBLP DOI BibTeX RDF	fault detection, checkpointing, fault recovery
1	Jerry Hom, Ulrich Kremer	Execution context optimization for disk energy.	CASES	2008	DBLP DOI BibTeX RDF	synchronization, user study, multiprogramming, runtime adaptation
1	Walter Binder, Alex Villazón, Martin Schoeberl, Philippe Moret	Cache-aware cross-profiling for java processors.	CASES	2008	DBLP DOI BibTeX RDF	cross-profiling, embedded java processors, platform-independent dynamic metrics, bytecode instrumentation
1	Lakshmi N. Chakrapani, Kirthi Krishna Muntimadugu, Lingamneni Avinash, Jason George, Krishna V. Palem	Highly energy and performance efficient embedded computing through approximately correct arithmetic: a mathematical foundation and preliminary experimental validation.	CASES	2008	DBLP DOI BibTeX RDF	digital signal pocessing, voltage overscaling

Publications at "CASES"( http://dblp.L3S.de/Venues/CASES )