Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Jürgen Maier 0002, Andreas Steininger, Robert Najvirt	The Hidden Behavior of a D-Latch.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
16	Jagadish Rajpoot, Shivam Verma	Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Taeyun Lee, In Jun Jung, Seong-Ook Jung	High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Young-Min Kang, Jung-Jin Park, Geon-Hak Kim, Ik-Joon Chang, Jinsang Kim	Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang 0009, Mingche Lai, Weifeng He	A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Hao Wang 0169, Dongxing Ma, Huaguo Liang, Yiming Ouyang, Aibin Yan	Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets.	J. Electron. Test.	2023	DBLP DOI BibTeX RDF
16	T. Dhanushya, T. Latha	High Reliability Soft Error Hardened Latch Designfor Nanoscale CMOS Technology using PVT Variation.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Zhouyu Gong, Dongxing Ma, Xiaolei Wang, Yingchun Lu, Wenfa Zhan, Huaguo Liang, Tianming Ni	Fault-avoidance C-element based low overhead and TNU-resilient latch.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Muhammad Imran Khan 0007	Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
16	Dake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, Andrew Rittenbach, Pierluigi Nuzzo 0002, Peter A. Beerel	Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP.	CoRR	2023	DBLP DOI BibTeX RDF
16	Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe	Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator.	IEICE Trans. Inf. Syst.	2023	DBLP DOI BibTeX RDF
16	Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare	A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO.	PRIME	2023	DBLP DOI BibTeX RDF
16	Abdullah Alshehri 0003, Abdullah Alqarni, Kuilian Yang, Hossein Fariborzi	A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application.	PRIME	2023	DBLP DOI BibTeX RDF
16	Karthik Swaminathan, Ramon Bertran, Doug Balazich, Alper Buyuktosunoglu, Arvind Haran, Sean M. Carey, Karl Anderson, Hans M. Jacobson, Matthias Pflanz, Pradip Bose	Characterization and Exploration of Latch Checkers for Efficient RAS Protection.	DSN-S	2023	DBLP DOI BibTeX RDF
16	Hamid Karrari, Pietro Andreani, Siyu Tan	A High-Speed Comparator Using a New Regeneration Latch.	MWSCAS	2023	DBLP DOI BibTeX RDF
16	Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang	Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL.	MWSCAS	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui 0004, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001	High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology.	DATE	2023	DBLP DOI BibTeX RDF
16	Shuo Cai, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu 0009	A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design.	ATS	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Xuehua Li, Zhongyu Gao, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen	Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications.	ATS	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Yu Chen, Zhengfeng Huang, Jie Cui 0004, Xiaoqing Wen	A High-Performance and P-Type FeFET-Based Non-Volatile Latch.	ATS	2023	DBLP DOI BibTeX RDF
16	Mustafa Mert Esen, Sükrü Uzun, Emre Göncü	FPGA Latch Primitive based Efficient True Random Number Generators.	ICECS	2023	DBLP DOI BibTeX RDF
16	Zeyang Xu, Shanlin Xiao, Lingfeng Zhou, Bohan Wang, Zhiyi Yu	Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement.	ICTA	2023	DBLP DOI BibTeX RDF
16	Hao Deng 0003, Phaneendra Bikkina, Esko Mikkola, Runxi Zhang, Jinghong Chen	A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.	ESSCIRC	2023	DBLP DOI BibTeX RDF
16	Andrew Cannon, Tasnuva Farheen, Sourav Roy, Shahin Tajik, Domenic Forte	Protection Against Physical Attacks Through Self-Destructive Polymorphic Latch.	ICCAD	2023	DBLP DOI BibTeX RDF
16	Suraj Kumar Prusty, V. K. Surya, Nijwm Wary	A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE).	NEWCAS	2023	DBLP DOI BibTeX RDF
16	Feng Tai, Qiang Li 0021	Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA.	NEWCAS	2023	DBLP DOI BibTeX RDF
16	Guoshun Sun, Jingbing Li, Uzair Aslam Bhatti, Jixin Ma 0001, Fangchun Dong, Yanyi Li	Robust Zero-Watermarking Algorithm for Medical Images Based on AGAST-LATCH and DCT.	SNPD-Winter	2023	DBLP DOI BibTeX RDF
16	Jooyoung Bae, Wonsik Oh, Jahyun Koo 0003, Bongjin Kim	CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States.	ISSCC	2023	DBLP DOI BibTeX RDF
16	Dongrui Li, Tomomasa Yamasaki, Aarthy Mani, Anh Tuan Do, Niangjun Chen, Bo Wang 0020	LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing.	ISLPED	2023	DBLP DOI BibTeX RDF
16	Sanjoy Kumar Dey, Mukul Sarkar, Shouribrata Chatterjee	Energy efficiency optimization in Strong-Arm latch-based dynamic comparator by capacitor distribution.	ISCAS	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen	Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness.	ITC-Asia	2023	DBLP DOI BibTeX RDF
16	Anwesh Kumar Samal, Sandeep Kumar, Atin Mukherjee 0001	Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications.	ITC-Asia	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Fan Xia, Tianming Ni, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen	A Low Overhead and Double-Node-Upset Self-Recoverable Latch.	ITC-Asia	2023	DBLP DOI BibTeX RDF
16	Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui 0004, Jie Song, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
16	Dake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, Andrew Rittenbach, Pierluigi Nuzzo 0002, Peter A. Beerel	Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP.	ISQED	2023	DBLP DOI BibTeX RDF
16	Javad Bahrami, Mohammad Ebrahimabadi, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi	Special Session: Security Verification & Testing for SR-Latch TRNGs.	VTS	2023	DBLP DOI BibTeX RDF
16	Sam M.-H. Hsiao, Amy H.-Y. Tsai, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen, Herming Chiueh	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs.	ITC	2023	DBLP DOI BibTeX RDF
16	Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder	Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.	RADIOELEKTRONIKA	2023	DBLP DOI BibTeX RDF
16	Yoichi Iizuka, Akihide Maezono, Wataru Saito, Atsushi Yamane, Kazuhiko Takami, Fukashi Morishita	A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System.	A-SSCC	2023	DBLP DOI BibTeX RDF
16	Konstantinos Papathanasiou, Orfeas Panetas-Felouris, Vasileios Kalenteridis, Spyridon Vlassis	Analog Latch for Time-Mode PWM Signal Processing.	MOCAST	2023	DBLP DOI BibTeX RDF
16	Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara	A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
16	Aibin Yan, Kuikui Qian, Tai Song, Zhengfeng Huang, Tianming Ni, Yu Chen, Xiaoqing Wen	A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.	Integr.	2022	DBLP DOI BibTeX RDF
16	Mithilesh Kumar 0008, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya	A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.	Integr.	2022	DBLP DOI BibTeX RDF
16	Seyedehsomayeh Hatefinasab, Akiko Ohata, Alfonso Salinas, Encarnación Castillo, Noel Rodriguez	Highly Reliable Quadruple-Node Upset-Tolerant D-Latch.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Zhongyang Liu, Haineng Zhang, Jianwei Jiang 0001, Yanjie Jia, Yuqiao Xie, Shichang Zou, Zhengxuan Zhang	A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui 0004, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen	Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
16	Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier	A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
16	Mohammad Gholami, Maryam Movahedi, Zaman Amirzadeh	Latch and flip-flop design in QCA technology with minimum number of cells.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
16	Chaudhry Indra Kumar	An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
16	Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel	Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
16	Yingchun Lu, Guangzhen Hu, Jianan Wang, Hao Wang 0169, Liang Yao, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang	A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design.	J. Electron. Test.	2022	DBLP DOI BibTeX RDF
16	Sounak Dutta	Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC.	CoRR	2022	DBLP DOI BibTeX RDF
16	Qiang Zhao 0007, Hanwen Dong, Licai Hao, Xiuying Wang, Chunyu Peng, Xiulong Wu	Novel radiation-hardened latch design for space-radiation environments.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
16	Sang-Wook Kwon, Yong-Seo Koo	Design of capless LDO regulator with low voltage application based ESD protection circuit using SR-latch switch structure.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
16	Federico D'Aniello, Andreas Ott, Andrea Baschirotto	StrongArm-Latch-Based Receiver for Supply Line Embedded Communication.	PRIME	2022	DBLP DOI BibTeX RDF
16	Shao-Chang Huang, Jian-Hsing Lee, Chun-Chih Chen, Ching-Ho Li, Chih-Cherng Liao, Kai-Chieh Hsu, Gong-Kai Lin, Li-Fan Chen, Chien-Wei Wang, Chih-Hsuan Lin, Yeh-Ning Jou, Ke-Horng Chen	Gate Voltages Impacting on Latch-up Measurements.	ICCE-TW	2022	DBLP DOI BibTeX RDF
16	Shogo Takahashi, Kazuteru Namba	A Double Node Upset tolerant SR latch using C-element.	ICCE-TW	2022	DBLP DOI BibTeX RDF
16	Anna V. Álvarez, Matthew R. Devlin, Nicholas D. Naclerio, Elliot W. Hawkes	Jumping on Air: Design and Modeling of Latch-mediated, Spring-actuated Air-jumpers.	IROS	2022	DBLP DOI BibTeX RDF
16	Zhihua Zhu, Songyan Wang, Xiaomei Fan	A Novel Latch-Up-Immune DDSCR Used for 12 V Applications.	IRPS	2022	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui 0004, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001	SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments.	DATE	2022	DBLP DOI BibTeX RDF
16	Aibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen	A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage.	ATS	2022	DBLP DOI BibTeX RDF
16	Kyung-Nam Kim, Won-Bum Lee, Do-Won Kim, Jae-Bok Song	Wearable Arm Strength Supporter based on Adjustable Counterbalance Mechanism using a Spring Latch Module.	UR	2022	DBLP DOI BibTeX RDF
16	Ali Azam, Venkatesh Kommangunta, Jung-Hyun Lee, Kang-Yoon Lee	A Design of Low-Power Dynamic Latch Comparator with Adaptive Power Control for12-bit Charge Sharing SAR ADCs.	ICEIC	2022	DBLP DOI BibTeX RDF
16	Tianyu Li 0001, Badrish Chandramouli, Samuel Madden 0001	Performant Almost-Latch-Free Data Structures Using Epoch Protection.	DaMoN	2022	DBLP DOI BibTeX RDF
16	Harijot Singh Bindra, Jeroen Ponte, Bram Nauta	A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch.	ISSCC	2022	DBLP DOI BibTeX RDF
16	Elizabeth Wyss, Alexander Wittman, Drew Davidson, Lorenzo De Carli	Wolf at the Door: Preventing Install-Time Attacks in npm with Latch.	AsiaCCS	2022	DBLP DOI BibTeX RDF
16	Meysam Asghari, Beomsoo Park, Marino De Jesus Guzman, Nima Maghari	Metalization Enhanced Latch-Based PUF With 1.29% Native Instability.	ISCAS	2022	DBLP DOI BibTeX RDF
16	Aibin Yan, Shukai Song, Jixiang Zhang 0007, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001	Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.	ITC-Asia	2022	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui 0004, Yong Zhou, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
16	Shanshan Liu 0001, Jing Guo 0004, Xiaochen Tang, Pedro Reviriego, Fabrizio Lombardi	A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance.	DFT	2022	DBLP DOI BibTeX RDF
16	Junung Choi, Jaeik Cho, Won Joon Choi, Myungguk Lee, Byungsub Kim	A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links.	ISOCC	2022	DBLP DOI BibTeX RDF
16	Phanidarapu Mounika, Deeksha Verma, Kang-Yoon Lee	An Improved Dynamic Latch Comparator with Low Power Consumption for SAR ADC Applications.	ISOCC	2022	DBLP DOI BibTeX RDF
16	Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara	A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement.	VLSI-DAT	2022	DBLP DOI BibTeX RDF
16	Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek	Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters.	MIXDES	2022	DBLP DOI BibTeX RDF
16	Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka	A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
16	Jing Guo 0004, Shanshan Liu 0001, Xiaohui Su, Chunhua Qi, Fabrizio Lombardi	High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets.	IEEE Trans. Aerosp. Electron. Syst.	2021	DBLP DOI BibTeX RDF
16	Hui Xu, Cong Sun, Le Zhou, Huaguo Liang, Zhengfeng Huang	Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Chao Wang, Yuxin Ji, Ce Ma, Qiao Cai, Liang Qi, Yongfu Li 0002	An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Sandeep Kumar, Atin Mukherjee 0001	A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
16	Aibin Yan, Chaoping Lai, Yinlei Zhang, Jie Cui 0004, Zhengfeng Huang, Jie Song, Jing Guo 0004, Xiaoqing Wen	Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
16	Jérôme Folla Kamdem, Maria Liz Crespo, Wembe Tafo Evariste, Mohammad A. S. Bhuiyan, Andres Cicuttin, Essimbi Zobo Bernard, Mamun Bin Ibne Reaz	A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage.	IET Circuits Devices Syst.	2021	DBLP DOI BibTeX RDF
16	Xinyu Wang, Huaguo Liang, Yanjie Wang, Liang Yao, Yang Guo, Maoxiang Yi, Zhengfeng Huang, Haochen Qi, Yingchun Lu	High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
16	Vikrant Varshney, Avaneesh K. Dubey, Rajendra Kumar Nagaria	Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
16	Hossein Firouzkouhi, Mohammadreza Ashraf	A low-power 10-bit CCP-based pipelined ADC using a multi-level variable current source MDAC and an ultra-low-power double-tail dynamic latch.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
16	Aibin Yan, Aoran Cao, Zhelong Xu, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Hao Wang 0169, Yang Ang, Huaguo Liang, Yiming Ouyang, Tianming Ni	A high-speed and triple-node-upset recovery latch with heterogeneous interconnection.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Di Cao, Jianguo Cui, Yingchun Lu, Huaguo Liang, Yiming Ouyang, Tianming Ni, Zhenmin Li	Design of node separated triple-node-upset self-recoverable latch.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
16	Aibin Yan, Zhihui He, Jun Zhou 0016, Jie Cui 0004, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001	Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
16	Fatemeh Safipoor, Reza Faghih Mirzaee, Mahdi Zare	High-performance quaternary latch and D-Type flip-flop with selective outputs.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Shangjie Pan, Hao Wang 0169, Huaguo Liang, Tianming Ni	LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
16	P. Ashokkumar, M. Sathish Aravindh, A. Venkatesan, M. Lakshmanan 0001	Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit.	CoRR	2021	DBLP BibTeX RDF
16	Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, Mahendra Sakare	Design of a PRBS generator and a serializer using active inductor employed CML latch.	MWSCAS	2021	DBLP DOI BibTeX RDF
16	Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler 0001, Milos Krstic	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops.	LASCAS	2021	DBLP DOI BibTeX RDF
16	Aibin Yan, Kuikui Qian, Jie Cui 0004, Ningning Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen	A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch.	NANOARCH	2021	DBLP DOI BibTeX RDF
16	Jaijeet Roychowdhury	Bistable Latch Ising Machines.	UCNC	2021	DBLP DOI BibTeX RDF
16	Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, Fan Yang, Kunyang Liu, Hirofumi Shinohara	A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
16	Qiao Cai, Yuxin Ji, Ce Ma, Xiaocui Li, Ting Zhou, Jian Zhao 0004, Yongfu Li 0002	An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices.	ISCAS	2021	DBLP DOI BibTeX RDF
16	Aibin Yan, Liang Ding, Chuanbo Shan, Haoran Cai, Xiaofeng Chen, Zhanjun Wei, Zhengfeng Huang, Xiaoqing Wen	TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation.	ISCAS	2021	DBLP DOI BibTeX RDF
16	Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang	A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design.	ITC-Asia	2021	DBLP DOI BibTeX RDF