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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 229 occurrences of 108 keywords
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Results
Found 220 publication records. Showing 220 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Thomas W. Williams |
Design for Testability: The Path to Deep Submicron. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
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14 | Sanjiv Taneja |
DFT Aware Layout - Layout Aware DFT. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
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14 | Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy |
On Improving Defect Coverage of Stuck-at Fault Tests. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Mehrdad Reshadi, Daniel Gajski |
A cycle-accurate compilation algorithm for custom pipelined datapaths. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
NISC, cycle-accurate compiler, scheduling |
14 | Jay Jahangiri, David Abercrombie |
Meeting Nanometer DPM Requirements Through DFT. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
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14 | Azzouz Nezar, Michael Creighton |
System on Chip: Challenges and Design for Manufacturing, invited. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
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14 | Amit K. Agrawal, Rama Chellappa |
Robust ego-motion estimation and 3d model refinement using depth based parallax model. |
ICIP |
2004 |
DBLP DOI BibTeX RDF |
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14 | Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop |
Backend CAD flows for "restrictive design rules". |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
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14 | Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu |
Failure Factor Based Yield Enhancement for SRAM Designs. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
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14 | John Ferguson |
Shifting Methods: Adopting a Design for Manufacture Flow. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
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14 | Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai |
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
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14 | Jitendra Khare |
Memory Yield Improvement - SoC Design Perspective. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
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14 | Robert Madge |
New Test Paradigms for Yield and Manufacturability. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
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14 | Hans T. Heineken, Jitendra Khare |
Test Strategies For a 40Gbps Framer SoC. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
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14 | Martin Schrader, Roderick McConnell |
SoC Design and Test Considerations. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
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14 | Jason Stinson, Stefan Rusu |
A 1.5GHz third generation itanium® 2 processor. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
on-die cache, reliability, test, design methodology, processor |
14 | Andreas Lechner, Andrew Richardson 0001, B. Hermes |
Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
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14 | Neil Harrison |
A Simple via Duplication Tool for Yield Enhancement. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
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14 | Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag |
Design for manufacturability in submicron domain. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
IC technologies, die size minimization, integrated circuit technology, submicron domain, yield, cost model, design for manufacturability, trade-offs, design rules |
14 | Mathew Alexander, K. Sríhari, C. Robert Emerson |
Cost based surface mount PCB design evaluation. |
J. Electron. Test. |
1994 |
DBLP DOI BibTeX RDF |
computer aided process planning, knowledge based framework, Computer aided design, design for manufacture, concurrent engineering |
Displaying result #201 - #220 of 220 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3] |
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