Search results for "MTV"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chia-Ling Lynn Chang, Charles H.-P. Wen	Mining Unreachable Cross-Timeframe State-Pairs for Bounded Sequential Equivalence Checking.	MTV	2008	DBLP DOI BibTeX RDF
1	Subir K. Roy	Top Level SOC Interconnectivity Verification Using Formal Techniques.	MTV	2007	DBLP DOI BibTeX RDF
1	Marc Herbstritt, Vanessa Struve, Bernd Becker 0001	Application of Lifting in Partial Design Analysis.	MTV	2007	DBLP DOI BibTeX RDF
1	Selma Ikiz, Alper Sen 0001	Runtime Verification of k-Mutual Exclusion for SoCs.	MTV	2007	DBLP DOI BibTeX RDF
1	Dam Sunwoo, Hassan Al-Sukhni, Jim Holt, Derek Chiou	Early Models for System-Level Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (eds.)	Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA	MTV	2007	DBLP BibTeX RDF
1	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
1	Wang-Dauh Tseng, Lung-Jen Lee	Reduction of Power Dissipation during Scan Testing by Test Vector Ordering.	MTV	2007	DBLP DOI BibTeX RDF
1	Mark H. Nodine	Automatic Testbench Generation for Rearchitected Designs.	MTV	2007	DBLP DOI BibTeX RDF
1	Andrew DeOrio, Adam Bauserman, Valeria Bertacco	Chico: An On-chip Hardware Checker for Pipeline Control Logic.	MTV	2007	DBLP DOI BibTeX RDF
1	Scott Little, Alper Sen 0001, Chris J. Myers	Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits.	MTV	2007	DBLP DOI BibTeX RDF
1	Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris	A CLP-Based Functional ATPG for Extended FSMs.	MTV	2007	DBLP DOI BibTeX RDF
1	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil	A Scalable Symbolic Simulator for Verilog RTL.	MTV	2007	DBLP DOI BibTeX RDF
1	Wei Qin, Asa Ben-Tzur, Boris Gutkovich	An ADL for Functional Specification of IA32.	MTV	2007	DBLP DOI BibTeX RDF
1	Gaurav Singh 0006, Sandeep K. Shukla	Model Checking Bluespec Specified Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
1	Sandip Ray, Warren A. Hunt Jr.	Mechanized Certification of Secure Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
1	W. Di Palma, Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Automotive Microcontroller End-of-Line Test via Software-Based Methodologies.	MTV	2007	DBLP DOI BibTeX RDF
1	Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.	MTV	2007	DBLP DOI BibTeX RDF
1	Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar	Assertion-Based Modal Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
1	Hyun Sung Kim, D. M. H. Walker	Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits.	MTV	2006	DBLP DOI BibTeX RDF
1		Acknowledgement.	MTV	2006	DBLP DOI BibTeX RDF
1	Hiren D. Patel, Sandeep K. Shukla	Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?.	MTV	2006	DBLP DOI BibTeX RDF
1	Jorge Campos, Hussain Al-Asaad	Circuit Profiling Mechanisms for High-Level {ATPG}.	MTV	2006	DBLP DOI BibTeX RDF
1	Noah Bamford, Rekha Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, Edgar Jimenez	Challenges in System on Chip Verification.	MTV	2006	DBLP DOI BibTeX RDF
1		Preface.	MTV	2006	DBLP DOI BibTeX RDF
1		Workshop Organizing Committee.	MTV	2006	DBLP DOI BibTeX RDF
1	Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese	Workload Slicing for Characterizing New Features in High Performance Microprocessors.	MTV	2006	DBLP DOI BibTeX RDF
1	József Sziray	Test Calculation for Logic and Delay Faults in Digital Circuits.	MTV	2006	DBLP DOI BibTeX RDF	Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic
1	Marc Herbstritt, Bernd Becker 0001, Christoph Scholl 0001	Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs.	MTV	2006	DBLP DOI BibTeX RDF
1	Jianmin Zhang, Ming Yan 0003, Sikun Li	Debug Support for Scalable System-on-Chip.	MTV	2006	DBLP DOI BibTeX RDF
1	Vijay Gangaram, Deepa Bhan, James K. Caldwell	Functional Test Selection for High Volume Manufacturing.	MTV	2006	DBLP DOI BibTeX RDF	Functional Test Sequences, Fault Simulation Acceleration, Untestable Fault Identification, Design Validation, Test Sequence Compaction
1	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	Diagnosing Silicon Failures Based on Functional Test Patterns.	MTV	2006	DBLP DOI BibTeX RDF	fault diagnosis, Silicon debug, design for debug
1	Heon-Mo Koo, Prabhat Mishra 0001, Jayanta Bhadra, Magdy S. Abadir	Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.	MTV	2006	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Letícia Maria Veiras Bolzani, Alberto Manzone, Massimo Osella, Massimo Violante, Matteo Sonza Reorda	Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.	MTV	2006	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (eds.)	Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA	MTV	2006	DBLP BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris	Abstraction and Refinement Techniques in Automated Design Debugging.	MTV	2006	DBLP DOI BibTeX RDF
1	Tamarah Arons, Elad Elster, Terry Murphy, Eli Singerman	Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation.	MTV	2006	DBLP DOI BibTeX RDF	Formal methods, Test generation, Software verification and validation
1		Program Committee.	MTV	2006	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Li-C. Wang (eds.)	Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA	MTV	2005	DBLP BibTeX RDF
1	Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	A Pseudo-Deterministic Functional ATPG based on EFSM Traversing.	MTV	2005	DBLP DOI BibTeX RDF
1	Tobias Schubert 0001, Matthew D. T. Lewis, Bernd Becker 0001	PaMira - A Parallel SAT Solver with Knowledge Sharing.	MTV	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.	MTV	2005	DBLP DOI BibTeX RDF
1		Acknowledgement.	MTV	2005	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Andrea Fedeli, Franco Fummi	On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.	MTV	2005	DBLP DOI BibTeX RDF
1	John Mark Nolen, Rabi N. Mahapatra	A TDM Test Scheduling Method for Network-on-Chip Systems.	MTV	2005	DBLP DOI BibTeX RDF
1	Daniel Große, Ulrich Kühne, Rolf Drechsler	HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.	MTV	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
1	Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt	An Introduction to the Plasma Language.	MTV	2005	DBLP DOI BibTeX RDF
1	Bin Xue, D. M. H. Walker	Is IDDQ Test of Microprocessors Feasible?	MTV	2005	DBLP DOI BibTeX RDF
1		Workshop Organizing Committee.	MTV	2005	DBLP DOI BibTeX RDF
1		Preface.	MTV	2005	DBLP DOI BibTeX RDF
1	David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla	Automated Extraction of Structural Information from SystemC-based IP for Validation.	MTV	2005	DBLP DOI BibTeX RDF
1	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.	MTV	2005	DBLP DOI BibTeX RDF
1		Program Committee.	MTV	2005	DBLP DOI BibTeX RDF
1	Wei Qin, Sharad Malik	A Study of Architecture Description Languages from a Model-based Perspective.	MTV	2005	DBLP DOI BibTeX RDF
1	Marc Herbstritt, Bernd Becker 0001	On SAT-based Bounded Invariant Checking of Blackbox Designs.	MTV	2005	DBLP DOI BibTeX RDF
1	Soohong P. Kim	Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors.	MTV	2005	DBLP DOI BibTeX RDF
1	Jennifer Dworak	An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects.	MTV	2005	DBLP DOI BibTeX RDF
1	Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler	Post-Verification Debugging of Hierarchical Designs.	MTV	2005	DBLP DOI BibTeX RDF
1	Jorge Campos, Hussain Al-Asaad	Search-Space Optimizations for High-Level ATPG.	MTV	2005	DBLP DOI BibTeX RDF
1	Charles H.-P. Wen, Li-C. Wang	Simulation Data Mining for Functional Test Pattern Justification.	MTV	2005	DBLP DOI BibTeX RDF
1	Prabhat Mishra 0001, Heon-Mo Koo, Zhuo Huang	Language-driven Validation of Pipelined Processors using Satisfiability Solvers.	MTV	2005	DBLP DOI BibTeX RDF
1	Brian Kahne, Magdy S. Abadir	Retiming Verification Using Sequential Equivalence Checking.	MTV	2005	DBLP DOI BibTeX RDF
1		Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA	MTV	2004	DBLP BibTeX RDF
1	Michele Borgatti, Andrea Fedeli, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Cristina Marconcini, Graziano Pravadelli	A Verification Methodology for Reconfigurable Systems.	MTV	2004	DBLP DOI BibTeX RDF
1	Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.	MTV	2004	DBLP DOI BibTeX RDF
1	W. Lindsay, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Automatic Test Programs Generation Driven by Internal Performance Counters.	MTV	2004	DBLP DOI BibTeX RDF
1	Xiuli Sun, Jinzhao Wu, Xiaoyu Song, Mila E. Majster-Cederbaum	Formal Specification of an Asynchronous Processor via Action Refinement.	MTV	2004	DBLP DOI BibTeX RDF	pipelines, microprocessors, asynchronous circuits, Action refinement
1	Tobias Schubert 0001, Bernd Becker 0001	PICHAFF2 - A Hierarchical Parallel SAT Solver.	MTV	2004	DBLP DOI BibTeX RDF
1	Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith 0001	Debugging Sequential Circuits Using Boolean Satisfiability.	MTV	2004	DBLP DOI BibTeX RDF
1	M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu	Identification of Gates for Covering all Critical Paths.	MTV	2004	DBLP DOI BibTeX RDF
1	Arkan Abdulrahman, Spyros Tragoudas	Compact ATPG for Concurrent SOC Testing.	MTV	2004	DBLP DOI BibTeX RDF
1		Program Committee.	MTV	2004	DBLP DOI BibTeX RDF
1	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner	Extreme Formal Modeling (XFM) for Hardware Models.	MTV	2004	DBLP DOI BibTeX RDF
1	Prabhat Mishra 0001, Nikil D. Dutt, Yaron Kashai	Functional Verification of Pipelined Processors: A Case Study.	MTV	2004	DBLP DOI BibTeX RDF
1		Workshop Organizing Committee.	MTV	2004	DBLP DOI BibTeX RDF
1	Anshuman S. Nadkarni, Tom Kenville	TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator.	MTV	2004	DBLP DOI BibTeX RDF
1		Acknowledgement.	MTV	2004	DBLP DOI BibTeX RDF
1		Preface.	MTV	2004	DBLP DOI BibTeX RDF
1	Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.	MTV	2004	DBLP DOI BibTeX RDF
1	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
1	Eyal Bin, Laurent Fournier	Micro-Architecture Verification for Microprocessors.	MTV	2004	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda	Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores.	MTV	2004	DBLP DOI BibTeX RDF
1	Marc Herbstritt, Thomas Kmieciak, Bernd Becker 0001	On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification.	MTV	2004	DBLP DOI BibTeX RDF
1	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir	A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.	MTV	2003	DBLP DOI BibTeX RDF
1	Prabhat Mishra 0001, Nikil D. Dutt	A Methodology for Validation of Microprocessors using Equivalence Checking.	MTV	2003	DBLP DOI BibTeX RDF
1	Alexander Klaiber, Sinclair Chau	Automatic Detection of Logic Bugs in Hardware Designs.	MTV	2003	DBLP DOI BibTeX RDF
1	F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya	Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC).	MTV	2003	DBLP DOI BibTeX RDF
1	Mrinal Bose, Mark H. Nodine, William R. Jurasz Jr., Vlad Zavadsky, Arvind Chodavadia, Lincoln R. Nunes	Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification.	MTV	2003	DBLP DOI BibTeX RDF
1	Ohad Shacham, Emmanuel Zarpas	Tuning the VSIDS Decision Heuristic for Bounded Model Checking.	MTV	2003	DBLP DOI BibTeX RDF
1	Wangqi Qiu, D. M. H. Walker	Testing the Path Delay Faults of ISCAS85 Circuit c6288.	MTV	2003	DBLP DOI BibTeX RDF
1	V. V. Iyer	Comparison of Verification Methodologies for Datapath Testing.	MTV	2003	DBLP DOI BibTeX RDF
1	Allon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman	DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms.	MTV	2003	DBLP DOI BibTeX RDF
1		Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA	MTV	2003	DBLP BibTeX RDF
1	Mahesh A. Iyer	A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification.	MTV	2003	DBLP DOI BibTeX RDF
1	Matthew W. Heath, Ian G. Harris	A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture.	MTV	2003	DBLP DOI BibTeX RDF
1	Alessandro Fin, Franco Fummi, Massimo Poncino, Graziano Pravadelli	A SystemC-based Framework for Properties Incompleteness Evaluation.	MTV	2003	DBLP DOI BibTeX RDF
1	Andreas G. Veneris	Fault Diagnosis and Logic Debugging Using Boolean Satisfiability.	MTV	2003	DBLP DOI BibTeX RDF
1	Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi	Utilizing Various ADL Facets for Instruction Level CPU Test.	MTV	2003	DBLP DOI BibTeX RDF
1	Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris	Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.	MTV	2003	DBLP DOI BibTeX RDF

Publications at "MTV"( http://dblp.L3S.de/Venues/MTV )