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Publications at "PATMOS"( http://dblp.L3S.de/Venues/PATMOS )

URL (DBLP): http://dblp.uni-trier.de/db/conf/patmos

Publication years (Num. hits)
2000 (35) 2002 (50) 2003 (69) 2004 (93) 2005 (83) 2006 (71) 2007 (61) 2008 (48) 2009 (41) 2010 (33) 2011 (36) 2012 (25) 2013 (44) 2014 (44) 2015 (27) 2016 (48) 2017 (49) 2018 (41) 2019 (29)
Publication types (Num. hits)
inproceedings(908) proceedings(19)
Venues (Conferences, Journals, ...)
PATMOS(927)
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The graphs summarize 84 occurrences of 72 keywords

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Found 927 publication records. Showing 927 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Christoph Roth, Christian Benkeser, Qiuting Huang Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Lisa J. K. Durbeck, Peter Athanas A global perspective on energy conservation in large data networks. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Manuel Llamas, Mohammad Mashayekhi, Jordi Carrabina, Jody Maick Matos, André Inácio Reis Optimization on cell-library design for digital Application Specific Printed Electronics Circuits. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Nasim Pour Aryan, Nils Heidmann, Martin Wirnshofer, Nico Hellwege, Jonas Pistor, Dagmar Peters-Drolshagen, Georg Georgakos, Steffen Paul, Doris Schmitt-Landsiedel Power efficient digital IC design for a medical application with high reliability requirements. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Bo Wang 0010, Yang Xu 0019, Ralph Hasholzner, Rafael Rosales, Michael Glaß, Jürgen Teich End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Cristian Carmona, Bartomeu Alorda, Miquel A. Ribot Energy consumption savings in ZigBee-based WSN adjusting power transmission at application layer. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Yang Xu 0019, Bo Wang 0010, Jürgen Teich Parametric yield optimization using leakage-yield-driven floorplanning. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Fabian Mischkalla, Wolfgang Müller 0003 Advanced SoC virtual prototyping for system-level power planning and validation. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Chris Dobson, Kurt Rooks, Peter M. Athanas A power-efficient FPGA-based self-adaptive software defined radio. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Felipe Rosa 0001, Luciano Ost, Thiago Raupp da Rosa, Fernando Gehm Moraes, Ricardo Reis 0001 Fast energy evaluation of embedded applications for many-core systems. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Dmitriy Shorin, Armin Zimmermann Formal description of an approach for power consumption estimation of embedded systems. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Axel Reimer, Wolfgang Nebel A methodology for scaling power dissipation values between different FPGAs. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta 0001 Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Eduarda Monteiro, Mateus Grellert, Bruno Zatt, Sergio Bampi Rate-distortion and energy performance of HEVC video encoders. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Syed Abbas Ali Shah, Jan Wagner, Thomas Schuster, Mladen Berekovic A lightweight-system-level power and area estimation methodology for application specific instruction set processors. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001 Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Abdoul Rjoub, Nedal Al Taradeh, Mamoun F. Al-Mistarihi Gate leakage current accurate models for nanoscale MOSFET transistors. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014 Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  BibTeX  RDF
1Minas Dasygenis A distributed VHDL compiler and simulator accessible from the web. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Amir Morad, Leonid Yavits, Ran Ginosar Convex optimization of resource allocation in asymmetric and heterogeneous SoC. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jimmy Tarrillo, Fernanda Lima Kastensmidt Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applications. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan Write scheme for multiple Complementary Resistive Switch (CRS) cells. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Sebastian Hesselbarth, Tim Baumgart, Holger Blume Hardware-assisted power estimation for design-stage processors using FPGA emulation. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Abdoul Rjoub, Areej Ahmad Fast modeling technique for nano scale CMOS inverter and propagation delay estimation. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar Energy management of highly dynamic server workloads in an heterogeneous data center. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Daniel Vidal, Mario Lúcio Côrtes Fast and accurate solution for power estimation and DPA countermeasure design. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Robert Najvirt, Andreas Steininger Equivalence of clock gating and synchronization with applicability to GALS communication. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Miquel L. Alomar, Vicent Canals, Víctor Martínez-Moll, José Luis Rosselló Low-cost hardware implementation of Reservoir Computers. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Sara Vinco, Alessandro Sassone, Davide Lasorsa, Enrico Macii, Massimo Poncino A framework for efficient evaluation and comparison of EES Models. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Panagiotis Chaourani, Ioannis Messaris, Nikolaos Fasarakis, Maria Ntogramatzi, Sotirios K. Goudos, Spiros Nikolaidis 0001 An analytical model for the CMOS inverter. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Giannis Petrousov, Minas Dasygenis A unique network EDA tool to create optimized ad hoc binary to residue number system converters. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Eduardo Chielle, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi Tuning software-based fault-tolerance techniques for power optimization. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Dominik Macko, Katarína Jelemenská, Pavel Cicák Power-efficient power-management logic. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Xin Fan 0003, Steffen Peter, Milos Krstic GALS design of ECC against side-channel attacks - A comparative study. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Haider Alrudainy, Andrey Mokhov, Alex Yakovlev A scalable physical model for Nano-Electro-Mechanical relays. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jesús Sánchez, José Miguel Gil-García, José Antonio Sainz, Miquel Roca 0001, Eugeni Isern 0001 Method to evaluate energy saving techniques in data buses. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Jae Min Kim, Minyong Kim, Sung Woo Chung Application-aware scaling governor for wearable devices. Search on Bibsonomy PATMOS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Alessandro Magnani, Vincenzo d'Alessandro, Niccolò Rinaldi, Massimiliano de Magistris, Klaus Aufinger Dynamic electrothermal macromodeling techniques for thermal-aware design of circuits and systems. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Michael Vonbun, Stefan Wallentowitz, Michael Feilen, Walter Stechele, Andreas Herkersdorf Evaluation of hop count advantages of network-coded 2D-mesh NoCs. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Thomas Polzer, Andreas Steininger Metastability characterization for muller C-elements. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Alex A. Birklykke, Peter Koch 0001, Ramjee Prasad, Lars K. Alminde, Yannick Le Moullec Empirical verification of fault models for FPGAs operating in the subcritical voltage region. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Gregor Nitsche, Kim Grüttner, Wolfgang Nebel Power contracts: A formal way towards power-closure?! Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Massimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino A framework with temperature-aware accuracy levels for battery modeling from datasheets. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Bashir M. Al-Hashimi Hardware reliability of embedded systems: Are we there yet? Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Ewerton Daniel de Lima, Tiago Cariolano de Souza Xavier, Anderson Faustino da Silva, Linnyer Beatrys Ruiz Compiling for performance and power efficiency. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Francesco Beneventi, Andrea Bartolini, Luca Benini On-line thermal emulation: How to speed-up your thermal controller design. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Thomas Ducroux, Germain Haugou, Vincent Risson, Pascal Vivet Fast and accurate power annotated simulation: Application to a many-core architecture. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Davide Zoni, José Flich, William Fornaciari Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel Reliability monitoring of digital circuits by in situ timing measurement. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Andrea Manuzzato, Fabio Campi, Valentino Liberali, Davide Pandini Design methodology for low-power embedded microprocessors. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Vasily G. Moshnyaga An assessment of software lifecycle energy. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Kjell O. Jeppson A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Fabian Mischkalla, Wolfgang Müller 0003 Efficient power Intent validation using loosely-timed simulation models. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Sascha Bischoff, Andreas Hansson 0001, Bashir M. Al-Hashimi Applying of Quality of Experience to system optimisation. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Radu Marculescu Design of future integrated systems: A cyber-physical systems approach. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Nathaniel A. Conos, Saro Meguerdichian, Sheng Wei 0001, Miodrag Potkonjak Maximizing yield in Near-Threshold Computing under the presence of process variation. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Marco Cazzaniga, Patrice Joubert Doriol, Emmanuel Blanc, Valentino Liberali, Davide Pandini Evaluating the impact of substrate on power integrity in industrial microcontrollers. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino Power modeling and characterization of Graphene-based logic gates. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Xinghua Yang, Fei Qiao, Chang Liu, Huazhong Yang Design of variable latency adder based on present and transitional states prediction. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Frank P. Burns, Abdullah Baz, Delong Shang, Alex Yakovlev Variability analysis of self-timed SRAM robustness. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Carlos Gomez, Julien DeAntoni, Frédéric Mallet Power consumption analysis using multi-view modeling. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Thomas Polzer, Andreas Steininger SET propagation in micropipelines. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Christoph W. Kessler, Nicolas Melot, Patrick Eitschberger, Jörg Keller 0001 Crown scheduling: Energy-efficient resource allocation, mapping and discrete frequency scaling for collections of malleable streaming tasks. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013 Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  BibTeX  RDF
1Georgios Tzimpragos, Christoforos Kachris, Dimitrios Soudris, Ioannis Tomkos Automatic implementation of low-complexity QC-LDPC encoders. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Waqaas Munawar, Jian-Jia Chen Peak power demand analysis and reduction by using battery buffers for monotonic controllers. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Marc Pons 0001, Jean-Luc Nagel, Daniel Séverac, Marc-Nicolas Morgan, Daniel Sigg, Pierre-François Rüedi, Christian Piguet Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Lars Kosmann, Daniel Lorenz 0002, Axel Reimer, Wolfgang Nebel Enabling energy-aware design decisions for behavioural descriptions containing black-box IP-components. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Georgios Tzimpragos, Christoforos Kachris, Dimitrios Soudris, Ioannis Tomkos Automatic implementation of low-complexity QC-LDPC encoders. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Maurício Altieri, Warody Lombardi, Diego Puschini, Suzanne Lesecq Coupled voltage and frequency control for DVFS management. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Vishwa Goudar, Zhi Ren, Paul Brochu, Qibing Pei, Miodrag Potkonjak Optimizing the configuration and control of a novel human-powered energy harvesting system. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1H. Ye, Lionel Lacassagne, Joël Falcou, Daniel Etiemble, Laurent Cabaret, O. Florent High level tranforms toreduce energy consumption of signal and image processing operators. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Filippo Casamassima, Elisabetta Farella, Luca Benini Power saving policies for multipurpose WBAN. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Junghyun Lee, Yungseon Eo An efficient eye-diagram determination technique for multi-coupled interconnect lines. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1José L. Ayala, Delong Shang, Alex Yakovlev (eds.) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Daniele Bortolotti, Davide Rossi, Andrea Bartolini, Luca Benini A variation tolerant architecture for ultra low power multi-processor cluster. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Juergen Karmann, Wolfgang Ecker The semantic of the power intent format UPF: Consistent power modeling from system level to implementation. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Pascal Benoit, Lionel Torres Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Alessandro Sassone, Massimo Petricca, Massimo Poncino, Enrico Macii A fully standard-cell delay measurement circuit for timing variability detection. Search on Bibsonomy PATMOS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Juan Núñez 0002, Maria J. Avedillo, José M. Quintana Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Reef Eilers, Malte Metzdorf, Sven Rosinger, Domenik Helms, Wolfgang Nebel Phase Space Based NBTI Model. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Chenxi Ni, Ziyad Al Tarawneh, Gordon Russell 0002, Alexandre V. Bystrov Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Axel Reimer, Lars Kosmann, Daniel Lorenz 0002, Wolfgang Nebel Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jakob Lechner, Robert Najvirt A Generic Architecture for Robust Asynchronous Communication Links. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Salomon Beer, Ran Ginosar An Extended Metastability Simulation Method for Synchronizer Characterization. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Maryam Triki, Yanzhi Wang, Ahmed Chiheb Ammari, Massoud Pedram Dynamic Power Management of a Computer with Self Power-Managed Components. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jatin N. Mistry, John Biggs, James Myers, Bashir M. Al-Hashimi, David Flynn dRail: A Novel Physical Layout Methodology for Power Gated Circuits. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Daniel Lorenz 0002, Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel Non-invasive Power Simulation at System-Level with SystemC. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Sven Rosinger, Wolfgang Nebel Sleep-Transistor Based Power-Gating Tradeoff Analyses. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Ghaith Tarawneh, Alex Yakovlev Adaptive Synchronization for DVFS Applications. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera A Standard Cell Optimization Method for Near-Threshold Voltage Operations. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Eyal-Itzhak Nave, Ran Ginosar TCP Window Based DVFS for Low Power Network Controller SoC. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Jorge Juan, Julian Viejo, Manuel J. Bellido Network Time Synchronization: A Full Hardware Approach. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Thomas Polzer, Andreas Steininger, Jakob Lechner Muller C-Element Metastability Containment. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs Direct Statistical Simulation of Timing Properties in Sequential Circuits. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero Low Power Implementation of Trivium Stream Cipher. Search on Bibsonomy PATMOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
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