Search results for "SDRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf	Buffer allocation for advanced packet segmentation in Network Processors.	ASAP	2008	DBLP DOI BibTeX RDF
14	Wei Chen 0009, Hongyi Lu, Li Shen 0007, Zhiying Wang 0003, Nong Xiao	DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture.	EUC (2)	2008	DBLP DOI BibTeX RDF
14	Ankush Varma, Bruce L. Jacob, Eric Debes, Igor Kozintsev, Paul Klein	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
14	Ke Ning, David R. Kaeli	External memory page remapping for embedded multimedia systems.	LCTES	2007	DBLP DOI BibTeX RDF	memory coloring, memory page remapping, embedded systems, memory controllers
14	Nathan Woods	Integrating FPGAs in high-performance computing: the architecture and implementation perspective.	FPGA	2007	DBLP DOI BibTeX RDF	compute acceleration, high-performance computinghigh-performance computing, reconfigurable computing, co-processor
14	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
14	Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Kai-Yuan Jan	A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform.	ASP-DAC	2007	DBLP DOI BibTeX RDF
14	Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura	Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories.	ESTIMedia	2007	DBLP DOI BibTeX RDF
14	Puranjoy Bhattacharya	Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile Computing.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Amilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst	FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs.	DAC	2007	DBLP DOI BibTeX RDF
14	Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe	DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.	FPL	2006	DBLP DOI BibTeX RDF
14	Tianzhou Chen, Wei Hu 0001, Yi Lian	Power-Efficient Microkernel of Embedded Operating System on Chip.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	power-efficient, microkernel, embedded operating system
14	Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah	An Energy Characterization Framework for Software-Based Embedded Systems.	ESTIMedia	2006	DBLP DOI BibTeX RDF
14	Tianzhou Chen, Hu Wei, Lian Yi	Microkernel of Embedded Operating System in SRAM.	IWNAS	2006	DBLP DOI BibTeX RDF
14	Tim Barrett, Sumit D. Mediratta, Taek-Jun Kwon, Ravinder Singh, Sachit Chandra, Jeff Sondeen, Jeffrey T. Draper	A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability.	ISCAS	2006	DBLP DOI BibTeX RDF
14	D. Scott McCaulay, Matthew R. Link, George W. Turner, David Y. Hancock, Maria Morris, Craig A. Stewart	Poster reception - Powerful new research computing system available via the TeraGrid.	SC	2006	DBLP DOI BibTeX RDF
14	Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho	A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications.	DAC	2006	DBLP DOI BibTeX RDF	DVD-RAM, SATA, WSR, CMOS, optical storage
14	Anand Ramachandran, Margarida F. Jacome	Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Artur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan	A Real-Time Streaming Memory Controller.	DATE	2005	DBLP DOI BibTeX RDF
14	Zhichun Zhu, Zhao Zhang 0010	A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.	HPCA	2005	DBLP DOI BibTeX RDF
14	Paul Willmann, Hyong-youb Kim, Scott Rixner, Vijay S. Pai	An Efficient Programmable 10 Gigabit Ethernet Network Interface Card.	HPCA	2005	DBLP DOI BibTeX RDF
14	Amilcar do Carmo Lucas, Rolf Ernst	An Image Processor for Digital Film.	ASAP	2005	DBLP DOI BibTeX RDF	weak-programing, stream-based architechture, digital .lm, recon.gurable, FPGA
14	Dongbing Pu, Changrui Du, Zhezhou Yu, Chunguang Zhou	Design of Face Recognition Door Manager System Based on DSP.	EUC	2005	DBLP DOI BibTeX RDF
14	Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo	Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.	PDCAT	2005	DBLP DOI BibTeX RDF
14	Paul Marchal, Francky Catthoor, Davide Bruni, Luca Benini, José Ignacio Gómez, Luis Piñuel	Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
14	Claude Tadonki, José D. P. Rolim	An Analytical Model for Energy Minimization.	WEA	2004	DBLP DOI BibTeX RDF
14	Min Li, Xiaobo Wu, Menglian Zhao, Hui Wang, Xiaolang Yan	Heterogeneous Grid Computing for Energy Constrained Mobile Device.	EUC	2004	DBLP DOI BibTeX RDF
14	Peter A. Boyle, Dong Chen 0005, Norman H. Christ, Michael A. Clark, Saul D. Cohen, Zhihua Dong, Alan Gara, Bálint Joó, Chulwoo Jung, Ludmila A. Levkova, Xiaodong Liao, Guofeng Liu, Robert D. Mawhinney, Shigemi Ohta, Konstantin Petrov, Tilo Wettig, Azusa Yamaguchi, Calin Cristian	QCDOC: A 10 Teraflops Computer for Tightly-Coupled Calculations.	SC	2004	DBLP DOI BibTeX RDF
14	Jörg E. Vollrath	Testing and Characterization of SDRAMs.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
14	Filip Traugott, Kim Andersson, Andreas Löfgren, Lennart Lindh	Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm.	DSD	2003	DBLP DOI BibTeX RDF
14	Betty Prince	Application Specific DRAMs Today.	MTDT	2003	DBLP DOI BibTeX RDF
14	Hyung Gyu Lee, Sungyuep Nam, Naehyuck Chang	Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs.	ISQED	2003	DBLP DOI BibTeX RDF
14	Michael S. Warren, Chris L. Fryer, M. Patrick Goda	The Space Simulator: Modeling the Universe from Supernovae to Cosmology.	SC	2003	DBLP DOI BibTeX RDF	price/performance, N-body, cluster, Beowulf, astrophysics
14	Anand Ramachandran, Margarida F. Jacome	Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing.	DAC	2003	DBLP DOI BibTeX RDF	streaming memory, low power, configurability, design space exploration, media processing, scratch-pad, energy delay product
14	Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001	Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.	FPL	2002	DBLP DOI BibTeX RDF
14	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
14	Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen	Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
14	Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu	An FPGA-based re-configurable functional tester for memory chips.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits
14	Stephen J. Bellis, William P. Marnane	A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.	FPL	2000	DBLP DOI BibTeX RDF
14	Lars Friebe, Yoshikazu Yabe, Masato Motomura	A Study of Channeled DRAM Memory Architectures.	ICCD	2000	DBLP DOI BibTeX RDF
14	Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai	BRAINS: A BIST Compiler for Embedded Memories.	DFT	2000	DBLP DOI BibTeX RDF
14	Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis	Algorithmic foundations for a parallel vector access memory system.	SPAA	2000	DBLP DOI BibTeX RDF
14	Daniel P. Van der Velde, Ad J. van de Goor	Designing a Memory Module Tester.	MTDT	1999	DBLP DOI BibTeX RDF
14	Jörg E. Vollrath	Tutorial: Characterizing SDRAMS.	MTDT	1999	DBLP DOI BibTeX RDF
14	Jim Anderson	Integrated probe card/interface solutions for specific test applications.	ITC	1998	DBLP DOI BibTeX RDF