Search results for "SEU"

Hits ?▲	Authors	Title	Venue	Year	Link
19	Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger	A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.	ATS	2017	DBLP DOI BibTeX RDF
19	Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel	Reliable SEU monitoring and recovery using a programmable configuration controller.	FPL	2017	DBLP DOI BibTeX RDF
19	Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria	Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories.	NEWCAS	2017	DBLP DOI BibTeX RDF
19	Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer	Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation.	IOLTS	2017	DBLP DOI BibTeX RDF
19	Holger Michel, Hipólito Guzmán-Miranda, Alexander Dörflinger, Harald Michalik, Miguel Aguirre Aguirre Echánove	SEU fault classification by fault injection for an FPGA in the space instrument SOPHI.	AHS	2017	DBLP DOI BibTeX RDF
19	Israel C. Lopes, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin	SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA.	LATS	2017	DBLP DOI BibTeX RDF
19	Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco	SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core.	LATS	2017	DBLP DOI BibTeX RDF
19	Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria	Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
19	Ahmed S. Sajit, Michael A. Turi	SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells.	CCWC	2017	DBLP DOI BibTeX RDF
19	Ligia Eliana Setenareski	Fiscalização da neutralidade da rede e seu impacto na evolução da internet.		2017	RDF
19	Pilin Junsangsri, Jie Han 0001, Fabrizio Lombardi	Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.	Integr.	2016	DBLP DOI BibTeX RDF
19	Wei Wei 0034, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi	A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
19	Qingyu Chen, Haibin Wang, Li Chen 0001, Lixiang Li 0001, Xing Zhao, Rui Liu 0011, Mo Chen, Xuantian Li	An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
19	Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco	Towards an efficient SEU effects emulation on SRAM-based FPGAs.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
19	Chung Tah Chua, Hock Guan Ong, Kevin Sanchez, Philippe Perdu, Chee Lip Gan	Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
19	Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xuejun Li	An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
19	Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro	Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
19	Saqib A. Khan, Shi-Jie Wen, Sanghyeon Baeg	Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
19	Saqib A. Khan, Shi-Jie Wen, Sanghyeon Baeg	Erratum: Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation [IEICE Electronics Express Vol. 13 (2016) No. 17 pp. 20160627].	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
19	Tomas Vanat, Filip Krizek, Jozef Ferencei, Hana Kubátová	Comparing proton and neutron induced SEU cross section in FPGA.	DDECS	2016	DBLP DOI BibTeX RDF
19	Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper	SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.	FPGA	2016	DBLP DOI BibTeX RDF
19	Michail S. Vavouras, Christos-Savvas Bouganis	Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs.	ReConFig	2016	DBLP DOI BibTeX RDF
19	Afef Kchaou, W. El Hadj Youssef, Rached Tourki, Fraidy Bouesse, Pablo Ramos, Raoul Velazco	A deep analysis of SEU consequences in the internal memory of LEON3 processor.	LATS	2016	DBLP DOI BibTeX RDF
19	Hiroki Ueno, Kazuteru Namba	Construction of a soft error (SEU) hardened Latch with high critical charge.	DFT	2016	DBLP DOI BibTeX RDF
19	Meng Li 0004, Ye Wang 0014, Michael Orshansky	A Monte Carlo simulation flow for SEU analysis of sequential circuits.	DAC	2016	DBLP DOI BibTeX RDF
19	Zhengfeng Huang, Huaguo Liang, Sybille Hellebrand	A High Performance SEU Tolerant Latch.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
19	Cécile Weulersse, Florent Miller, Thierry Carrière, R. Mangeret	Prediction of proton cross sections for SEU in SRAMs and SDRAMs using the METIS engineer tool.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
19	Daniela Munteanu, Jean-Luc Autran	SEU sensitivity of Junctionless Single-Gate SOI MOSFETs-based 6T SRAM cells investigated by 3D TCAD simulation.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
19	Guohe Zhang, Yunlin Zeng, Feng Liang 0001, Kebin Chen	A novel SEU tolerant SRAM data cell design.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
19	Gilles Gasiot, Dimitri Soussan, Jean-Luc Autran, Victor Malherbe, Philippe Roche	Muons and thermal neutrons SEU characterization of 28nm UTBB FD-SOI and Bulk eSRAMs.	IRPS	2015	DBLP DOI BibTeX RDF
19	Vanessa Vargas, Pablo Ramos, Raoul Velazco, Jean-François Méhaut, Nacer-Eddine Zergainoh	Evaluating SEU fault-injection on parallel applications implemented on multicore processors.	LASCAS	2015	DBLP DOI BibTeX RDF
19	Sushil Kumar, Srivatsan Chellappa, Lawrence T. Clark	Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU.	ISCAS	2015	DBLP DOI BibTeX RDF
19	Adrian Evans, Enrico Costenaro, Arkady Bramnik	Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF).	IOLTS	2015	DBLP DOI BibTeX RDF
19	Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco	Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis.	IOLTS	2015	DBLP DOI BibTeX RDF
19	Katerina Katsarou, Yiorgos Tsiatouhas	Soft error immune latch under SEU related double-node charge collection.	IOLTS	2015	DBLP DOI BibTeX RDF
19	Clement Champeix, Nicolas Borrel, Jean-Max Dutertre, Bruno Robisson, Mathieu Lisart, Alexandre Sarafianos	SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology.	DFTS	2015	DBLP DOI BibTeX RDF
19	Clara Vianna Prado	Digital natives versus digital immigrants: interpretive analysis of differences in the use of ICT in their daily lives and their perception of education in the present (Nativos digitais versus imigrantes digitais: análise interpretativista das diferenças no uso das TIC em seu cotidiano e sua percepção do ensino na atualidade).		2015	RDF
19	Reza Omidi Gosheblagh, Karim Mohammadi	Seu-Secure Parity Prediction Multiplier on SRAM-Based FPGAs.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
19	Yibai He, Shuming Chen	Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology.	Sci. China Inf. Sci.	2014	DBLP DOI BibTeX RDF
19	Reza Omidi Gosheblagh, Karim Mohammadi	Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators.	J. Electron. Test.	2014	DBLP DOI BibTeX RDF
19	I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng	A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
19	Reza Omidi Gosheblagh, Karim Mohammadi	Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
19	Peng Li, Minxuan Zhang, Weicheng Zhang, Zhenyu Zhao, Chao Song, Hua Fan	Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
19	Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001	A hybrid non-volatile SRAM cell with concurrent SEU detection and correction.	DATE	2014	DBLP DOI BibTeX RDF
19	Zhengfeng Huang	A high performance SEU-tolerant latch for nanoscale CMOS technology.	DATE	2014	DBLP DOI BibTeX RDF
19	Patricio Lopez Gonzalez, Vicente Baena Lecuyer, Hipólito Guzmán-Miranda, Javier Barrientos Rojas, Miguel A. Aguirre	On the modelling of SEU effects on spread spectrum wireless systems.	WiSEE	2014	DBLP DOI BibTeX RDF
19	Igor Villata, Unai Bidarte, Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001	Fast and accurate SEU-tolerance characterization method for Zynq SoCs.	FPL	2014	DBLP DOI BibTeX RDF
19	Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener	A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor.	FCCM	2014	DBLP DOI BibTeX RDF
19	Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai	Reconfiguration network design for SEU recovery in FPGAs.	ISCAS	2014	DBLP DOI BibTeX RDF
19	Kejun Wu, Hoda Pahlevanzadeh, Peng Liu 0016, Qiaoyan Yu	A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability.	ISCAS	2014	DBLP DOI BibTeX RDF
19	Vanessa Vargas, Pablo Ramos, Wassim Mansour, Raoul Velazco, Nacer-Eddine Zergainoh, Jean-François Méhaut	Preliminary results of SEU fault-injection on multicore processors in AMP mode.	IOLTS	2014	DBLP DOI BibTeX RDF
19	Luca Cassano, Hipólito Guzmán-Miranda, Miguel A. Aguirre	Early assessment of SEU sensitivity through untestable fault identification.	IOLTS	2014	DBLP DOI BibTeX RDF
19	Katerina Katsarou, Yiorgos Tsiatouhas	Double node charge sharing SEU tolerant latch design.	IOLTS	2014	DBLP DOI BibTeX RDF
19	Wassim Mansour, Pablo Ramos, Rafic A. Ayoubi, Raoul Velazco	SEU fault-injection at system level: Method, tools and preliminary results.	LATW	2014	DBLP DOI BibTeX RDF
19	Evaldo Carlos Fonseca Pereira, Odair Lelis Goncalez, Rafael Galhardo Vaz, Claudio Antonio Federico, Thiago Hanna Both, Gilson Inácio Wirth	The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory.	LATW	2014	DBLP DOI BibTeX RDF
19	Anna Vaskova, A. Fabregat, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda	Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques.	LATW	2014	DBLP DOI BibTeX RDF
19	Wei Wei 0034, Fabrizio Lombardi, Kazuteru Namba	Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.	DFT	2014	DBLP DOI BibTeX RDF
19	Thiago Baesso Procaci, Sean W. M. Siqueira, Leila Cristina Vasconcelos de Andrade	Encontrando Usuários Confiáveis em Comunidades Online de Perguntas e Respostas Através de seu Índice de Confiança.	SBSI	2014	DBLP DOI BibTeX RDF
19	Marcio Juliato, Catherine H. Gebotys	A Quantitative Analysis of a Novel SEU-Resistant SHA-2 and HMAC Architecture for Space Missions Security.	IEEE Trans. Aerosp. Electron. Syst.	2013	DBLP DOI BibTeX RDF
19	Michelangelo Grosso, Hipólito Guzmán-Miranda, Miguel A. Aguirre	Exploiting Fault Model Correlations to Accelerate SEU Sensitivity Assessment.	IEEE Trans. Ind. Informatics	2013	DBLP DOI BibTeX RDF
19	Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka	Fault tolerant system design and SEU injection based testing.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
19	Wassim Mansour, Raoul Velazco	SEU Fault-Injection in VHDL-Based Processors: A Case Study.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
19	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Alessio Gravina, Valentino Liberali, Marcello Mancini, Paolo Musazzi, Sandro Pastore, Matteo Sassi, Gabriele Sorrenti	A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs.	J. Electron. Test.	2013	DBLP DOI BibTeX RDF
19	Zhen Gao 0001, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao 0001, Jing Wang 0001, Juan Antonio Maestro	Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
19	Cinzia Bernardeschi, Luca Cassano, Mario G. C. A. Cimino, Andrea Domenici	GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs.	J. Syst. Archit.	2013	DBLP DOI BibTeX RDF
19	Jose Luis Nunes, João Carlos Cunha, Raul Barbosa, Mário Zenha Rela	Evaluating Xilinx SEU Controller Macro for fault injection.	DSN	2013	DBLP DOI BibTeX RDF
19	Konstantin O. Petrosyants, Igor A. Kharitonov, D. A. Popov	Coupled TCAD-SPICE simulation of parasitic BJT effect on SOI CMOS SRAM SEU.	EWDTS	2013	DBLP DOI BibTeX RDF
19	Greicy Marques-Costa, Wassim Mansour, Fabrice Pancher, Raoul Velazco, Alain Bui, Devan Sohier	Optimization of a self-converging algorithm at assembly level to improve SEU fault-tolerance.	LASCAS	2013	DBLP DOI BibTeX RDF
19	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001	SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA.	ARC	2013	DBLP DOI BibTeX RDF
19	Cinzia Bernardeschi, Luca Cassano, Andrea Domenici	Formal approaches to SEU testing in FPGAs.	AHS	2013	DBLP DOI BibTeX RDF
19	Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato	High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA.	ISQED	2013	DBLP DOI BibTeX RDF
19	Eugenio de Oliveira Simonetto, Mauri Leodir Löbler	Simulação Computacional para Avaliação de Cenários sobre a Reciclagem de Resíduos Sólidos Urbanos e o seu Impacto na Economia de Energia.	SBSI	2013	DBLP DOI BibTeX RDF
19	Yaqing Chi, Yibai He, Bin Liang, Chunmei Hu	A Scan Chain Based SEU Test Method for Microprocessors.	NCCET	2013	DBLP DOI BibTeX RDF
19	Pietro Cunha Dolci	Modelo para avaliar a influência dos investimentos em TI na governança da cadeia de suprimentos e o seu desempenho.		2013	RDF
19	Sidnei Roberto Feliciano da Silva	As relações do intraempreendedorismo e da IT Fashion com a consumerização de TI e seu impacto no desempenho pessoal e na governança de TI.		2013	RDF
19	Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi	Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
19	Wenhui Yang, Zhen Gao 0001, Xiang Chen 0007, Ming Zhao 0001, Jing Wang 0001	Residue code based low cost SEU-tolerant fir filter design for OBP satellite communication systems.	EURASIP J. Wirel. Commun. Netw.	2012	DBLP DOI BibTeX RDF
19	Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta	Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity.	J. Circuits Syst. Comput.	2012	DBLP DOI BibTeX RDF
19	Zhongming Wang, Zhibin Yao, Hongxia Guo, Min Lv	Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs.	Sci. China Inf. Sci.	2012	DBLP DOI BibTeX RDF
19	Karine Castellani-Coulié, Hassen Aziza, Gilles Micolau, Jean-Michel Portal	Optimization of SEU Simulations for SRAM Cells Reliability under Radiation.	J. Electron. Test.	2012	DBLP DOI BibTeX RDF
19	Naifeng Jing, Ju-Yueh Lee, Zhe Feng 0002, Weifeng He, Zhigang Mao, Lei He 0001	SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
19	Seokjoong Kim, Matthew R. Guthaus	SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
19	Seokjoong Kim, Matthew R. Guthaus	Dynamic voltage scaling for SEU-tolerance in low-power memories.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
19	Abbas Mohammadi 0001, Mojtaba Ebrahimi, Alireza Ejlali, Seyed Ghassem Miremadi	SCFIT: A FPGA-based fault injection technique for SEU fault model.	DATE	2012	DBLP DOI BibTeX RDF
19	Jing Zhou, Zengrong Liu, Lei Chen 0010, Shuo Wang, Zhiping Wen 0001, Lishuai Wu, Xun Chen	Study of an Automated Precise SEU Fault Injection Technique.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
19	Fang Dong 0001, Junzhou Luo, Jiahui Jin, Yanhao Wang, Yanmin Zhu	Performance evaluation and analysis of SEU Cloud Computing Platform - Using general benchmarks and real world AMS application.	SMC	2012	DBLP DOI BibTeX RDF
19	Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi	Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration.	FPT	2012	DBLP DOI BibTeX RDF
19	Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita	SEU tolerant robust memory cell design.	IOLTS	2012	DBLP DOI BibTeX RDF
19	Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Anna Vaskova, Luis Entrena, Joaquín Rivas-Abalo, Alberto Martín-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego	SEU sensitivity of robust communication protocols.	IOLTS	2012	DBLP DOI BibTeX RDF
19	Norhuzaimin Julai, Alexandre Yakovlev, Alexandre V. Bystrov	Error detection and correction of single event upset (SEU) tolerant latch.	IOLTS	2012	DBLP DOI BibTeX RDF
19	Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou	A low power memory cell design for SEU protection against radiation effects.	AHS	2012	DBLP DOI BibTeX RDF
19	Wassim Mansour, Raoul Velazco	SEU fault-injection in VHDL-based processors: A case study.	LATW	2012	DBLP DOI BibTeX RDF
19	Neil J. Perrins, Alistair A. McEwan	SEU Protection for High-Reliability Flash File Systems.	CPA	2012	DBLP BibTeX RDF
19	Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita	SEU Tolerant Robust Latch Design.	VDAT	2012	DBLP DOI BibTeX RDF
19	Josmaria Lima Ribeiro de Oliveira	Estudo comparado entre bibliotecários, contadores e analistas de tecnologia da informação: processo de profissionalização e seu efeito na formação, atuação e reconhecimento profissional.		2012	RDF
19	Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh	SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
19	Martin Straka, Jan Kastil, Zdenek Kotásek	SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems.	DSD	2011	DBLP DOI BibTeX RDF
19	Naifeng Jing, Ju-Yueh Lee, Zhe Feng 0002, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He 0001	Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.	FPL	2011	DBLP DOI BibTeX RDF
19	Aitzan Sari, Mihalis Psarakis	Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips.	FPT	2011	DBLP DOI BibTeX RDF
19	Luca Sterpone, Fabio Margaglia, Markus Köster, Jens Hagemeyer, Mario Porrmann	Analysis of SEU effects in partially reconfigurable SoPCs.	AHS	2011	DBLP DOI BibTeX RDF