Search results for "SIMD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Chunjiang J. Duanmu, M. Omair Ahmad, M. N. S. Swamy, Ali M. Shatnawi	A vector based fast block motion estimation algorithm for implementation on SIMD architectures.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
29	Patricio Bulic, Veselko Gustin	Macro Extension for SIMD Processing.	Euro-Par	2001	DBLP DOI BibTeX RDF
29	Antonio Gentile, D. Scott Wills	Impact of Pixel per Processor Ratio on Embedded SIMD Architectures.	ICIAP	2001	DBLP DOI BibTeX RDF
29	Kazumaro Aoki, Fumitaka Hoshino, Tetsutaro Kobayashi, Hiroaki Oguro	Elliptic Curve Arithmetic Using SIMD.	ISC	2001	DBLP DOI BibTeX RDF
29	Hongzheng Li, Hongchi Shi	A Parallel Algorithm for Volume Projections on SIMD Mesh-Connected Computers.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	volume projection, data distribution and redistribution, parallel algorithm, matrix decomposition, mesh-connected computer
29	Per Larsson-Edefors	A Miniature Serial-Data SIMD Architecture.	EUROMICRO	1998	DBLP DOI BibTeX RDF
29	Vivek Garg, David E. Schimmel	CCSIMD: A Concurrent Communication and Computation Framework for SIMD Machines.	PCRCW	1997	DBLP DOI BibTeX RDF
29	Martin C. Herbordt, Owais Kidwai, Charles C. Weems	Preprototyping SIMD Coprocessors Using Virtual Machine Emulation and Trace Compilation.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
29	Janusz Sosnowski	Testing and Diagnostics of SIMD Arrays.	EUROMICRO	1997	DBLP DOI BibTeX RDF
29	Mattias Johannesson	FFTs on a Linear SIMD Arrat.	Euro-Par	1995	DBLP DOI BibTeX RDF
29	Ross A. Bagley, Philip A. Wilsey, Nael B. Abu-Ghazaleh	Composing Functional Unit Blocks for Efficient Interpretation of MIMD Code Sequences on SIMD Processors.	CONPAR	1994	DBLP DOI BibTeX RDF
29	Rod Fatoohi	Performance Analysis of Four SIMD Machines.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF	DAP, CM-2
29	Todd C. Marek	A new simulator workbench for comparing SIMD processing element architectures.	ACM Southeast Regional Conference	1992	DBLP DOI BibTeX RDF
29	Luc Bougé, Patrick Garda	Towards a Semantic Approach to SIMD Architectures and their Languages.	Semantics of Systems of Concurrent Processes	1990	DBLP DOI BibTeX RDF
29	Ted Sztnabski	A fiber optic hypermesh for SIMD/MIMD machines.	SC	1990	DBLP DOI BibTeX RDF
29	Richard Hughey, Andrea Di Blas	Finding the Next Computational Model: Experience with the UCSC Kestrel.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers
29	Ali El-Moursy, Ahmed El-Mahdy 0002, Hisham El-Shishiny	An efficient in-place 3D transpose for multicore processors with software managed memory hierarchy.	IFMT	2008	DBLP DOI BibTeX RDF	3D transpose, vector programming, parallel programming, SIMD, multi-core systems
29	Robert L. Bocchino Jr., Vikram S. Adve	Vector LLVA: a virtual vector instruction set for media processing.	VEE	2006	DBLP DOI BibTeX RDF	virtual instruction sets, multimedia, SIMD, vector
29	Andrea Di Blas, David M. Dahle, Mark Diekhans, Leslie Grate, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Mark Kendrick, Francisco J. Mesa-Martinez, David Pease, Eric Rice, Angela Schultz, Don Speck, Richard Hughey	The UCSC Kestrel Parallel Processor.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	VLSI system design, image processing, Parallel processing, high performance computing, computer architecture, systolic array, SIMD, DNA, computational chemistry, biological sequence analysis
29	V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj	Performance Analysis of Embedded Media Applications in Newer ARM Architectures.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
29	Raymond Hoare, Shen Chih Tung, Katrina Werger	An 88-Way Multiprocessor within an FPGA with Customizable Instructions.	IPDPS	2004	DBLP DOI BibTeX RDF	FPGA, Architecture, Parallelism, DSP, SIMD
29	Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh	Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	multimedia, computer graphics, reconfigurable architectures, SIMD, hierarchical trees
29	James B. Armstrong, Muthucumaru Maheswaran, Mitchell D. Theys, Howard Jay Siegel, Mark A. Nichols, Kenneth H. Casey	Parallel Image Correlation: Case Study to Examine Trade-Offs in Algorithm-to-Machine Mappings.	J. Supercomput.	1998	DBLP DOI BibTeX RDF	nCUBE 2, PASM prototype, scalability, SIMD, MIMD, Intel Paragon, image correlation, mixed-mode, MasPar MP-1
29	Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek	A Parallel Multimedia Processor for Macroblock Based Compression Standards.	ICIP (2)	1997	DBLP DOI BibTeX RDF	parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1
29	Xiaobo Li 0001	Parallel Algorithms for Hierarchical Clustering and Cluster Validity.	IEEE Trans. Pattern Anal. Mach. Intell.	1990	DBLP DOI BibTeX RDF	alignment network, pattern matrix, proximity matrix, parallel algorithms, computational complexity, computational complexity, parallel processing, computerised pattern recognition, hierarchical clustering, cluster validity, SIMD machines, parallel memory system
26	Ping Wang, Fei Wen, Paul V. Gratz, Alex Sprintson	SIMD-Matcher: A SIMD-based Arbitrary Matching Framework.	ACM Trans. Archit. Code Optim.	2022	DBLP DOI BibTeX RDF
26	Kenny Peou	Computing Tools for HPDA: a Cache-Oblivious and SIMD Approach. (Outils de calculs pour le HPDA: approche Cache-Oblivious et SIMD).		2021	RDF
26	Muhammad Ashfaq, Rubing Huang, Michael Omari	FSCS-SIMD: An efficient implementation of Fixed-Size-Candidate-Set adaptive random testing using SIMD instructions.	ISSRE	2020	DBLP DOI BibTeX RDF
26	Florian Lemaitre, Arthur M. Hennequin, Lionel Lacassagne	How to speed Connected Component Labeling up with SIMD RLE algorithms.	WPMVP@PPoPP	2020	DBLP DOI BibTeX RDF
26	Régis Pierrard, Laurent Cabaret, Jean-Philippe Poli, Céline Hudelot	SIMD-based Exact Parallel Fuzzy Dilation Operator for Fast Computing of Fuzzy Spatial Relations.	WPMVP@PPoPP	2020	DBLP DOI BibTeX RDF
26	Tom Plano, Jeremy Buhler	Scheduling Irregular Dataflow Pipelines on SIMD Architectures.	WPMVP@PPoPP	2020	DBLP DOI BibTeX RDF
26	Florian Lemaitre	Tracking haute fréquence pour architectures SIMD : optimisation de la reconstruction LHCb. (High frequency tracking for SIMD architectures : optimization of the LHCb reconstruction).		2019	RDF
26	Arthur M. Hennequin, Ian Masliah, Lionel Lacassagne	Designing efficient SIMD algorithms for direct Connected Component Labeling.	PPoPP	2019	DBLP DOI BibTeX RDF
26	Christopher Rodrigues, Amarin Phaosawasdi, Peng Wu 0001	SIMDization of Small Tensor Multiplication Kernels for Wide SIMD Vector Processors.	WPMVP@PPoPP	2018	DBLP DOI BibTeX RDF
26	Florian Lemaitre, Benjamin Couturier, Lionel Lacassagne	Small SIMD Matrices for CERN High Throughput Computing.	WPMVP@PPoPP	2018	DBLP DOI BibTeX RDF
26	Adrien Cassagne, Olivier Aumage, Denis Barthou, Camille Leroux, Christophe Jégo	MIPP: a Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard.	WPMVP@PPoPP	2018	DBLP DOI BibTeX RDF
26	Ali Hassan El Moussawi	SIMD-aware Word Length Optimization for Floating-point to Fixed-point Conversion targeting Embedded Processors. (Optimisation de la largeur des mots pour la conversion de virgule flottante en virgule fixe ciblant des processeurs embarqués avec support SIMD).		2016	RDF
26	Lionel Lacassagne, Laurent Cabaret, Daniel Etiemble, Farouk Hebache, Andrea Petreto	A new SIMD iterative connected component labeling algorithm.	WPMVP@PPoPP	2016	DBLP DOI BibTeX RDF
26	Angela Pohl, Biagio Cosenza, Mauricio Alvarez-Mesa, Chi Ching Chi, Ben H. H. Juurlink	An evaluation of current SIMD programming models for C++.	WPMVP@PPoPP	2016	DBLP DOI BibTeX RDF
26	Diego Caballero	SIMD@OpenMP: a programming model approach to leverage SIMD features.		2015	RDF
26	Matthias Boettcher, Bashir M. Al-Hashimi, Mbou Eyole, Giacomo Gabrielli, Alastair Reid 0001	Advanced SIMD: Extending the reach of contemporary SIMD architectures.	DATE	2014	DBLP DOI BibTeX RDF
26	Serge Guelton, Joël Falcou, Pierrick Brunet	Exploring the vectorization of python constructs using pythran and boost SIMD.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	James C. Brodman, Dmitry Babokin, Ilia Filippov, Peng Tu	Writing scalable SIMD programs with ISPC.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	Johannes Hofmann 0001, Jan Treibig, Georg Hager, Gerhard Wellein	Comparing the performance of different x86 SIMD instruction sets for a medical imaging application on modern multi- and manycore chips.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	John McCutchan, Haitao Feng, Nicholas D. Matsakis, Zachary Anderson, Peter Jensen	A SIMD programming model for dart, javascript, and other dynamically typed scripting languages.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	Roland Leißa, Immanuel Haffner, Sebastian Hack	Sierra: a SIMD extension for C++.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	Lionel Lacassagne, Daniel Etiemble, Ali Hassan Zahraee, Alain Dominguez, Pascal Vezolle	High level transforms for SIMD and low-level computer vision algorithms.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	Pierre Estérie, Joel Falcou, Mathias Gaunard, Jean-Thierry Lapresté	Boost.SIMD: generic programming for portable SIMDization.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
26	Yaohua Wang, Shuming Chen, Jianghua Wan, Jiayuan Meng, Kai Zhang 0023, Wei Liu 0013, Xi Ning	A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments.	HPCA	2013	DBLP DOI BibTeX RDF
26	Minsoo Rhu, Mattan Erez	Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation.	ISCA	2013	DBLP DOI BibTeX RDF
26	Xinmin Tian, Hideki Saito 0001, Milind Girkar, Serguei Preis, Sergey Kozhukhov, Aleksei G. Cherkasov, Clark Nelson, Nikolay Panchenko, Robert Geva	Compiling C/C++ SIMD Extensions for Function and Loop Vectorizaion on Multicore-SIMD Processors.	IPDPS Workshops	2012	DBLP DOI BibTeX RDF
26	Jiayuan Meng, Jeremy W. Sheaffer, Kevin Skadron	Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth.	IPDPS	2012	DBLP DOI BibTeX RDF
26	Guy-Alain Lusilao-Zodi, Mqhele E. Dlodlo, Gerhard de Jager, Keith L. Ferguson	RRB-SIMD: RTP Rate-Based SIMD Protocol for Media Streaming Applications over the Internet.	CNSR	2011	DBLP DOI BibTeX RDF
26	Libo Huang, Zhiying Wang 0003	SV: Enhancing SIMD Architectures via Combined SIMD-Vector Approach.	ICA3PP (1)	2010	DBLP DOI BibTeX RDF
26	Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst	RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications.	J. Embed. Comput.	2006	DBLP BibTeX RDF
26	Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki	A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF
26	Paul Rodríguez V., Marios S. Pattichis, Ramiro Jordan	Computational SIMD framework: split-radix SIMD-FFT algorithm, derivation, implementation and performance.	DSP	2002	DBLP DOI BibTeX RDF
26	Patrick Lincoln, Narciso Martí-Oliet, José Meseguer 0001, Livio Ricciulli	Compiling Rewriting onto SIMD and MIMD/SIMD Maschines.	PARLE	1994	DBLP DOI BibTeX RDF
26	Yixin Shou, Robert A. van Engelen	Automatic SIMD vectorization of chains of recurrences.	ICS	2008	DBLP DOI BibTeX RDF	chains of recurrences, short vector simd, vectorization, ILP
26	Albert Danysh, Dimitri Tan	Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	data-path design, multiply-accumulate, Booth, Wallace, unsigned, multimedia, VLSI, Parallel, MAC, SIMD, vector, fixed-point, multiplier, high-speed arithmetic, signed, integer
26	Raghav Bhaskar, Pradeep K. Dubey, Vijay Kumar, Atri Rudra	Efficient galois field arithmetic on SIMD architectures.	SPAA	2003	DBLP DOI BibTeX RDF	correcting codes, reed-solomon error, SIMD, rijndael, galois field arithmetic, bit slicing
26	Claude Limousin, Julien Sébot, Alexis Vartanian, Nathalie Drach-Temam	Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor.	ICS	2001	DBLP DOI BibTeX RDF	SIMD extensions, cache memories, parallel rendering, data prefetching, SMT, applications specific architectures
26	Krishna Kumar Rangan, Nael B. Abu-Ghazaleh, Philip A. Wilsey	A Distributed Multiple-SIMD Intelligent Memory.	ICPP	2001	DBLP DOI BibTeX RDF	Processing (ICPP '01)-in-memory architectures, PPIM, M-SIMD, ppim-sim, Data-intensive applications
26	Hao Chen, Nicholas S. Flann, Daniel W. Watson	Parallel Genetic Simulated Annealing: A Massively Parallel SIMD Algorithm.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	traveling salesperson, Genetic algorithms, parallel algorithms, simulated annealing, combinatorial optimization, error correcting codes, SIMD, hybrid methods, massive parallelism
26	Srinivasan Balakrishnan, Soumitra Kumar Nandy	Arbitrary Precision Arithmetic - SIMD Style.	VLSI Design	1998	DBLP DOI BibTeX RDF	Packed Addition, Arbitrary Precision, SIMD, Integer Arithmetic
26	Tsan-sheng Hsu, Vijaya Ramachandran, Nathaniel Dean	Implementation of parallel graph algorithms on a massively parallel SIMD computer with virtual processing.	IPPS	1995	DBLP DOI BibTeX RDF	massively parallel SIMD computer, virtual processing, parallel algorithms, graph theory, virtual machines, graph algorithms, parallel graph algorithms, MasPar MP-1
26	Wei-Ming Lin, Viktor K. Prasanna, K. Wojtek Przytula	Algorithmic Mapping of Neural Network Models onto Parallel SIMD Machines.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	parallel SIMD machines, programmable massively parallel computers, nonzero synaptic weights, parallel processing, graph theory, routing algorithm, neural nets, processor array, data transfers, neurons, neural network models, matrix operations, graph theoretic approach, algorithmic mapping, vector operations
26	André Seznec	A New Interconnection Network for SIMD Computers: The Sigma Network.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	BPC (bit permute complement permutation), reverse Omega network, Sigma network, compression, expansion, Omega network, vector processing, SIMD computer
26	David Nassimi, Sartaj Sahni	Optimal BPC Permutations on a Cube Connected SIMD Computer.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	cube connected SIMD computer, complexity, BPC permutation
26	Michael R. Warpenburg, Leah J. Siegel	SIMD Image Resampling.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Algorithms, image processing, parallel programming, interpolation, resampling, SIMD machine, rectification, PASM
26	Angela Y. Wu, Azriel Rosenfeld	SIMD Machines and Cellular d-Graph Automata.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	parallel processing, Cellular automata, formal models, SIMD machines
26	Howard Jay Siegel	The Theory Underlying the Partitioning of Permutation Networks.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	Cube network, Illiac, multiple-SIMD (MSIMD) machines, partitionable computer systems, PM21 network, parallel processing, interconnection networks, SIMD machines, permutation networks, Shuffle-Exchange network
24	John A. Tsakok	Faster incoherent rays: Multi-BVH ray stream tracing.	High Performance Graphics	2009	DBLP DOI BibTeX RDF	MBVH, MBVH RS, QBVH, incoherent rays, ray traversal, real time, ray tracing, global illumination, path tracing
24	Hyungwook Park, Paul A. Fishwick	A fast hybrid time-synchronous/event approach to parallel discrete event simulation of queuing networks.	WSC	2008	DBLP DOI BibTeX RDF
24	Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.	DATE	2007	DBLP DOI BibTeX RDF
24	Chun Chen 0002, Jaewook Shin, Shiva Kintali, Jacqueline Chame, Mary W. Hall	Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study.	IPDPS	2007	DBLP DOI BibTeX RDF
24	Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridharan Iyengar, Leiguang Gong, Hiroshi Inoue, Hideaki Komatsu, Vadim Sheinin, Shahrokh Daijavad	Accelerating Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor.	ICME	2007	DBLP DOI BibTeX RDF
24	Tirath Ramdas, Gregory K. Egan, David Abramson 0001, Kim K. Baldridge	Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	thread-level parallelism, content-addressable memory, vector processing, address generation, data-level parallelism
24	Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen 0007	Hardware Support for Arithmetic Units of Processor with Multimedia Extension.	MUE	2007	DBLP DOI BibTeX RDF
24	Yoshiki Ohshima	Semantics and Performance Considerations of Kedama, a GUI-based Massively Parallel Programming Language.	C5	2006	DBLP DOI BibTeX RDF
24	Dorit Nuzman, Richard Henderson	Multi-platform Auto-vectorization.	CGO	2006	DBLP DOI BibTeX RDF
24	Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu 0001, Tong Chen 0001, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind	Optimizing Compiler for the CELL Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
24	Akihito Takahashi, Stanislav Sedukhin	Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor.	HPCC	2005	DBLP DOI BibTeX RDF
24	Xizhen Xu, Sotirios G. Ziavras, Tae-Gyu Chang	An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method.	EUC	2005	DBLP DOI BibTeX RDF
24	Stefan Kral, Franz Franchetti, Juergen Lorenz, Christoph W. Ueberhuber, Peter Wurzinger	FFT Compiler Techniques.	CC	2004	DBLP DOI BibTeX RDF
24	Jie Han 0001, Pieter Jonker	From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers.	ICPR (3)	2004	DBLP DOI BibTeX RDF
24	Jesús Corbal, Roger Espasa, Mateo Valero	Three-dimensional memory vectorization for high bandwidth media memory systems.	MICRO	2002	DBLP DOI BibTeX RDF
24	Bogdan J. Falkowski	Calculation of Walsh transform on MasPar computer.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
24	Jae-dong Lee, Kenneth E. Batcher	Minimizing Communication in the Bitonic Sort.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	minimizing communication, parallel computing, sorting, sorting networks, omega networks, Bitonic sorting
24	Yi-Shin Tung, Chia-Chiang Ho, Ja-Ling Wu	MMX-Based DCT and MC Algorithms for Real-Time Pure Software MPEG Decoding.	ICMCS, Vol. 1	1999	DBLP DOI BibTeX RDF	Pattern-Based IDCT, MPEG, Video Compression, MMX
24	Philippe Hoogvorst, Ronan Keryell, Philippe Matherat, Nicolas Paris	POMP or How to Design a Massively Parallel Machine with Small Developments.	PARLE (1)	1991	DBLP DOI BibTeX RDF
24	Samuel A. Fineberg, Thomas L. Casavant, Howard Jay Siegel	Experimental analysis of communication/data-conditional aspects of a mixed-mode parallel architecture via synthetic computations.	SC	1990	DBLP DOI BibTeX RDF	PASM
21	Chunyang Gou, Georgi Kuzmanov, Georgi Gaydadjiev	SAMS multi-layout memory: providing multiple views of data to boost SIMD performance.	ICS	2010	DBLP DOI BibTeX RDF
21		Single Instruction Multiple Data (SIMD) Parallelism.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
21	Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch	An Enhanced DMA Controller in SIMD Processors for Video Applications.	ARCS	2009	DBLP DOI BibTeX RDF
21	Fouzhan Hosseini, Amir Fijany, Saeed Safari, Ryad Chellali, Jean-Guy Fontaine	Real-Time Parallel Implementation of SSD Stereo Vision Algorithm on CSX SIMD Architecture.	ISVC (1)	2009	DBLP DOI BibTeX RDF
21	Markus Billeter, Ola Olsson, Ulf Assarsson	Efficient stream compaction on wide SIMD many-core architectures.	High Performance Graphics	2009	DBLP DOI BibTeX RDF	stream compaction, GPGPU, CUDA, parallel sorting, prefix sum
21	Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala	A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	performance, design
21	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors.	IEEE Trans. Multim.	2008	DBLP DOI BibTeX RDF
21	Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata	New SIMD instructions set for image processing applications enhancement.	ICIP	2008	DBLP DOI BibTeX RDF