Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Donatella Sciuto, Luciano Baresi, Cristiana Bolchini	Software methodologies for VHDL code static analysis based on flow graphs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	João Paulo Teixeira 0001, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos	VHDL fault simulation for defect-oriented test and diagnosis of digital ICs.	EURO-DAC	1996	DBLP DOI BibTeX RDF
29	Ralf Reetz, Thomas Kropf	A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL.	Formal Methods Syst. Des.	1995	DBLP DOI BibTeX RDF
29	Sowmitri Swamy, Arthur Molin, Burt Covnot	OO-VHDL: Object-Oriented Extensions to VHDL.	Computer	1995	DBLP DOI BibTeX RDF
29	Brian Dickinson	VHDL '92: The new features of the VHDL hardware description language : Jean-Michel Bergé, Alain Fonkoua, Serge Maginot and Jacques Rouillard Kluwer Academic Publishers, Dortrecht, The Netherlands (1993) ISBN 0 7923 9356 2, Dfl 180.00, £65.50, pp214.	Microprocess. Microsystems	1995	DBLP DOI BibTeX RDF
29	Alain Vachoux, J. M. Bergé	VHDL-A: Analog and Mixed-Mode Extensions to VHDL.	EUROSIM	1995	DBLP BibTeX RDF
29	Marie-Claude Cebelieu	Utilisation de macro blocs en synthèse VHDL. (Macro block handling in VHDL synthesis).		1995	RDF
29	Serafín Olcoz, Luis Entrena, Luis Berrojo	An effective system development environment based on VHDL prototyping.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	D. Galán, Carlos Jesús Jiménez-Fernández, Angel Barriga, Santiago Sánchez-Solano	VHDL package for description of fuzzy logic controllers.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Eugen Röhm	Latest benchmark results of VHDL simulation systems.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Laurent Arditi, Hélène Collavizza	Towards verifying VHDL descriptions of processors.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Cristian A. Giumale, Hilary J. Kahn	A core information model of VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli	Timing constraint specification and synthesis in behavioral VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Steve Hodgson, Zak Shaar, Andy Smith	A high performance VHDL simulator for large systems design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel	Debugging of behavioral VHDL specifications by source level emulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Ronald B. Stewart	LibQA - library quality assurance for VHDL synthesis and simulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Jan Andersson	A DSP ASIC design flow based on VHDL and ASIC-emulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Polen Kission, Hong Ding, Ahmed Amine Jerraya	VHDL based design methodology for hierarchy and component re-use.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Ludwig Schwoerer, Matthias Lück, Hartmut Schröder	Integration of VHDL into a system design environment.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Markus Schütz	How to efficiently build VHDL testbenches.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Joris van den Hurk, Edwin Dilling	System level design, a VHDL based approach.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	John Willis, Zhiyuan Li 0001, Tsang-Puu Lin	Use of embedded scheduling to compile VHDL for effective parallel simulation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Vincent Moser, Hans Peter Amann, Pascal Nussbaum, Fausto Pellandini	Generating VHDL-A - like models using ABSynth.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Wolfgang Ecker, Manfred Huber	VHDL-based communication and synchronization synthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Karlheinz Agsteiner, Dieter Monjau, Sören Schulze	Object-oriented high-level modeling of system components for the generation of VHDL code.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Andrea Finotello, Maurizio Paolini	The VHDL based design of the MIDA MPEG1 audio decoder.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Ronald Herrmann, Thomas Reielts	Verification of a production cell using an automatic verification environment for VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Guido Schumacher, Wolfgang Nebel	Inheritance concept for signals in object-oriented extensions to VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Peter T. Breuer, Natividad Martínez Madrid	A native process algebra for VHDL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Mirella Mastretti	VHDL quality: synthesizability, complexity and efficiency evaluation.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Viktor Preis, Renate Henftling, Markus Schütz, Sabine März-Rössel	A reuse scenario for the VHDL-based hardware design flow.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Dominique Rodriguez	Description et simulation mixte analogique-numérique: analyse de VHDL analogique, réalisation d'un simulateur mixte. (Mixed analog-digital description and simulation: Study of analog VHDL. Implementation of a mixed simulator).		1994	RDF
29	Johannes Helbig, Rainer Schlör, Werner Damm, Gert Döhmen, Peter Kelb	VHDL/S - integrating statecharts, timing diagrams, and VHDL.	Microprocess. Microprogramming	1993	DBLP DOI BibTeX RDF
29	John Van Tassel	Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant.		1993	RDF
29	Pierre Wodey	Compilation de programmes VHDL en vue de l'évaluation de testabilité d'équipements digitaux. (Compilation of VHDL programs for analysing testability of asynchronous digital devices).		1993	RDF
29	Michael Gasteier, Norbert Wehn, Manfred Glesner	Synthesis of complex VHDL operators.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Péter Keresztes, Istvan Agotai	The concept of superprocesses for high-level synthesis and their VHDL modelling.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Manzer Masud, Maddu Karunaratne	Test generation based on synthesizable VHDL descriptions.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Antonio J. Acosta 0001, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas	Modeling of real bistables in VHDL.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Alain Debreil, Philippe Oddo	Synchronous designs in VHDL.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Wolfgang Ecker	Using VHDL for HW/SW co-specification.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Werner Damm, Bernhard Josko, Rainer Schlör	A net-based semantics for VHDL.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Jean Paul Calvez, Dominique Heller, P. Bakowski	Functional-level synthesis with VHDL.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Peter Gutberlet, Wolfgang Rosenstiel	Interface specification and synthesis for VHDL processes.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Serafín Olcoz, José Manuel Colom	Toward a formal semantics of IEEE Std. VHDL 1076.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Mohamed Belhadj, Roderick McConnell, Paul Le Guernic	A framework for macro- and micro-time to model VHDL attributes.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Veronique Pla, Jean François Santucci, Norbert Giambiasi	On the modeling and testing of VHDL behavioral descriptions of sequential circuits.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski	Synthesis of functions and procedures in behavioral VHDL.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Hsiao-Ping Juan, Nancy D. Holmes, Smita Bakshi, Daniel D. Gajski	Top-down modeling of RISC processors in VHDL.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Jens Müller 0008, Heinrich Krämer	Analysis of multi-process VHDL specifications with a Petri net model.	EURO-DAC	1993	DBLP DOI BibTeX RDF
29	Thierry Collette	Architecture et validation comportementale en VHDL d'un calculateur parallèle dédié à la vision. (Architecture and VHDL behavioural validation of a parallel processor dedicated to computer vision).		1992	RDF
28	Marc Schlickling, Markus Pister 0002	Semi-automatic derivation of timing models for WCET analysis.	LCTES	2010	DBLP DOI BibTeX RDF	vhdl, worst-case execution time, hard real-time
28	Maher E. Rizkalla, Paul Salama, Mohamed El-Sharkawy 0001, Modukuri Sushmitha	Hardware Implementation of Block-based Motion Estimation for Real Time Applications.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	fast search algorithms, exhaustive search algorithm, VHDL implementation, VLSI, motion estimation, finite state machine
28	B. Lorente, Raul Aragonés, Joan Oliver, Carles Ferrer 0001	Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development.	SCSC	2007	DBLP BibTeX RDF	smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS
28	David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda	Symbolic Model Checking of Analog/Mixed-Signal Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language
28	Iouliia Skliarova	Self-correction of FPGA-Based Control Units.	ICESS	2005	DBLP DOI BibTeX RDF	Self-correcting finite state machines, specification in VHDL, Hamming codes
28	Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel	FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	cluster maintenance algorithm, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field Programmable Gate Arrays), Mobile ad-hoc networks
28	Amjad Hajjar, Tom Chen 0001	Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria.	ISQED	2002	DBLP DOI BibTeX RDF	Behavioral Model Verification, VHDL, Stopping Criteria
28	M. Ernst, Michael Jung 0002, Felix Madlener, Sorin A. Huss, Rainer Blümel	A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n).	CHES	2002	DBLP DOI BibTeX RDF	$ mathbb {GF}(2^n)$ arithmetic, Karatsuba multiplication, VHDL model generator, coprocessor synthesis, FPGA hardware acceleration, Atmel FPSLIC platform, Elliptic Curve cryptography
28	Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee	Load Balancing and Workload Minimization Of Overlapping Parallel Tasks.	ICPP	1997	DBLP DOI BibTeX RDF	parallel compiled VHDL simulation, load balancing, task assignment, VLSI-CAD, fine grained parallelism
28	Michael Yang, Ahmed N. Tantawy	A design methodology for protocol processors.	FTDCS	1995	DBLP DOI BibTeX RDF	protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols
28	Md. Rezwanul Ahsan, Muhammad Ibn Ibrahimy, Othman Omran Khalifa	VHDL Modelling of Fixed-point DWT for the Purpose of EMG Signal Denoising.	CICSyN	2011	DBLP DOI BibTeX RDF	Daubechies, VHDL, DWT, Fixed-point, Electromyography
28	Hassan Bajwa, Isaac G. Macwan, Vignesh Veerapandian, Xinghao Chen 0005	VHDL Implementation of High-Performance and Dynamically Configures Multi-port Cache Memory.	ITNG	2010	DBLP DOI BibTeX RDF	Dynamically configured memory, Multi-port Cache Architecture, VHDL, SRAM
28	Hongli Tian, Shuo Shi, Jun Zhang, Hongdong Zhao	Controllable Arbitrary Integer Frequency Divider Based on VHDL.	JCAI	2009	DBLP DOI BibTeX RDF	50% duty cycle, frequency divider, FPGA, VHDL, CPLD
28	Günter Knittel, Stefanie Mayer, Christian Rothländer	Integrating Logic Analyzer Functionality into VHDL Designs.	ReConFig	2008	DBLP DOI BibTeX RDF	On-chip logic analyzer, FPGA, VHDL
28	Nikolay Kostadinov, Anelia Ivanova	A VHDL training model of a processor.	CompSysTech	2007	DBLP DOI BibTeX RDF	CPLD implementation, VHDL model, processor, instruction set
28	Christophe Paoli, Marie-Laure Nivet, Jean François Santucci, Antoine Campana	Path-Oriented Test Data Generation of Behavioral VHDL Description.	DELTA	2002	DBLP DOI BibTeX RDF	High level design validation, simulation-based validation, software testing techniques, constraint logic programming language, VHDL
28	Jochen Mades, Manfred Glesner	Regularization of hierarchical VHDL-AMS models using bipartite graphs.	DAC	2002	DBLP DOI BibTeX RDF	structural solvability, regularization, bipartite graphs, VHDL-AMS, DAEs
28	Marco Rona, Gunter Krampl	Modelling SoC devices for virtual test using VHDL.	DATE	2001	DBLP DOI BibTeX RDF	VHDL
28	Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius, Giedrius Majauskas	Two approaches for developing generic components in VHDL.	DATE	2001	DBLP DOI BibTeX RDF	VHDL
28	Raoul Velazco, Régis Leveugle, Oscar Calvo	Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results.	DFT	2001	DBLP DOI BibTeX RDF	fuzzy logic, VHDL, fault injection
28	Fabian Vargas 0001, Alexandre M. Amory	Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transient-fault tolerant VHDL descriptions, area overhead analysis, reliable complex circuit design, harmful environments, reliability level, early-estimation, maximum area overhead, redundancy insertion, application minimum reliability requirement, FT-PRO tool, fault tolerant computing, redundancy, microprocessor, integrated circuit design, circuit CAD, CAD tool, transients, reliability estimation, memory elements, integrated circuit reliability, fault-tolerant circuit
28	Venkatram Krishnaswamy, Prithviraj Banerjee	Parallel Compiled Event Driven VHDL Simulation.	International Conference on Supercomputing	1998	DBLP DOI BibTeX RDF	VHDL
28	Rick Miller	VHDL-based EDA Tool Implementation with Java.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Hardware/Software CoSynthesis, Java, VHDL
28	Nihal J. Godambe, C.-J. Richard Shi	Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS.	VTS	1997	DBLP DOI BibTeX RDF	behavioral level noise modeling, jitter simulation, mixed-signal hardware description language, phase-locked loops, voltage-controlled oscillator, power supply noise, phase noise, VHDL-AMS, catastrophic faults, top down design, integrated circuit noise
28	Cristian A. Giumale, Hilary J. Kahn	Information Models of VHDL.	DAC	1995	DBLP DOI BibTeX RDF	VHDL
28	Peter Zepter, Thorsten Grötker, Heinrich Meyr	Digital Receiver Design Using VHDL Generation from Data Flow Graphs.	DAC	1995	DBLP DOI BibTeX RDF	VHDL
28	Neal S. Stollon, John D. Provence	Measures of Syntactic Complexity for Modeling Behavioral VHDL.	DAC	1995	DBLP DOI BibTeX RDF	VHDL
28	Loïc Vandeventer, Jean François Santucci	Speeding up test pattern generation from behavioral VHDL descriptions containing several processes.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Petru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng	Synthesis of VHDL concurrent processes.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuominen	A VHDL-based bus model for multi-PCB system design.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Jan Madsen, Jens P. Brage	Modeling shared variables in VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Juan Carlos Calderón, Enric Corominas, José M. Tapia, Luis París	Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	France Mendez	VHDL and cyclic corrector codes.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Christopher A. Ryan, Joseph G. Tront	VHDL switch level fault simulation.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Mario Stefanoni	Static analysis for VHDL model evaluation.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Felix Nicoli, Laurence Pierre	Formal verification of behavioral VHDL specifications: a case study.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto	A process algebra interpretation of a verification oriented overlanguage of VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Ronald Herrmann, Hergen Pargmann	Computing binary decision diagrams for VHDL data types.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	David B. Bernstein, Werner van Almsick, Wilfried Daehn	Distributed simulation for structural VHDL netlists.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Maurizio Valle, Daniele D. Caviglia, Marco Cornero, Giovanni Nateri, Luciano Briozzo	A VHDL-based design methodology: the design experience of a high performance ASIC chip.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Loïc Vandeventer, Jean François Santucci	Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructs.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Luis Sánchez Fernández 0001, Peter T. Breuer, Carlos Delgado Kloos	Proof theory and a validation condition generator for VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	Prolog, VHDL
28	Gert Döhmen	Petri nets as intermediate representation between VHDL and symbolic transition systems.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Karen Hale	Automotive databus simulation using VHDL.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Kevin O'Brien, Serge Maginot	Non-reversible VHDL source-source encryption.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Walling R. Cyre, Jim Armstrong, M. Manek-Honcharik, Alexander J. Honcharik	Generating VHDL models from natural language descriptions.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
28	Wolfgang Ecker, Manfred Glesner, Andreas Vombach	Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Wolfgang Müller 0003, Egon Börger, Uwe Glässer	The semantics of behavioral VHDL '93 descriptions.	EURO-DAC	1994	DBLP BibTeX RDF	VHDL
28	Peter Gutberlet, Wolfgang Rosenstiel	Timing preserving interface transformations for the synthesis of behavioral VHDL.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL